//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// File name "fifo_control.v" ////
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//// File name "fifo_control.v" ////
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//// ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README ////
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//// All additional information is avaliable in the README ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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//
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//
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//
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/* FIFO_CONTROL module provides read/write address and status generation for
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/* FIFO_CONTROL module provides read/write address and status generation for
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FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
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FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
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`include "constants.v"
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`include "constants.v"
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`ifdef FPGA
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`ifdef FPGA
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// fifo design in FPGA will be synchronous
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// fifo design in FPGA will be synchronous
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`ifdef SYNCHRONOUS
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`ifdef SYNCHRONOUS
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`else
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`else
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`define SYNCHRONOUS
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`define SYNCHRONOUS
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`endif
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`endif
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`endif
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`endif
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`include "timescale.v"
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|
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module FIFO_CONTROL
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module FIFO_CONTROL
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(
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(
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rclock_in,
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rclock_in,
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wclock_in,
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wclock_in,
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renable_in,
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renable_in,
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wenable_in,
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wenable_in,
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reset_in,
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reset_in,
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flush_in,
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flush_in,
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almost_full_out,
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almost_full_out,
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full_out,
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full_out,
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almost_empty_out,
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almost_empty_out,
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empty_out,
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empty_out,
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waddr_out,
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waddr_out,
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raddr_out,
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raddr_out,
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rallow_out,
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rallow_out,
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wallow_out
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wallow_out
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);
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);
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// address length parameter - depends on fifo depth
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// address length parameter - depends on fifo depth
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parameter ADDR_LENGTH = 7 ;
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parameter ADDR_LENGTH = 7 ;
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|
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// independent clock inputs - rclock_in = read clock, wclock_in = write clock
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// independent clock inputs - rclock_in = read clock, wclock_in = write clock
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input rclock_in, wclock_in;
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input rclock_in, wclock_in;
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|
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// enable inputs - read address changes on rising edge of rclock_in when reads are allowed
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// enable inputs - read address changes on rising edge of rclock_in when reads are allowed
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// write address changes on rising edge of wclock_in when writes are allowed
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// write address changes on rising edge of wclock_in when writes are allowed
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input renable_in, wenable_in;
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input renable_in, wenable_in;
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|
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// reset input
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// reset input
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input reset_in;
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input reset_in;
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|
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// flush input
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// flush input
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input flush_in ;
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input flush_in ;
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// almost full and empy status outputs
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// almost full and empy status outputs
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output almost_full_out, almost_empty_out;
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output almost_full_out, almost_empty_out;
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|
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// full and empty status outputs
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// full and empty status outputs
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output full_out, empty_out;
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output full_out, empty_out;
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|
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// read and write addresses outputs
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// read and write addresses outputs
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output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
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output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
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|
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// read and write allow outputs
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// read and write allow outputs
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output rallow_out, wallow_out ;
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output rallow_out, wallow_out ;
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|
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// read address register
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// read address register
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reg [(ADDR_LENGTH - 1):0] raddr ;
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reg [(ADDR_LENGTH - 1):0] raddr ;
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|
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// write address register
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// write address register
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reg [(ADDR_LENGTH - 1):0] waddr;
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reg [(ADDR_LENGTH - 1):0] waddr;
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assign waddr_out = waddr ;
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assign waddr_out = waddr ;
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|
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// grey code registers
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// grey code registers
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// grey code pipeline for write address
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// grey code pipeline for write address
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reg [(ADDR_LENGTH - 1):0] wgrey_minus1 ; // one before current grey coded write address
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reg [(ADDR_LENGTH - 1):0] wgrey_minus1 ; // one before current grey coded write address
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reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current grey coded write address
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reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current grey coded write address
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reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next grey coded write address
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reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next grey coded write address
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|
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// next write gray address calculation - bitwise xor between address and shifted address
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// next write gray address calculation - bitwise xor between address and shifted address
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wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
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wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
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// grey code pipeline for read address
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// grey code pipeline for read address
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reg [(ADDR_LENGTH - 1):0] rgrey_minus2 ; // two before current
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reg [(ADDR_LENGTH - 1):0] rgrey_minus2 ; // two before current
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reg [(ADDR_LENGTH - 1):0] rgrey_minus1 ; // one before current
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reg [(ADDR_LENGTH - 1):0] rgrey_minus1 ; // one before current
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reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
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reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
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|
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// next read gray address calculation - bitwise xor between address and shifted address
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// next read gray address calculation - bitwise xor between address and shifted address
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wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
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wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
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// FFs for registered empty and full flags
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// FFs for registered empty and full flags
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reg empty ;
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reg empty ;
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reg full ;
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reg full ;
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|
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// almost_empty and almost_full tag - implemented as latches
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// almost_empty and almost_full tag - implemented as latches
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reg almost_empty ;
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reg almost_empty ;
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reg almost_full ;
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reg almost_full ;
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|
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// write allow wire - writes are allowed when fifo is not full
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// write allow wire - writes are allowed when fifo is not full
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wire wallow = wenable_in && ~full ;
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wire wallow = wenable_in && ~full ;
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|
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// write allow output assignment
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// write allow output assignment
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assign wallow_out = wallow ;
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assign wallow_out = wallow ;
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// read allow wire
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// read allow wire
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wire rallow ;
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wire rallow ;
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|
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// full output assignment
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// full output assignment
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assign full_out = full ;
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assign full_out = full ;
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|
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// almost full output assignment
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// almost full output assignment
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assign almost_full_out = almost_full && ~full ;
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assign almost_full_out = almost_full && ~full ;
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// clear generation for FFs and registers
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// clear generation for FFs and registers
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wire clear = reset_in || flush_in ;
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wire clear = reset_in || flush_in ;
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`ifdef SYNCHRONOUS
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`ifdef SYNCHRONOUS
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reg wclock_nempty_detect ;
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reg wclock_nempty_detect ;
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always@(posedge reset_in or posedge wclock_in)
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always@(posedge reset_in or posedge wclock_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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wclock_nempty_detect <= #`FF_DELAY 1'b0 ;
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wclock_nempty_detect <= #`FF_DELAY 1'b0 ;
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else
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else
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wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
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wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
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end
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end
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|
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// special synchronizing mechanism for different implementations - in synchronous imp., empty is prolonged for 1 clock edge if no write clock comes after initial write
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// special synchronizing mechanism for different implementations - in synchronous imp., empty is prolonged for 1 clock edge if no write clock comes after initial write
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reg stretched_empty ;
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reg stretched_empty ;
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if(clear)
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if(clear)
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stretched_empty <= #`FF_DELAY 1'b1 ;
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stretched_empty <= #`FF_DELAY 1'b1 ;
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else
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else
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stretched_empty <= #`FF_DELAY empty && ~wclock_nempty_detect ;
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stretched_empty <= #`FF_DELAY empty && ~wclock_nempty_detect ;
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end
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end
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// empty output is actual empty + 1 read clock cycle ( stretched empty )
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// empty output is actual empty + 1 read clock cycle ( stretched empty )
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assign empty_out = empty || stretched_empty ;
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assign empty_out = empty || stretched_empty ;
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//rallow generation
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//rallow generation
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assign rallow = renable_in && ~empty && ~stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
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assign rallow = renable_in && ~empty && ~stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
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// rallow output assignment
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// rallow output assignment
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assign rallow_out = rallow ;
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assign rallow_out = rallow ;
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// almost empty output assignment
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// almost empty output assignment
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assign almost_empty_out = almost_empty && ~empty && ~stretched_empty ;
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assign almost_empty_out = almost_empty && ~empty && ~stretched_empty ;
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|
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// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
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// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
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// when FIFO is empty, this register provides actual read address, so first location can be read
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// when FIFO is empty, this register provides actual read address, so first location can be read
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reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
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reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
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|
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// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
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// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
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// done for zero wait state burst
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// done for zero wait state burst
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assign raddr_out = empty_out ? raddr : raddr_plus_one ;
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assign raddr_out = empty_out ? raddr : raddr_plus_one ;
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// enable for this register
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// enable for this register
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wire raddr_plus_one_en = rallow ;
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wire raddr_plus_one_en = rallow ;
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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raddr_plus_one[(ADDR_LENGTH - 1):1] <= #`FF_DELAY { (ADDR_LENGTH - 1){1'b0}} ;
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raddr_plus_one[(ADDR_LENGTH - 1):1] <= #`FF_DELAY { (ADDR_LENGTH - 1){1'b0}} ;
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raddr_plus_one[0] <= #`FF_DELAY 1'b1 ;
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raddr_plus_one[0] <= #`FF_DELAY 1'b1 ;
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end
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end
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else if (raddr_plus_one_en)
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else if (raddr_plus_one_en)
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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end
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end
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|
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// raddr is filled with raddr_plus_one on rising read clock edge when rallow is high
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// raddr is filled with raddr_plus_one on rising read clock edge when rallow is high
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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// initial value is 000......00
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// initial value is 000......00
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raddr <= #`FF_DELAY { ADDR_LENGTH{1'b0}} ;
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raddr <= #`FF_DELAY { ADDR_LENGTH{1'b0}} ;
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else if (rallow)
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else if (rallow)
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raddr <= #`FF_DELAY raddr_plus_one ;
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raddr <= #`FF_DELAY raddr_plus_one ;
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end
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end
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`else
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`else
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// asynchronous RAM storage for FIFOs - somewhat simpler control logic
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// asynchronous RAM storage for FIFOs - somewhat simpler control logic
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//rallow generation
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//rallow generation
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assign rallow = renable_in && ~empty ;
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assign rallow = renable_in && ~empty ;
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|
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assign rallow_out = rallow;
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assign rallow_out = rallow;
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|
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assign almost_empty_out = almost_empty && ~empty ;
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assign almost_empty_out = almost_empty && ~empty ;
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|
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// read address counter - normal counter, nothing to it
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// read address counter - normal counter, nothing to it
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// for asynchronous implementation, there is no need for pointing to next address.
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// for asynchronous implementation, there is no need for pointing to next address.
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// On clock edge that read is performed, read address will change and on the next clock edge
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// On clock edge that read is performed, read address will change and on the next clock edge
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// asynchronous memory will provide next data
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// asynchronous memory will provide next data
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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// initial value is 000......00
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// initial value is 000......00
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raddr <= #`FF_DELAY { ADDR_LENGTH{1'b0}} ;
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raddr <= #`FF_DELAY { ADDR_LENGTH{1'b0}} ;
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else if (rallow)
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else if (rallow)
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raddr <= #`FF_DELAY raddr + 1'b1 ;
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raddr <= #`FF_DELAY raddr + 1'b1 ;
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end
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end
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|
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assign empty_out = empty ;
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assign empty_out = empty ;
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assign raddr_out = raddr ;
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assign raddr_out = raddr ;
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`endif
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`endif
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|
|
/*-----------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------
|
Read address control consists of Read address counter and Grey Address pipeline
|
Read address control consists of Read address counter and Grey Address pipeline
|
There are 4 Grey addresses:
|
There are 4 Grey addresses:
|
- rgrey_minus2 is Grey Code of address two before current address
|
- rgrey_minus2 is Grey Code of address two before current address
|
- rgrey_minus1 is Grey Code of address one before current address
|
- rgrey_minus1 is Grey Code of address one before current address
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- rgrey_addr is Grey Code of current read address
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- rgrey_addr is Grey Code of current read address
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- rgrey_next is Grey Code of next read address
|
- rgrey_next is Grey Code of next read address
|
--------------------------------------------------------------------------------------------------*/
|
--------------------------------------------------------------------------------------------------*/
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// grey code register for two before read address
|
// grey code register for two before read address
|
always@(posedge rclock_in or posedge clear)
|
always@(posedge rclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
begin
|
begin
|
// initial value is 100......010
|
// initial value is 100......010
|
rgrey_minus2[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
|
rgrey_minus2[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
|
rgrey_minus2[(ADDR_LENGTH - 2):2] <= #`FF_DELAY { (ADDR_LENGTH - 3){1'b0} } ;
|
rgrey_minus2[(ADDR_LENGTH - 2):2] <= #`FF_DELAY { (ADDR_LENGTH - 3){1'b0} } ;
|
rgrey_minus2[1:0] <= #`FF_DELAY 2'b10 ;
|
rgrey_minus2[1:0] <= #`FF_DELAY 2'b10 ;
|
end
|
end
|
else
|
else
|
if (rallow)
|
if (rallow)
|
rgrey_minus2 <= #`FF_DELAY rgrey_minus1 ;
|
rgrey_minus2 <= #`FF_DELAY rgrey_minus1 ;
|
end
|
end
|
|
|
// grey code register for one before read address
|
// grey code register for one before read address
|
always@(posedge rclock_in or posedge clear)
|
always@(posedge rclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
begin
|
begin
|
// initial value is 100......011
|
// initial value is 100......011
|
rgrey_minus1[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
|
rgrey_minus1[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
|
rgrey_minus1[(ADDR_LENGTH - 2):2] <= #`FF_DELAY { (ADDR_LENGTH - 3){1'b0} } ;
|
rgrey_minus1[(ADDR_LENGTH - 2):2] <= #`FF_DELAY { (ADDR_LENGTH - 3){1'b0} } ;
|
rgrey_minus1[1:0] <= #`FF_DELAY 2'b11 ;
|
rgrey_minus1[1:0] <= #`FF_DELAY 2'b11 ;
|
end
|
end
|
else
|
else
|
if (rallow)
|
if (rallow)
|
rgrey_minus1 <= #`FF_DELAY rgrey_addr ;
|
rgrey_minus1 <= #`FF_DELAY rgrey_addr ;
|
end
|
end
|
|
|
// grey code register for read address - represents current Read Address
|
// grey code register for read address - represents current Read Address
|
always@(posedge rclock_in or posedge clear)
|
always@(posedge rclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
begin
|
begin
|
// initial value is 100.......01
|
// initial value is 100.......01
|
rgrey_addr[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
|
rgrey_addr[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
|
rgrey_addr[(ADDR_LENGTH - 2):1] <= #`FF_DELAY { (ADDR_LENGTH - 2){1'b0} } ;
|
rgrey_addr[(ADDR_LENGTH - 2):1] <= #`FF_DELAY { (ADDR_LENGTH - 2){1'b0} } ;
|
rgrey_addr[0] <= #`FF_DELAY 1'b1 ;
|
rgrey_addr[0] <= #`FF_DELAY 1'b1 ;
|
end
|
end
|
else
|
else
|
if (rallow)
|
if (rallow)
|
rgrey_addr <= #`FF_DELAY rgrey_next ;
|
rgrey_addr <= #`FF_DELAY rgrey_next ;
|
end
|
end
|
|
|
// grey code register for next read address - represents Grey Code of next read address
|
// grey code register for next read address - represents Grey Code of next read address
|
always@(posedge rclock_in or posedge clear)
|
always@(posedge rclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
begin
|
begin
|
// initial value is 100......00
|
// initial value is 100......00
|
rgrey_next[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
|
rgrey_next[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
|
rgrey_next[(ADDR_LENGTH - 2):0] <= #`FF_DELAY { (ADDR_LENGTH - 1){1'b0} } ;
|
rgrey_next[(ADDR_LENGTH - 2):0] <= #`FF_DELAY { (ADDR_LENGTH - 1){1'b0} } ;
|
end
|
end
|
else
|
else
|
if (rallow)
|
if (rallow)
|
rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
|
rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
|
end
|
end
|
|
|
/*--------------------------------------------------------------------------------------------
|
/*--------------------------------------------------------------------------------------------
|
Write address control consists of write address counter and three Grey Code Registers:
|
Write address control consists of write address counter and three Grey Code Registers:
|
- wgrey_minus1 represents Grey Coded address of location one before current write address
|
- wgrey_minus1 represents Grey Coded address of location one before current write address
|
- wgrey_addr represents current Grey Coded write address
|
- wgrey_addr represents current Grey Coded write address
|
- wgrey_next represents Grey Coded next write address
|
- wgrey_next represents Grey Coded next write address
|
----------------------------------------------------------------------------------------------*/
|
----------------------------------------------------------------------------------------------*/
|
// grey code register for one before write address
|
// grey code register for one before write address
|
always@(posedge wclock_in or posedge clear)
|
always@(posedge wclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
begin
|
begin
|
// initial value is 100.....001
|
// initial value is 100.....001
|
wgrey_minus1[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
|
wgrey_minus1[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
|
wgrey_minus1[(ADDR_LENGTH - 2):2] <= #`FF_DELAY { (ADDR_LENGTH - 3){1'b0} } ;
|
wgrey_minus1[(ADDR_LENGTH - 2):2] <= #`FF_DELAY { (ADDR_LENGTH - 3){1'b0} } ;
|
wgrey_minus1[1:0] <= #`FF_DELAY 2'b11 ;
|
wgrey_minus1[1:0] <= #`FF_DELAY 2'b11 ;
|
end
|
end
|
else
|
else
|
if (wallow)
|
if (wallow)
|
wgrey_minus1 <= #`FF_DELAY wgrey_addr ;
|
wgrey_minus1 <= #`FF_DELAY wgrey_addr ;
|
end
|
end
|
|
|
// grey code register for write address
|
// grey code register for write address
|
always@(posedge wclock_in or posedge clear)
|
always@(posedge wclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
begin
|
begin
|
// initial value is 100.....001
|
// initial value is 100.....001
|
wgrey_addr[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
|
wgrey_addr[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
|
wgrey_addr[(ADDR_LENGTH - 2):1] <= #`FF_DELAY { (ADDR_LENGTH - 2){1'b0} } ;
|
wgrey_addr[(ADDR_LENGTH - 2):1] <= #`FF_DELAY { (ADDR_LENGTH - 2){1'b0} } ;
|
wgrey_addr[0] <= #`FF_DELAY 1'b1 ;
|
wgrey_addr[0] <= #`FF_DELAY 1'b1 ;
|
end
|
end
|
else
|
else
|
if (wallow)
|
if (wallow)
|
wgrey_addr <= #`FF_DELAY wgrey_next ;
|
wgrey_addr <= #`FF_DELAY wgrey_next ;
|
end
|
end
|
|
|
// grey code register for next write address
|
// grey code register for next write address
|
always@(posedge wclock_in or posedge clear)
|
always@(posedge wclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
begin
|
begin
|
// initial value is 100......00
|
// initial value is 100......00
|
wgrey_next[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
|
wgrey_next[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
|
wgrey_next[(ADDR_LENGTH - 2):0] <= #`FF_DELAY { (ADDR_LENGTH - 1){1'b0} } ;
|
wgrey_next[(ADDR_LENGTH - 2):0] <= #`FF_DELAY { (ADDR_LENGTH - 1){1'b0} } ;
|
end
|
end
|
else
|
else
|
if (wallow)
|
if (wallow)
|
wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
|
wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
|
end
|
end
|
|
|
// write address counter - nothing special
|
// write address counter - nothing special
|
always@(posedge wclock_in or posedge clear)
|
always@(posedge wclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
// initial value 00.........00
|
// initial value 00.........00
|
waddr <= #`FF_DELAY { (ADDR_LENGTH){1'b0} } ;
|
waddr <= #`FF_DELAY { (ADDR_LENGTH){1'b0} } ;
|
else
|
else
|
if (wallow)
|
if (wallow)
|
waddr <= #`FF_DELAY waddr + 1'b1 ;
|
waddr <= #`FF_DELAY waddr + 1'b1 ;
|
end
|
end
|
|
|
/*------------------------------------------------------------------------------------------------------------------------------
|
/*------------------------------------------------------------------------------------------------------------------------------
|
Registered full control:
|
Registered full control:
|
registered full is set on rising edge of wclock_in, when fifo is almost full and something gets written to it.
|
registered full is set on rising edge of wclock_in, when fifo is almost full and something gets written to it.
|
It's kept high until something is read from FIFO, which is registered on next rising write clock edge.
|
It's kept high until something is read from FIFO, which is registered on next rising write clock edge.
|
|
|
Registered almost full control:
|
Registered almost full control:
|
Almost full flag is set on rising write clock edge whenever two free locations are left in fifo and another entry is written to it.
|
Almost full flag is set on rising write clock edge whenever two free locations are left in fifo and another entry is written to it.
|
It remains set if nothing is read/written from/to fifo. All operations are synchronized on write clock.
|
It remains set if nothing is read/written from/to fifo. All operations are synchronized on write clock.
|
--------------------------------------------------------------------------------------------------------------------------------*/
|
--------------------------------------------------------------------------------------------------------------------------------*/
|
wire comb_full = wgrey_next == rgrey_addr ;
|
wire comb_full = wgrey_next == rgrey_addr ;
|
wire comb_almost_full = wgrey_addr == rgrey_minus2 ;
|
wire comb_almost_full = wgrey_addr == rgrey_minus2 ;
|
wire comb_two_left = wgrey_next == rgrey_minus2 ;
|
wire comb_two_left = wgrey_next == rgrey_minus2 ;
|
|
|
//combinatorial input to Registered full FlipFlop
|
//combinatorial input to Registered full FlipFlop
|
wire reg_full = (wallow && comb_almost_full) || (comb_full) ;
|
wire reg_full = (wallow && comb_almost_full) || (comb_full) ;
|
|
|
always@(posedge wclock_in or posedge clear)
|
always@(posedge wclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
full <= #`FF_DELAY 1'b0 ;
|
full <= #`FF_DELAY 1'b0 ;
|
else
|
else
|
full <= #`FF_DELAY reg_full ;
|
full <= #`FF_DELAY reg_full ;
|
end
|
end
|
|
|
// input for almost full flip flop
|
// input for almost full flip flop
|
wire reg_almost_full_in = wallow && comb_two_left || comb_almost_full ;
|
wire reg_almost_full_in = wallow && comb_two_left || comb_almost_full ;
|
|
|
always@(posedge clear or posedge wclock_in)
|
always@(posedge clear or posedge wclock_in)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
almost_full <= #`FF_DELAY 1'b0 ;
|
almost_full <= #`FF_DELAY 1'b0 ;
|
else
|
else
|
almost_full <= #`FF_DELAY reg_almost_full_in ;
|
almost_full <= #`FF_DELAY reg_almost_full_in ;
|
end
|
end
|
|
|
/*------------------------------------------------------------------------------------------------------------------------------
|
/*------------------------------------------------------------------------------------------------------------------------------
|
Registered empty control:
|
Registered empty control:
|
registered empty is set on rising edge of rclock_in when one location is occupied and read from it. It remains set until
|
registered empty is set on rising edge of rclock_in when one location is occupied and read from it. It remains set until
|
something is written to fifo which is detected on next read clock edge.
|
something is written to fifo which is detected on next read clock edge.
|
|
|
Registered almost empty control:
|
Registered almost empty control:
|
Almost empty is set on rising clock edge of read clock when two locations are used in fifo and one of them is read from it.
|
Almost empty is set on rising clock edge of read clock when two locations are used in fifo and one of them is read from it.
|
It remains set until something is read/written from/to fifo. All operations are detected on rising edge of read clock.
|
It remains set until something is read/written from/to fifo. All operations are detected on rising edge of read clock.
|
--------------------------------------------------------------------------------------------------------------------------------*/
|
--------------------------------------------------------------------------------------------------------------------------------*/
|
wire comb_almost_empty = rgrey_next == wgrey_addr ;
|
wire comb_almost_empty = rgrey_next == wgrey_addr ;
|
wire comb_empty = rgrey_addr == wgrey_addr ;
|
wire comb_empty = rgrey_addr == wgrey_addr ;
|
wire comb_two_used = rgrey_next == wgrey_minus1 ;
|
wire comb_two_used = rgrey_next == wgrey_minus1 ;
|
|
|
// combinatorial input for registered emty FlipFlop
|
// combinatorial input for registered emty FlipFlop
|
wire reg_empty = (rallow && comb_almost_empty) || comb_empty ;
|
wire reg_empty = (rallow && comb_almost_empty) || comb_empty ;
|
|
|
always@(posedge rclock_in or posedge clear)
|
always@(posedge rclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
empty <= #`FF_DELAY 1'b1 ;
|
empty <= #`FF_DELAY 1'b1 ;
|
else
|
else
|
empty <= #`FF_DELAY reg_empty ;
|
empty <= #`FF_DELAY reg_empty ;
|
end
|
end
|
|
|
// input for almost empty flip flop
|
// input for almost empty flip flop
|
wire reg_almost_empty = rallow && comb_two_used || comb_almost_empty ;
|
wire reg_almost_empty = rallow && comb_two_used || comb_almost_empty ;
|
always@(posedge clear or posedge rclock_in)
|
always@(posedge clear or posedge rclock_in)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
almost_empty <= #`FF_DELAY 1'b0 ;
|
almost_empty <= #`FF_DELAY 1'b0 ;
|
else
|
else
|
almost_empty <= #`FF_DELAY reg_almost_empty ;
|
almost_empty <= #`FF_DELAY reg_almost_empty ;
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
