//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// File name: pci_rst_int.v ////
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//// File name: pci_rst_int.v ////
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//// ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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//
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//
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//
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//
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`include "pci_constants.v"
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`include "pci_constants.v"
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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// Module is used to switch appropriate reset and interrupt signals with few logic
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// Module is used to switch appropriate reset and interrupt signals with few logic
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module PCI_RST_INT
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module PCI_RST_INT
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(
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(
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clk_in,
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clk_in,
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// reset signals
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// reset signals
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rst_i,
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rst_i,
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pci_rstn_in,
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pci_rstn_in,
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conf_soft_res_in,
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conf_soft_res_in,
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reset,
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reset,
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pci_rstn_out,
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pci_rstn_out,
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pci_rstn_en_out,
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pci_rstn_en_out,
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rst_o,
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rst_o,
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// interrupt signals
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// interrupt signals
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pci_intan_in,
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pci_intan_in,
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conf_int_in,
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conf_int_in,
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int_i,
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int_i,
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out_bckp_perr_en_in,
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out_bckp_perr_en_in,
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out_bckp_serr_en_in,
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out_bckp_serr_en_in,
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pci_intan_out,
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pci_intan_out,
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pci_intan_en_out,
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pci_intan_en_out,
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int_o,
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int_o,
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conf_isr_int_prop_out
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conf_isr_int_prop_out
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);
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);
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input clk_in;
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input clk_in;
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// RESET inputs and outputs
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// RESET inputs and outputs
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input rst_i;
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input rst_i;
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input pci_rstn_in;
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input pci_rstn_in;
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input conf_soft_res_in;
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input conf_soft_res_in;
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output reset;
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output reset;
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output pci_rstn_out;
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output pci_rstn_out;
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output pci_rstn_en_out;
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output pci_rstn_en_out;
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output rst_o;
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output rst_o;
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// INTERRUPT inputs and outputs
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// INTERRUPT inputs and outputs
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input pci_intan_in;
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input pci_intan_in;
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input conf_int_in;
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input conf_int_in;
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input int_i;
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input int_i;
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input out_bckp_perr_en_in;
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input out_bckp_perr_en_in;
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input out_bckp_serr_en_in;
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input out_bckp_serr_en_in;
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output pci_intan_out;
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output pci_intan_out;
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output pci_intan_en_out;
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output pci_intan_en_out;
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output int_o;
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output int_o;
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output conf_isr_int_prop_out;
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output conf_isr_int_prop_out;
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/*--------------------------------------------------------------------------------------------------------
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/*--------------------------------------------------------------------------------------------------------
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RESET logic
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RESET logic
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--------------------------------------------------------------------------------------------------------*/
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--------------------------------------------------------------------------------------------------------*/
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assign pci_rstn_out = 1'b0 ;
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assign pci_rstn_out = 1'b0 ;
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// host implementation of the bridge gets its reset from WISHBONE bus - RST_I and propagates it to PCI bus
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// host implementation of the bridge gets its reset from WISHBONE bus - RST_I and propagates it to PCI bus
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`ifdef HOST
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`ifdef HOST
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assign reset = rst_i ;
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assign reset = rst_i ;
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`ifdef ACTIVE_LOW_OE
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`ifdef ACTIVE_LOW_OE
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assign pci_rstn_en_out = ~(rst_i || conf_soft_res_in) ;
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assign pci_rstn_en_out = ~(rst_i || conf_soft_res_in) ;
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`else
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`else
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assign pci_rstn_en_out = rst_i || conf_soft_res_in ;
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assign pci_rstn_en_out = rst_i || conf_soft_res_in ;
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`endif
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`endif
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assign rst_o = 1'b0 ;
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assign rst_o = 1'b0 ;
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`else
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`else
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// guest implementation of the bridge gets its reset from PCI bus - RST# and propagates it to WISHBONE bus
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// guest implementation of the bridge gets its reset from PCI bus - RST# and propagates it to WISHBONE bus
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`ifdef GUEST
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`ifdef GUEST
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assign reset = ~pci_rstn_in ;
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assign reset = ~pci_rstn_in ;
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assign rst_o = (~pci_rstn_in) || conf_soft_res_in ;
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assign rst_o = (~pci_rstn_in) || conf_soft_res_in ;
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`ifdef ACTIVE_LOW_OE
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`ifdef ACTIVE_LOW_OE
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assign pci_rstn_en_out = 1'b1 ; // disabled
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assign pci_rstn_en_out = 1'b1 ; // disabled
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`else
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`else
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assign pci_rstn_en_out = 1'b0 ; // disabled
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assign pci_rstn_en_out = 1'b0 ; // disabled
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`endif
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`endif
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`endif
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`endif
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`endif
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`endif
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/*--------------------------------------------------------------------------------------------------------
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/*--------------------------------------------------------------------------------------------------------
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INTERRUPT logic
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INTERRUPT logic
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--------------------------------------------------------------------------------------------------------*/
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--------------------------------------------------------------------------------------------------------*/
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assign pci_intan_out = 1'b0 ;
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assign pci_intan_out = 1'b0 ;
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// host implementation of the bridge gets its interrupt from PCI bus - INTA# and propagates it to WISHBONE bus
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// host implementation of the bridge gets its interrupt from PCI bus - INTA# and propagates it to WISHBONE bus
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`ifdef HOST
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`ifdef HOST
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assign conf_isr_int_prop_out = ~pci_intan_in ;
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assign conf_isr_int_prop_out = ~pci_intan_in ;
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assign int_o = conf_int_in ;
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assign int_o = conf_int_in ;
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`ifdef ACTIVE_LOW_OE
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`ifdef ACTIVE_LOW_OE
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assign pci_intan_en_out = 1'b1 ; // disabled
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assign pci_intan_en_out = 1'b1 ; // disabled
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`else
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`else
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assign pci_intan_en_out = 1'b0 ; // disabled
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assign pci_intan_en_out = 1'b0 ; // disabled
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`endif
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`endif
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`else
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`else
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// guest implementation of the bridge gets its interrupt from WISHBONE bus - INT_I and propagates it to PCI bus
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// guest implementation of the bridge gets its interrupt from WISHBONE bus - INT_I and propagates it to PCI bus
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`ifdef GUEST
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`ifdef GUEST
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wire interrupt_a_en;
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wire interrupt_a_en;
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OUT_REG inta
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OUT_REG inta
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(
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(
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.reset_in ( reset ),
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.reset_in ( reset ),
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.clk_in ( clk_in) ,
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.clk_in ( clk_in) ,
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.dat_en_in ( 1'b1 ),
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.dat_en_in ( 1'b1 ),
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.en_en_in ( 1'b1 ),
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.en_en_in ( 1'b1 ),
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.dat_in ( 1'b0 ) , // active low
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.dat_in ( 1'b0 ) , // active low
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.en_in ( conf_int_in ) ,
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.en_in ( conf_int_in ) ,
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.en_out ( interrupt_a_en ),
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.en_out ( interrupt_a_en ),
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.dat_out ( )
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.dat_out ( )
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);
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);
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assign conf_isr_int_prop_out = int_i ;
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assign conf_isr_int_prop_out = int_i ;
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assign int_o = 1'b0 ;
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assign int_o = 1'b0 ;
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assign pci_intan_en_out = interrupt_a_en ;
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assign pci_intan_en_out = interrupt_a_en ;
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`endif
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`endif
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`endif
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`endif
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endmodule
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endmodule
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