//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// File name: pci_target32_devs_crit.v ////
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//// File name: pci_target32_devs_crit.v ////
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//// ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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// module is used to separate logic which uses criticaly constrained inputs from slower logic.
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// module is used to separate logic which uses criticaly constrained inputs from slower logic.
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// It is used to synthesize critical timing logic separately with faster cells or without optimization
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// It is used to synthesize critical timing logic separately with faster cells or without optimization
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module PCI_TARGET32_DEVS_CRIT
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module PCI_TARGET32_DEVS_CRIT
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(
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(
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devs_w,
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devs_w,
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devs_w_frm,
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devs_w_frm,
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devs_w_frm_irdy,
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devs_w_frm_irdy,
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pci_frame_in,
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pci_frame_in,
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pci_irdy_in,
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pci_irdy_in,
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pci_devsel_out
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pci_devsel_out
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);
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);
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input devs_w ; // devsel signal (composed without critical signals) that do not need critical inputs
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input devs_w ; // devsel signal (composed without critical signals) that do not need critical inputs
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input devs_w_frm ; // devsel signal (composed without critical signals) that needs AND with critical FRAME input
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input devs_w_frm ; // devsel signal (composed without critical signals) that needs AND with critical FRAME input
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input devs_w_frm_irdy ; // devsel signal (composed without critical signals) that needs AND with critical FRAME and
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input devs_w_frm_irdy ; // devsel signal (composed without critical signals) that needs AND with critical FRAME and
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// IRDY inputs
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// IRDY inputs
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input pci_frame_in ; // critical constrained input signal
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input pci_frame_in ; // critical constrained input signal
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input pci_irdy_in ; // critical constrained input signal
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input pci_irdy_in ; // critical constrained input signal
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output pci_devsel_out ; // PCI devsel output
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output pci_devsel_out ; // PCI devsel output
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// PCI devsel output with preserved hierarchy for minimum delay!
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// PCI devsel output with preserved hierarchy for minimum delay!
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assign pci_devsel_out = ~(devs_w || (devs_w_frm && ~pci_frame_in) || (devs_w_frm_irdy && ~pci_frame_in && pci_irdy_in)) ;
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assign pci_devsel_out = ~(devs_w || (devs_w_frm && ~pci_frame_in) || (devs_w_frm_irdy && ~pci_frame_in && pci_irdy_in)) ;
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