//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// File name: pci_target32_interface.v ////
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//// File name: pci_target32_interface.v ////
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//// ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/08/22 13:28:04 mihad
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// Revision 1.5 2002/08/22 13:28:04 mihad
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// Updated for synthesis purposes. Gate level simulation was failing in some configurations
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// Updated for synthesis purposes. Gate level simulation was failing in some configurations
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//
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//
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// Revision 1.4 2002/02/19 16:32:37 mihad
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// Revision 1.4 2002/02/19 16:32:37 mihad
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// Modified testbench and fixed some bugs
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// Modified testbench and fixed some bugs
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//
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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`include "bus_commands.v"
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`include "bus_commands.v"
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`include "pci_constants.v"
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`include "pci_constants.v"
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module PCI_TARGET32_INTERFACE
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module PCI_TARGET32_INTERFACE
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(
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(
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// system inputs
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// system inputs
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clk_in,
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clk_in,
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reset_in,
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reset_in,
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// PCI Target side of INTERFACE
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// PCI Target side of INTERFACE
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address_in,
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address_in,
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addr_claim_out,
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addr_claim_out,
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bc_in,
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bc_in,
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bc0_in,
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bc0_in,
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data_in,
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data_in,
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data_out,
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data_out,
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be_in,
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be_in,
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req_in,
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req_in,
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rdy_in,
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rdy_in,
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addr_phase_in,
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addr_phase_in,
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bckp_devsel_in,
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bckp_devsel_in,
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bckp_trdy_in,
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bckp_trdy_in,
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bckp_stop_in,
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bckp_stop_in,
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last_reg_in,
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last_reg_in,
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frame_reg_in,
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frame_reg_in,
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fetch_pcir_fifo_in,
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fetch_pcir_fifo_in,
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load_medium_reg_in,
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load_medium_reg_in,
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sel_fifo_mreg_in,
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sel_fifo_mreg_in,
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sel_conf_fifo_in,
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sel_conf_fifo_in,
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fetch_conf_in,
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fetch_conf_in,
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load_to_pciw_fifo_in,
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load_to_pciw_fifo_in,
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load_to_conf_in,
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load_to_conf_in,
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same_read_out,
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same_read_out,
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norm_access_to_config_out,
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norm_access_to_config_out,
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read_completed_out,
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read_completed_out,
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read_processing_out,
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read_processing_out,
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target_abort_out,
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target_abort_out,
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disconect_wo_data_out,
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disconect_wo_data_out,
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disconect_w_data_out,
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disconect_w_data_out,
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pciw_fifo_full_out,
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pciw_fifo_full_out,
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pcir_fifo_data_err_out,
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pcir_fifo_data_err_out,
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wbw_fifo_empty_out,
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wbw_fifo_empty_out,
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wbu_del_read_comp_pending_out,
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wbu_del_read_comp_pending_out,
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// Delayed synchronizacion module signals
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// Delayed synchronizacion module signals
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req_out,
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req_out,
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done_out,
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done_out,
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in_progress_out,
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in_progress_out,
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req_req_pending_in,
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req_req_pending_in,
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req_comp_pending_in,
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req_comp_pending_in,
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addr_out,
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addr_out,
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be_out,
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be_out,
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we_out,
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we_out,
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bc_out,
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bc_out,
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burst_ok_out,
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burst_ok_out,
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strd_addr_in,
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strd_addr_in,
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strd_bc_in,
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strd_bc_in,
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status_in,
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status_in,
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comp_flush_in,
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comp_flush_in,
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// FIFO signals
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// FIFO signals
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pcir_fifo_renable_out,
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pcir_fifo_renable_out,
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pcir_fifo_data_in,
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pcir_fifo_data_in,
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pcir_fifo_be_in,
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pcir_fifo_be_in,
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pcir_fifo_control_in,
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pcir_fifo_control_in,
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pcir_fifo_flush_out,
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pcir_fifo_flush_out,
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pcir_fifo_almost_empty_in,
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pcir_fifo_almost_empty_in,
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pcir_fifo_empty_in,
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pcir_fifo_empty_in,
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pciw_fifo_wenable_out,
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pciw_fifo_wenable_out,
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pciw_fifo_addr_data_out,
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pciw_fifo_addr_data_out,
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pciw_fifo_cbe_out,
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pciw_fifo_cbe_out,
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pciw_fifo_control_out,
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pciw_fifo_control_out,
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pciw_fifo_two_left_in,
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pciw_fifo_two_left_in,
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pciw_fifo_almost_full_in,
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pciw_fifo_almost_full_in,
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pciw_fifo_full_in,
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pciw_fifo_full_in,
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wbw_fifo_empty_in,
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wbw_fifo_empty_in,
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wbu_del_read_comp_pending_in,
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wbu_del_read_comp_pending_in,
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// Configuration space signals
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// Configuration space signals
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conf_hit_out,
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conf_hit_out,
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conf_addr_out,
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conf_addr_out,
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conf_data_out,
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conf_data_out,
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conf_data_in,
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conf_data_in,
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conf_be_out,
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conf_be_out,
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conf_we_out,
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conf_we_out,
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conf_re_out,
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conf_re_out,
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mem_enable_in,
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mem_enable_in,
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io_enable_in,
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io_enable_in,
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mem_io_addr_space0_in,
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mem_io_addr_space0_in,
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mem_io_addr_space1_in,
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mem_io_addr_space1_in,
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mem_io_addr_space2_in,
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mem_io_addr_space2_in,
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mem_io_addr_space3_in,
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mem_io_addr_space3_in,
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mem_io_addr_space4_in,
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mem_io_addr_space4_in,
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mem_io_addr_space5_in,
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mem_io_addr_space5_in,
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pre_fetch_en0_in,
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pre_fetch_en0_in,
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pre_fetch_en1_in,
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pre_fetch_en1_in,
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pre_fetch_en2_in,
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pre_fetch_en2_in,
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pre_fetch_en3_in,
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pre_fetch_en3_in,
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pre_fetch_en4_in,
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pre_fetch_en4_in,
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pre_fetch_en5_in,
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pre_fetch_en5_in,
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pci_base_addr0_in,
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pci_base_addr0_in,
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pci_base_addr1_in,
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pci_base_addr1_in,
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pci_base_addr2_in,
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pci_base_addr2_in,
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pci_base_addr3_in,
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pci_base_addr3_in,
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pci_base_addr4_in,
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pci_base_addr4_in,
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pci_base_addr5_in,
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pci_base_addr5_in,
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pci_addr_mask0_in,
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pci_addr_mask0_in,
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pci_addr_mask1_in,
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pci_addr_mask1_in,
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pci_addr_mask2_in,
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pci_addr_mask2_in,
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pci_addr_mask3_in,
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pci_addr_mask3_in,
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pci_addr_mask4_in,
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pci_addr_mask4_in,
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pci_addr_mask5_in,
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pci_addr_mask5_in,
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pci_tran_addr0_in,
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pci_tran_addr0_in,
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pci_tran_addr1_in,
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pci_tran_addr1_in,
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pci_tran_addr2_in,
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pci_tran_addr2_in,
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pci_tran_addr3_in,
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pci_tran_addr3_in,
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pci_tran_addr4_in,
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pci_tran_addr4_in,
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pci_tran_addr5_in,
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pci_tran_addr5_in,
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addr_tran_en0_in,
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addr_tran_en0_in,
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addr_tran_en1_in,
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addr_tran_en1_in,
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addr_tran_en2_in,
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addr_tran_en2_in,
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addr_tran_en3_in,
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addr_tran_en3_in,
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addr_tran_en4_in,
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addr_tran_en4_in,
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addr_tran_en5_in
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addr_tran_en5_in
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) ;
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) ;
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/*==================================================================================================================
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/*==================================================================================================================
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System inputs.
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System inputs.
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==================================================================================================================*/
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==================================================================================================================*/
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// PCI side clock and reset
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// PCI side clock and reset
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input clk_in,
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input clk_in,
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reset_in ;
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reset_in ;
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/*==================================================================================================================
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/*==================================================================================================================
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Side of the PCI Target state machine
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Side of the PCI Target state machine
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==================================================================================================================*/
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==================================================================================================================*/
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// Data, byte enables, bus commands and address ports
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// Data, byte enables, bus commands and address ports
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input [31:0] address_in ; // current request address input - registered
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input [31:0] address_in ; // current request address input - registered
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output addr_claim_out ; // current request address claim output
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output addr_claim_out ; // current request address claim output
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input [3:0] bc_in ; // current request bus command input - registered
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input [3:0] bc_in ; // current request bus command input - registered
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input bc0_in ; // current cycle RW signal
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input bc0_in ; // current cycle RW signal
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output [31:0] data_out ; // for read operations - current dataphase data output
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output [31:0] data_out ; // for read operations - current dataphase data output
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input [31:0] data_in ; // for write operations - current request data input - registered
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input [31:0] data_in ; // for write operations - current request data input - registered
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input [3:0] be_in ; // current dataphase byte enable inputs - registered
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input [3:0] be_in ; // current dataphase byte enable inputs - registered
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// Port connection control signals from PCI FSM
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// Port connection control signals from PCI FSM
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input req_in ; // Read is requested to WB master from PCI side
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input req_in ; // Read is requested to WB master from PCI side
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input rdy_in ; // DATA / ADDRESS selection from PCI side when read or write - registered
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input rdy_in ; // DATA / ADDRESS selection from PCI side when read or write - registered
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input addr_phase_in ; // Indicates address phase and also fast-back-to-back address phase - registered
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input addr_phase_in ; // Indicates address phase and also fast-back-to-back address phase - registered
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input bckp_devsel_in ; // DEVSEL input (which is registered) equivalent
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input bckp_devsel_in ; // DEVSEL input (which is registered) equivalent
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input bckp_trdy_in ; // TRDY input (which is registered) equivalent
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input bckp_trdy_in ; // TRDY input (which is registered) equivalent
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input bckp_stop_in ; // STOP input (which is registered) equivalent
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input bckp_stop_in ; // STOP input (which is registered) equivalent
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input last_reg_in ; // Indicates last data phase - registered
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input last_reg_in ; // Indicates last data phase - registered
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input frame_reg_in ; // FRAME input signal - registered
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input frame_reg_in ; // FRAME input signal - registered
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input fetch_pcir_fifo_in ;// Read enable for PCIR_FIFO when when read is finishen on WB side
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input fetch_pcir_fifo_in ;// Read enable for PCIR_FIFO when when read is finishen on WB side
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input load_medium_reg_in ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
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input load_medium_reg_in ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
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input sel_fifo_mreg_in ; // Read data selection between PCIR_FIFO and medium register
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input sel_fifo_mreg_in ; // Read data selection between PCIR_FIFO and medium register
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input sel_conf_fifo_in ; // Read data selection between Configuration registers and "FIFO"
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input sel_conf_fifo_in ; // Read data selection between Configuration registers and "FIFO"
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input fetch_conf_in ; // Read enable for configuration space registers
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input fetch_conf_in ; // Read enable for configuration space registers
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input load_to_pciw_fifo_in ;// Write enable to PCIW_FIFO
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input load_to_pciw_fifo_in ;// Write enable to PCIW_FIFO
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input load_to_conf_in ; // Write enable to Configuration space registers
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input load_to_conf_in ; // Write enable to Configuration space registers
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/*==================================================================================================================
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/*==================================================================================================================
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Status outputs to PCI side (FSM)
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Status outputs to PCI side (FSM)
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==================================================================================================================*/
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==================================================================================================================*/
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output same_read_out ; // Indicates the same read request (important when read is finished on WB side)
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output same_read_out ; // Indicates the same read request (important when read is finished on WB side)
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output norm_access_to_config_out ; // Indicates the access to Configuration space with MEMORY commands
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output norm_access_to_config_out ; // Indicates the access to Configuration space with MEMORY commands
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output read_completed_out ; // Indicates that read request is completed on WB side
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output read_completed_out ; // Indicates that read request is completed on WB side
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output read_processing_out ; // Indicates that read request is processing on WB side
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output read_processing_out ; // Indicates that read request is processing on WB side
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output target_abort_out ; // Indicates target abort termination
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output target_abort_out ; // Indicates target abort termination
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output disconect_wo_data_out ; // Indicates disconnect without data termination
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output disconect_wo_data_out ; // Indicates disconnect without data termination
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output disconect_w_data_out ; // Indicates disconnect with data termination
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output disconect_w_data_out ; // Indicates disconnect with data termination
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output pciw_fifo_full_out ; // Indicates that write PCIW_FIFO is full
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output pciw_fifo_full_out ; // Indicates that write PCIW_FIFO is full
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output pcir_fifo_data_err_out ; // Indicates data error on current data read from PCIR_FIFO
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output pcir_fifo_data_err_out ; // Indicates data error on current data read from PCIR_FIFO
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output wbw_fifo_empty_out ; // Indicates that WB SLAVE has no data to be written to PCI bus
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output wbw_fifo_empty_out ; // Indicates that WB SLAVE has no data to be written to PCI bus
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output wbu_del_read_comp_pending_out ; // Indicates that WB Unit has a delayed read poending!
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output wbu_del_read_comp_pending_out ; // Indicates that WB Unit has a delayed read poending!
|
|
|
/*==================================================================================================================
|
/*==================================================================================================================
|
Read request interface through Delayed sinchronization module to WB Master
|
Read request interface through Delayed sinchronization module to WB Master
|
==================================================================================================================*/
|
==================================================================================================================*/
|
// request, completion, done and progress indicator outputs for delayed_sync module where they are synchronized
|
// request, completion, done and progress indicator outputs for delayed_sync module where they are synchronized
|
output req_out, // request qualifier - when 1 it indicates that valid data is provided on outputs
|
output req_out, // request qualifier - when 1 it indicates that valid data is provided on outputs
|
done_out, // done output - when 1 indicates that PCI Target has completed a cycle on its bus
|
done_out, // done output - when 1 indicates that PCI Target has completed a cycle on its bus
|
in_progress_out ; // out progress indicator - indicates that current completion is in progress on
|
in_progress_out ; // out progress indicator - indicates that current completion is in progress on
|
// PCI Target side
|
// PCI Target side
|
// pending indication inputs - PCI Target side must know about requests and completions
|
// pending indication inputs - PCI Target side must know about requests and completions
|
input req_req_pending_in ; // request pending input for PCI Target side
|
input req_req_pending_in ; // request pending input for PCI Target side
|
input req_comp_pending_in ; // completion pending input for PCI Target side - it indicates when completion
|
input req_comp_pending_in ; // completion pending input for PCI Target side - it indicates when completion
|
// is ready for completing on PCI Target bus
|
// is ready for completing on PCI Target bus
|
// various data outputs - PCI Target sets address, bus command, byte enables, write enable and burst
|
// various data outputs - PCI Target sets address, bus command, byte enables, write enable and burst
|
output [31:0] addr_out ; // address bus output
|
output [31:0] addr_out ; // address bus output
|
output [3:0] be_out ; // byte enable output
|
output [3:0] be_out ; // byte enable output
|
output we_out ; // write enable output - read/write request indication 1 = write request / 0 = read request
|
output we_out ; // write enable output - read/write request indication 1 = write request / 0 = read request
|
output [3:0] bc_out ; // bus command output
|
output [3:0] bc_out ; // bus command output
|
output burst_ok_out ; // pre-fetch enable & burst read - qualifies pre-fetch for access to current image space
|
output burst_ok_out ; // pre-fetch enable & burst read - qualifies pre-fetch for access to current image space
|
|
|
// completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completion
|
// completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completion
|
input [31:0] strd_addr_in ; // Stored requested read access address
|
input [31:0] strd_addr_in ; // Stored requested read access address
|
input [3:0] strd_bc_in ; // Stored requested read access bus command
|
input [3:0] strd_bc_in ; // Stored requested read access bus command
|
input status_in ; // Error status reported - NOT USED because FIFO control bits determin data error status
|
input status_in ; // Error status reported - NOT USED because FIFO control bits determin data error status
|
input comp_flush_in ; // If completition counter (2^16 clk periods) has expired, PCIR_FIFO must flush data
|
input comp_flush_in ; // If completition counter (2^16 clk periods) has expired, PCIR_FIFO must flush data
|
|
|
|
|
/*==================================================================================================================
|
/*==================================================================================================================
|
PCIR_PCIW_FIFO signals from pci side
|
PCIR_PCIW_FIFO signals from pci side
|
==================================================================================================================*/
|
==================================================================================================================*/
|
// PCIR_FIFO control signals used for fetching data from PCIR_FIFO
|
// PCIR_FIFO control signals used for fetching data from PCIR_FIFO
|
output pcir_fifo_renable_out ; // read enable output to PCIR_FIFO
|
output pcir_fifo_renable_out ; // read enable output to PCIR_FIFO
|
input [31:0] pcir_fifo_data_in ; // data input from PCIR_FIFO
|
input [31:0] pcir_fifo_data_in ; // data input from PCIR_FIFO
|
input [3:0] pcir_fifo_be_in ; // byte enable input from PCIR_FIFO
|
input [3:0] pcir_fifo_be_in ; // byte enable input from PCIR_FIFO
|
input [3:0] pcir_fifo_control_in ; // control signals input from PCIR_FIFO
|
input [3:0] pcir_fifo_control_in ; // control signals input from PCIR_FIFO
|
output pcir_fifo_flush_out ; // flush PCIR_FIFO
|
output pcir_fifo_flush_out ; // flush PCIR_FIFO
|
input pcir_fifo_almost_empty_in ; // almost empty indicator from PCIR_FIFO
|
input pcir_fifo_almost_empty_in ; // almost empty indicator from PCIR_FIFO
|
input pcir_fifo_empty_in ; // empty indicator
|
input pcir_fifo_empty_in ; // empty indicator
|
|
|
// PCIW_FIFO control signals used for sinking data into PCIW_FIFO and status monitoring
|
// PCIW_FIFO control signals used for sinking data into PCIW_FIFO and status monitoring
|
output pciw_fifo_wenable_out ; // write enable output to PCIW_FIFO
|
output pciw_fifo_wenable_out ; // write enable output to PCIW_FIFO
|
output [31:0] pciw_fifo_addr_data_out ; // address / data output signals to PCIW_FIFO
|
output [31:0] pciw_fifo_addr_data_out ; // address / data output signals to PCIW_FIFO
|
output [3:0] pciw_fifo_cbe_out ; // command / byte enable signals to PCIW_FIFO
|
output [3:0] pciw_fifo_cbe_out ; // command / byte enable signals to PCIW_FIFO
|
output [3:0] pciw_fifo_control_out ; // control signals to PCIW_FIFO
|
output [3:0] pciw_fifo_control_out ; // control signals to PCIW_FIFO
|
input pciw_fifo_two_left_in ; // two data spaces left in PCIW_FIFO
|
input pciw_fifo_two_left_in ; // two data spaces left in PCIW_FIFO
|
input pciw_fifo_almost_full_in ; // almost full indicator from PCIW_FIFO
|
input pciw_fifo_almost_full_in ; // almost full indicator from PCIW_FIFO
|
input pciw_fifo_full_in ; // full indicator from PCIW_FIFO
|
input pciw_fifo_full_in ; // full indicator from PCIW_FIFO
|
|
|
// WBW_FIFO empy control signal used when delayed read is complete in PCIR_FIFO
|
// WBW_FIFO empy control signal used when delayed read is complete in PCIR_FIFO
|
input wbw_fifo_empty_in ; // empty indicator from WBW_FIFO
|
input wbw_fifo_empty_in ; // empty indicator from WBW_FIFO
|
input wbu_del_read_comp_pending_in ; // delayed read pending indicator from WB Unit
|
input wbu_del_read_comp_pending_in ; // delayed read pending indicator from WB Unit
|
|
|
|
|
/*==================================================================================================================
|
/*==================================================================================================================
|
Configuration space signals - from and to registers
|
Configuration space signals - from and to registers
|
==================================================================================================================*/
|
==================================================================================================================*/
|
// BUS for reading and writing to configuration space registers
|
// BUS for reading and writing to configuration space registers
|
output conf_hit_out ; // like "chip select" for configuration space
|
output conf_hit_out ; // like "chip select" for configuration space
|
output [11:0] conf_addr_out ; // address to configuration space when there is access to it
|
output [11:0] conf_addr_out ; // address to configuration space when there is access to it
|
output [31:0] conf_data_out ; // data to configuration space - for writing to registers
|
output [31:0] conf_data_out ; // data to configuration space - for writing to registers
|
input [31:0] conf_data_in ; // data from configuration space - for reading from registers
|
input [31:0] conf_data_in ; // data from configuration space - for reading from registers
|
output [3:0] conf_be_out ; // byte enables used for correct writing to configuration space
|
output [3:0] conf_be_out ; // byte enables used for correct writing to configuration space
|
output conf_we_out ; // write enable control signal - 1 for writing / 0 for nothing
|
output conf_we_out ; // write enable control signal - 1 for writing / 0 for nothing
|
output conf_re_out ; // read enable control signal - 1 for reading / 0 for nothing
|
output conf_re_out ; // read enable control signal - 1 for reading / 0 for nothing
|
|
|
// Inputs for image control registers
|
// Inputs for image control registers
|
input mem_enable_in ; // allowed access to memory mapped image
|
input mem_enable_in ; // allowed access to memory mapped image
|
input io_enable_in ; // allowed access to io mapped image
|
input io_enable_in ; // allowed access to io mapped image
|
|
|
// Inputs needed for determining if image is assigned to memory or io space with pre-fetch and address translation
|
// Inputs needed for determining if image is assigned to memory or io space with pre-fetch and address translation
|
input mem_io_addr_space0_in ; // bit-0 in pci_base_addr0 register
|
input mem_io_addr_space0_in ; // bit-0 in pci_base_addr0 register
|
input mem_io_addr_space1_in ; // bit-0 in pci_base_addr1 register
|
input mem_io_addr_space1_in ; // bit-0 in pci_base_addr1 register
|
input mem_io_addr_space2_in ; // bit-0 in pci_base_addr2 register
|
input mem_io_addr_space2_in ; // bit-0 in pci_base_addr2 register
|
input mem_io_addr_space3_in ; // bit-0 in pci_base_addr3 register
|
input mem_io_addr_space3_in ; // bit-0 in pci_base_addr3 register
|
input mem_io_addr_space4_in ; // bit-0 in pci_base_addr4 register
|
input mem_io_addr_space4_in ; // bit-0 in pci_base_addr4 register
|
input mem_io_addr_space5_in ; // bit-0 in pci_base_addr5 register
|
input mem_io_addr_space5_in ; // bit-0 in pci_base_addr5 register
|
input pre_fetch_en0_in ; // bit-1 in pci_image_ctr0 register
|
input pre_fetch_en0_in ; // bit-1 in pci_image_ctr0 register
|
input pre_fetch_en1_in ; // bit-1 in pci_image_ctr1 register
|
input pre_fetch_en1_in ; // bit-1 in pci_image_ctr1 register
|
input pre_fetch_en2_in ; // bit-1 in pci_image_ctr2 register
|
input pre_fetch_en2_in ; // bit-1 in pci_image_ctr2 register
|
input pre_fetch_en3_in ; // bit-1 in pci_image_ctr3 register
|
input pre_fetch_en3_in ; // bit-1 in pci_image_ctr3 register
|
input pre_fetch_en4_in ; // bit-1 in pci_image_ctr4 register
|
input pre_fetch_en4_in ; // bit-1 in pci_image_ctr4 register
|
input pre_fetch_en5_in ; // bit-1 in pci_image_ctr5 register
|
input pre_fetch_en5_in ; // bit-1 in pci_image_ctr5 register
|
|
|
// Input from image registers - register values needed for decoder to work properly
|
// Input from image registers - register values needed for decoder to work properly
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr0_in ; // base address from base address register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr0_in ; // base address from base address register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr1_in ; // base address from base address register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr1_in ; // base address from base address register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr2_in ; // base address from base address register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr2_in ; // base address from base address register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr3_in ; // base address from base address register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr3_in ; // base address from base address register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr4_in ; // base address from base address register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr4_in ; // base address from base address register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr5_in ; // base address from base address register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr5_in ; // base address from base address register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask0_in ; // masking of base address from address mask register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask0_in ; // masking of base address from address mask register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask1_in ; // masking of base address from address mask register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask1_in ; // masking of base address from address mask register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask2_in ; // masking of base address from address mask register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask2_in ; // masking of base address from address mask register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask3_in ; // masking of base address from address mask register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask3_in ; // masking of base address from address mask register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask4_in ; // masking of base address from address mask register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask4_in ; // masking of base address from address mask register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask5_in ; // masking of base address from address mask register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask5_in ; // masking of base address from address mask register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr0_in ; // translation address from address translation register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr0_in ; // translation address from address translation register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr1_in ; // translation address from address translation register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr1_in ; // translation address from address translation register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr2_in ; // translation address from address translation register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr2_in ; // translation address from address translation register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr3_in ; // translation address from address translation register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr3_in ; // translation address from address translation register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr4_in ; // translation address from address translation register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr4_in ; // translation address from address translation register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr5_in ; // translation address from address translation register
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr5_in ; // translation address from address translation register
|
|
|
input addr_tran_en0_in ; // address translation enable bit
|
input addr_tran_en0_in ; // address translation enable bit
|
input addr_tran_en1_in ; // address translation enable bit
|
input addr_tran_en1_in ; // address translation enable bit
|
input addr_tran_en2_in ; // address translation enable bit
|
input addr_tran_en2_in ; // address translation enable bit
|
input addr_tran_en3_in ; // address translation enable bit
|
input addr_tran_en3_in ; // address translation enable bit
|
input addr_tran_en4_in ; // address translation enable bit
|
input addr_tran_en4_in ; // address translation enable bit
|
input addr_tran_en5_in ; // address translation enable bit
|
input addr_tran_en5_in ; // address translation enable bit
|
|
|
/*==================================================================================================================
|
/*==================================================================================================================
|
END of input / output PORT DEFINITONS !!!
|
END of input / output PORT DEFINITONS !!!
|
==================================================================================================================*/
|
==================================================================================================================*/
|
|
|
// address output from address multiplexer
|
// address output from address multiplexer
|
reg [31:0] address ;
|
reg [31:0] address ;
|
// prefetch enable for access to selected image space
|
// prefetch enable for access to selected image space
|
reg pre_fetch_en ;
|
reg pre_fetch_en ;
|
|
|
// Input addresses and image hits from address decoders - addresses are multiplexed to address
|
// Input addresses and image hits from address decoders - addresses are multiplexed to address
|
`ifdef HOST
|
`ifdef HOST
|
`ifdef NO_CNF_IMAGE
|
`ifdef NO_CNF_IMAGE
|
`ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
|
`ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
|
wire hit0_in ;
|
wire hit0_in ;
|
wire [31:0] address0_in ;
|
wire [31:0] address0_in ;
|
wire pre_fetch_en0 = pre_fetch_en0_in ;
|
wire pre_fetch_en0 = pre_fetch_en0_in ;
|
`else
|
`else
|
wire hit0_in = 1'b0 ;
|
wire hit0_in = 1'b0 ;
|
wire [31:0] address0_in = 32'h0 ;
|
wire [31:0] address0_in = 32'h0 ;
|
wire pre_fetch_en0 = 1'b0 ;
|
wire pre_fetch_en0 = 1'b0 ;
|
`endif
|
`endif
|
`else
|
`else
|
wire hit0_in ;
|
wire hit0_in ;
|
wire [31:0] address0_in ;
|
wire [31:0] address0_in ;
|
wire pre_fetch_en0 = pre_fetch_en0_in ;
|
wire pre_fetch_en0 = pre_fetch_en0_in ;
|
`endif
|
`endif
|
`else // GUEST
|
`else // GUEST
|
wire hit0_in ;
|
wire hit0_in ;
|
wire [31:0] address0_in ;
|
wire [31:0] address0_in ;
|
wire pre_fetch_en0 = pre_fetch_en0_in ;
|
wire pre_fetch_en0 = pre_fetch_en0_in ;
|
`endif
|
`endif
|
|
|
wire hit1_in ;
|
wire hit1_in ;
|
wire [31:0] address1_in ;
|
wire [31:0] address1_in ;
|
wire pre_fetch_en1 = pre_fetch_en1_in ;
|
wire pre_fetch_en1 = pre_fetch_en1_in ;
|
|
|
`ifdef PCI_IMAGE2
|
`ifdef PCI_IMAGE2
|
wire hit2_in ;
|
wire hit2_in ;
|
wire [31:0] address2_in ;
|
wire [31:0] address2_in ;
|
wire pre_fetch_en2 = pre_fetch_en2_in ;
|
wire pre_fetch_en2 = pre_fetch_en2_in ;
|
`else
|
`else
|
wire hit2_in = 1'b0 ;
|
wire hit2_in = 1'b0 ;
|
wire [31:0] address2_in = 32'h0 ;
|
wire [31:0] address2_in = 32'h0 ;
|
wire pre_fetch_en2 = 1'b0 ;
|
wire pre_fetch_en2 = 1'b0 ;
|
`endif
|
`endif
|
|
|
`ifdef PCI_IMAGE3
|
`ifdef PCI_IMAGE3
|
wire hit3_in ;
|
wire hit3_in ;
|
wire [31:0] address3_in ;
|
wire [31:0] address3_in ;
|
wire pre_fetch_en3 = pre_fetch_en3_in ;
|
wire pre_fetch_en3 = pre_fetch_en3_in ;
|
`else
|
`else
|
wire hit3_in = 1'b0 ;
|
wire hit3_in = 1'b0 ;
|
wire [31:0] address3_in = 32'h0 ;
|
wire [31:0] address3_in = 32'h0 ;
|
wire pre_fetch_en3 = 1'b0 ;
|
wire pre_fetch_en3 = 1'b0 ;
|
`endif
|
`endif
|
|
|
`ifdef PCI_IMAGE4
|
`ifdef PCI_IMAGE4
|
wire hit4_in ;
|
wire hit4_in ;
|
wire [31:0] address4_in ;
|
wire [31:0] address4_in ;
|
wire pre_fetch_en4 = pre_fetch_en4_in ;
|
wire pre_fetch_en4 = pre_fetch_en4_in ;
|
`else
|
`else
|
wire hit4_in = 1'b0 ;
|
wire hit4_in = 1'b0 ;
|
wire [31:0] address4_in = 32'h0 ;
|
wire [31:0] address4_in = 32'h0 ;
|
wire pre_fetch_en4 = 1'b0 ;
|
wire pre_fetch_en4 = 1'b0 ;
|
`endif
|
`endif
|
|
|
`ifdef PCI_IMAGE5
|
`ifdef PCI_IMAGE5
|
wire hit5_in ;
|
wire hit5_in ;
|
wire [31:0] address5_in ;
|
wire [31:0] address5_in ;
|
wire pre_fetch_en5 = pre_fetch_en5_in ;
|
wire pre_fetch_en5 = pre_fetch_en5_in ;
|
`else
|
`else
|
wire hit5_in = 1'b0 ;
|
wire hit5_in = 1'b0 ;
|
wire [31:0] address5_in = 32'h0 ;
|
wire [31:0] address5_in = 32'h0 ;
|
wire pre_fetch_en5 = 1'b0 ;
|
wire pre_fetch_en5 = 1'b0 ;
|
`endif
|
`endif
|
|
|
// Include address decoders
|
// Include address decoders
|
`ifdef HOST
|
`ifdef HOST
|
`ifdef NO_CNF_IMAGE
|
`ifdef NO_CNF_IMAGE
|
`ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
|
`ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder0
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder0
|
(.hit (hit0_in),
|
(.hit (hit0_in),
|
.addr_out (address0_in),
|
.addr_out (address0_in),
|
.addr_in (address_in),
|
.addr_in (address_in),
|
.bc_in (bc_in),
|
.bc_in (bc_in),
|
.base_addr (pci_base_addr0_in),
|
.base_addr (pci_base_addr0_in),
|
.mask_addr (pci_addr_mask0_in),
|
.mask_addr (pci_addr_mask0_in),
|
.tran_addr (pci_tran_addr0_in),
|
.tran_addr (pci_tran_addr0_in),
|
.at_en (addr_tran_en0_in),
|
.at_en (addr_tran_en0_in),
|
.mem_io_space (mem_io_addr_space0_in),
|
.mem_io_space (mem_io_addr_space0_in),
|
.mem_en (mem_enable_in),
|
.mem_en (mem_enable_in),
|
.io_en (io_enable_in)
|
.io_en (io_enable_in)
|
) ;
|
) ;
|
`endif
|
`endif
|
`else
|
`else
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder0
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder0
|
(.hit (hit0_in),
|
(.hit (hit0_in),
|
.addr_out (address0_in),
|
.addr_out (address0_in),
|
.addr_in (address_in),
|
.addr_in (address_in),
|
.bc_in (bc_in),
|
.bc_in (bc_in),
|
.base_addr (pci_base_addr0_in),
|
.base_addr (pci_base_addr0_in),
|
.mask_addr (pci_addr_mask0_in),
|
.mask_addr (pci_addr_mask0_in),
|
.tran_addr (pci_tran_addr0_in),
|
.tran_addr (pci_tran_addr0_in),
|
.at_en (addr_tran_en0_in),
|
.at_en (addr_tran_en0_in),
|
.mem_io_space (mem_io_addr_space0_in),
|
.mem_io_space (mem_io_addr_space0_in),
|
.mem_en (mem_enable_in),
|
.mem_en (mem_enable_in),
|
.io_en (io_enable_in)
|
.io_en (io_enable_in)
|
) ;
|
) ;
|
`endif
|
`endif
|
`else // GUEST
|
`else // GUEST
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder0
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder0
|
(.hit (hit0_in),
|
(.hit (hit0_in),
|
.addr_out (address0_in),
|
.addr_out (address0_in),
|
.addr_in (address_in),
|
.addr_in (address_in),
|
.bc_in (bc_in),
|
.bc_in (bc_in),
|
.base_addr (pci_base_addr0_in),
|
.base_addr (pci_base_addr0_in),
|
.mask_addr (pci_addr_mask0_in),
|
.mask_addr (pci_addr_mask0_in),
|
.tran_addr (pci_tran_addr0_in),
|
.tran_addr (pci_tran_addr0_in),
|
.at_en (addr_tran_en0_in),
|
.at_en (addr_tran_en0_in),
|
.mem_io_space (mem_io_addr_space0_in),
|
.mem_io_space (mem_io_addr_space0_in),
|
.mem_en (mem_enable_in),
|
.mem_en (mem_enable_in),
|
.io_en (io_enable_in)
|
.io_en (io_enable_in)
|
) ;
|
) ;
|
`endif
|
`endif
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder1
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder1
|
(.hit (hit1_in),
|
(.hit (hit1_in),
|
.addr_out (address1_in),
|
.addr_out (address1_in),
|
.addr_in (address_in),
|
.addr_in (address_in),
|
.bc_in (bc_in),
|
.bc_in (bc_in),
|
.base_addr (pci_base_addr1_in),
|
.base_addr (pci_base_addr1_in),
|
.mask_addr (pci_addr_mask1_in),
|
.mask_addr (pci_addr_mask1_in),
|
.tran_addr (pci_tran_addr1_in),
|
.tran_addr (pci_tran_addr1_in),
|
.at_en (addr_tran_en1_in),
|
.at_en (addr_tran_en1_in),
|
.mem_io_space (mem_io_addr_space1_in),
|
.mem_io_space (mem_io_addr_space1_in),
|
.mem_en (mem_enable_in),
|
.mem_en (mem_enable_in),
|
.io_en (io_enable_in)
|
.io_en (io_enable_in)
|
) ;
|
) ;
|
`ifdef PCI_IMAGE2
|
`ifdef PCI_IMAGE2
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
|
(.hit (hit2_in),
|
(.hit (hit2_in),
|
.addr_out (address2_in),
|
.addr_out (address2_in),
|
.addr_in (address_in),
|
.addr_in (address_in),
|
.bc_in (bc_in),
|
.bc_in (bc_in),
|
.base_addr (pci_base_addr2_in),
|
.base_addr (pci_base_addr2_in),
|
.mask_addr (pci_addr_mask2_in),
|
.mask_addr (pci_addr_mask2_in),
|
.tran_addr (pci_tran_addr2_in),
|
.tran_addr (pci_tran_addr2_in),
|
.at_en (addr_tran_en2_in),
|
.at_en (addr_tran_en2_in),
|
.mem_io_space (mem_io_addr_space2_in),
|
.mem_io_space (mem_io_addr_space2_in),
|
.mem_en (mem_enable_in),
|
.mem_en (mem_enable_in),
|
.io_en (io_enable_in)
|
.io_en (io_enable_in)
|
) ;
|
) ;
|
`endif
|
`endif
|
`ifdef PCI_IMAGE3
|
`ifdef PCI_IMAGE3
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
|
(.hit (hit3_in),
|
(.hit (hit3_in),
|
.addr_out (address3_in),
|
.addr_out (address3_in),
|
.addr_in (address_in),
|
.addr_in (address_in),
|
.bc_in (bc_in),
|
.bc_in (bc_in),
|
.base_addr (pci_base_addr3_in),
|
.base_addr (pci_base_addr3_in),
|
.mask_addr (pci_addr_mask3_in),
|
.mask_addr (pci_addr_mask3_in),
|
.tran_addr (pci_tran_addr3_in),
|
.tran_addr (pci_tran_addr3_in),
|
.at_en (addr_tran_en3_in),
|
.at_en (addr_tran_en3_in),
|
.mem_io_space (mem_io_addr_space3_in),
|
.mem_io_space (mem_io_addr_space3_in),
|
.mem_en (mem_enable_in),
|
.mem_en (mem_enable_in),
|
.io_en (io_enable_in)
|
.io_en (io_enable_in)
|
) ;
|
) ;
|
`endif
|
`endif
|
`ifdef PCI_IMAGE4
|
`ifdef PCI_IMAGE4
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder4
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder4
|
(.hit (hit4_in),
|
(.hit (hit4_in),
|
.addr_out (address4_in),
|
.addr_out (address4_in),
|
.addr_in (address_in),
|
.addr_in (address_in),
|
.bc_in (bc_in),
|
.bc_in (bc_in),
|
.base_addr (pci_base_addr4_in),
|
.base_addr (pci_base_addr4_in),
|
.mask_addr (pci_addr_mask4_in),
|
.mask_addr (pci_addr_mask4_in),
|
.tran_addr (pci_tran_addr4_in),
|
.tran_addr (pci_tran_addr4_in),
|
.at_en (addr_tran_en4_in),
|
.at_en (addr_tran_en4_in),
|
.mem_io_space (mem_io_addr_space4_in),
|
.mem_io_space (mem_io_addr_space4_in),
|
.mem_en (mem_enable_in),
|
.mem_en (mem_enable_in),
|
.io_en (io_enable_in)
|
.io_en (io_enable_in)
|
) ;
|
) ;
|
`endif
|
`endif
|
`ifdef PCI_IMAGE5
|
`ifdef PCI_IMAGE5
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder5
|
PCI_DECODER #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder5
|
(.hit (hit5_in),
|
(.hit (hit5_in),
|
.addr_out (address5_in),
|
.addr_out (address5_in),
|
.addr_in (address_in),
|
.addr_in (address_in),
|
.bc_in (bc_in),
|
.bc_in (bc_in),
|
.base_addr (pci_base_addr5_in),
|
.base_addr (pci_base_addr5_in),
|
.mask_addr (pci_addr_mask5_in),
|
.mask_addr (pci_addr_mask5_in),
|
.tran_addr (pci_tran_addr5_in),
|
.tran_addr (pci_tran_addr5_in),
|
.at_en (addr_tran_en5_in),
|
.at_en (addr_tran_en5_in),
|
.mem_io_space (mem_io_addr_space5_in),
|
.mem_io_space (mem_io_addr_space5_in),
|
.mem_en (mem_enable_in),
|
.mem_en (mem_enable_in),
|
.io_en (io_enable_in)
|
.io_en (io_enable_in)
|
) ;
|
) ;
|
`endif
|
`endif
|
|
|
// Internal signals for image hit determination
|
// Internal signals for image hit determination
|
reg addr_claim ;// address claim signal is asinchronous set for addr_claim_out signal to PCI Target SM
|
reg addr_claim ;// address claim signal is asinchronous set for addr_claim_out signal to PCI Target SM
|
|
|
// Determining if image 0 is assigned to configuration space or as normal pci to wb access!
|
// Determining if image 0 is assigned to configuration space or as normal pci to wb access!
|
// if normal access is allowed to configuration space, then hit0 is hit0_conf
|
// if normal access is allowed to configuration space, then hit0 is hit0_conf
|
`ifdef HOST
|
`ifdef HOST
|
`ifdef NO_CNF_IMAGE
|
`ifdef NO_CNF_IMAGE
|
parameter hit0_conf = 1'b0 ;
|
parameter hit0_conf = 1'b0 ;
|
`else
|
`else
|
parameter hit0_conf = 1'b1 ; // if normal access is allowed to configuration space, then hit0 is hit0_conf
|
parameter hit0_conf = 1'b1 ; // if normal access is allowed to configuration space, then hit0 is hit0_conf
|
`endif
|
`endif
|
`else // GUEST
|
`else // GUEST
|
parameter hit0_conf = 1'b1 ; // if normal access is allowed to configuration space, then hit0 is hit0_conf
|
parameter hit0_conf = 1'b1 ; // if normal access is allowed to configuration space, then hit0 is hit0_conf
|
`endif
|
`endif
|
|
|
// Logic with address mux, determining if address is still in the same image space and if it is prefetced or not
|
// Logic with address mux, determining if address is still in the same image space and if it is prefetced or not
|
always@(hit5_in or hit4_in or hit3_in or hit2_in or hit1_in or hit0_in or
|
always@(hit5_in or hit4_in or hit3_in or hit2_in or hit1_in or hit0_in or
|
address5_in or address4_in or address3_in or address2_in or address1_in or address0_in or
|
address5_in or address4_in or address3_in or address2_in or address1_in or address0_in or
|
pre_fetch_en5 or
|
pre_fetch_en5 or
|
pre_fetch_en4 or
|
pre_fetch_en4 or
|
pre_fetch_en3 or
|
pre_fetch_en3 or
|
pre_fetch_en2 or
|
pre_fetch_en2 or
|
pre_fetch_en1 or
|
pre_fetch_en1 or
|
pre_fetch_en0
|
pre_fetch_en0
|
)
|
)
|
begin
|
begin
|
addr_claim <= (hit5_in || hit4_in) || (hit3_in || hit2_in || hit1_in || hit0_in) ;
|
addr_claim <= (hit5_in || hit4_in) || (hit3_in || hit2_in || hit1_in || hit0_in) ;
|
case ({hit5_in, hit4_in, hit3_in, hit2_in, hit0_in})
|
case ({hit5_in, hit4_in, hit3_in, hit2_in, hit0_in})
|
5'b10000 :
|
5'b10000 :
|
begin
|
begin
|
address <= address5_in ;
|
address <= address5_in ;
|
pre_fetch_en <= pre_fetch_en5 ;
|
pre_fetch_en <= pre_fetch_en5 ;
|
end
|
end
|
5'b01000 :
|
5'b01000 :
|
begin
|
begin
|
address <= address4_in ;
|
address <= address4_in ;
|
pre_fetch_en <= pre_fetch_en4 ;
|
pre_fetch_en <= pre_fetch_en4 ;
|
end
|
end
|
5'b00100 :
|
5'b00100 :
|
begin
|
begin
|
address <= address3_in ;
|
address <= address3_in ;
|
pre_fetch_en <= pre_fetch_en3 ;
|
pre_fetch_en <= pre_fetch_en3 ;
|
end
|
end
|
5'b00010 :
|
5'b00010 :
|
begin
|
begin
|
address <= address2_in ;
|
address <= address2_in ;
|
pre_fetch_en <= pre_fetch_en2 ;
|
pre_fetch_en <= pre_fetch_en2 ;
|
end
|
end
|
5'b00001 :
|
5'b00001 :
|
begin
|
begin
|
address <= address0_in ;
|
address <= address0_in ;
|
pre_fetch_en <= pre_fetch_en0 ;
|
pre_fetch_en <= pre_fetch_en0 ;
|
end
|
end
|
default : // IMAGE 1 is always included into PCI bridge
|
default : // IMAGE 1 is always included into PCI bridge
|
begin
|
begin
|
address <= address1_in ;
|
address <= address1_in ;
|
pre_fetch_en <= pre_fetch_en1 ;
|
pre_fetch_en <= pre_fetch_en1 ;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
// Address claim output to PCI Target SM
|
// Address claim output to PCI Target SM
|
assign addr_claim_out = addr_claim ;
|
assign addr_claim_out = addr_claim ;
|
|
|
reg [31:0] norm_address ; // stored normal address (decoded and translated) for access to WB
|
reg [31:0] norm_address ; // stored normal address (decoded and translated) for access to WB
|
reg norm_prf_en ; // stored pre-fetch enable
|
reg norm_prf_en ; // stored pre-fetch enable
|
reg [3:0] norm_bc ; // stored bus-command
|
reg [3:0] norm_bc ; // stored bus-command
|
reg same_read_reg ; // stored SAME_READ information
|
reg same_read_reg ; // stored SAME_READ information
|
reg target_rd ; // delayed registered TRDY output equivalent signal
|
reg target_rd ; // delayed registered TRDY output equivalent signal
|
|
|
always@(posedge clk_in or posedge reset_in)
|
always@(posedge clk_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
begin
|
begin
|
norm_address <= #`FF_DELAY 32'h0000_0000 ;
|
norm_address <= #`FF_DELAY 32'h0000_0000 ;
|
norm_prf_en <= #`FF_DELAY 1'b0 ;
|
norm_prf_en <= #`FF_DELAY 1'b0 ;
|
norm_bc <= #`FF_DELAY 4'h0 ;
|
norm_bc <= #`FF_DELAY 4'h0 ;
|
same_read_reg <= #`FF_DELAY 1'b0 ;
|
same_read_reg <= #`FF_DELAY 1'b0 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (addr_phase_in)
|
if (addr_phase_in)
|
begin
|
begin
|
norm_address <= #`FF_DELAY address ;
|
norm_address <= #`FF_DELAY address ;
|
norm_prf_en <= #`FF_DELAY pre_fetch_en ;
|
norm_prf_en <= #`FF_DELAY pre_fetch_en ;
|
norm_bc <= #`FF_DELAY bc_in ;
|
norm_bc <= #`FF_DELAY bc_in ;
|
same_read_reg <= #`FF_DELAY same_read_out ;
|
same_read_reg <= #`FF_DELAY same_read_out ;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
`ifdef HOST
|
`ifdef HOST
|
`ifdef NO_CNF_IMAGE
|
`ifdef NO_CNF_IMAGE
|
reg [1:0] strd_address ; // stored INPUT address for accessing Configuration space registers
|
reg [1:0] strd_address ; // stored INPUT address for accessing Configuration space registers
|
`else
|
`else
|
reg [11:0] strd_address ; // stored INPUT address for accessing Configuration space registers
|
reg [11:0] strd_address ; // stored INPUT address for accessing Configuration space registers
|
`endif
|
`endif
|
`else
|
`else
|
reg [11:0] strd_address ; // stored INPUT address for accessing Configuration space registers
|
reg [11:0] strd_address ; // stored INPUT address for accessing Configuration space registers
|
`endif
|
`endif
|
always@(posedge clk_in or posedge reset_in)
|
always@(posedge clk_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
begin
|
begin
|
strd_address <= #`FF_DELAY 0 ;
|
strd_address <= #`FF_DELAY 0 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (addr_phase_in)
|
if (addr_phase_in)
|
begin
|
begin
|
`ifdef HOST
|
`ifdef HOST
|
`ifdef NO_CNF_IMAGE
|
`ifdef NO_CNF_IMAGE
|
strd_address <= #`FF_DELAY address_in[1:0] ;
|
strd_address <= #`FF_DELAY address_in[1:0] ;
|
`else
|
`else
|
strd_address <= #`FF_DELAY address_in[11:0] ;
|
strd_address <= #`FF_DELAY address_in[11:0] ;
|
`endif
|
`endif
|
`else
|
`else
|
strd_address <= #`FF_DELAY address_in[11:0] ;
|
strd_address <= #`FF_DELAY address_in[11:0] ;
|
`endif
|
`endif
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always@(posedge clk_in or posedge reset_in)
|
always@(posedge clk_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
begin
|
begin
|
target_rd <= #`FF_DELAY 1'b0 ;
|
target_rd <= #`FF_DELAY 1'b0 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (same_read_reg && !bckp_trdy_in)
|
if (same_read_reg && !bckp_trdy_in)
|
target_rd <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus
|
target_rd <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus
|
else if (same_read_reg && bckp_devsel_in && !bckp_stop_in)
|
else if (same_read_reg && bckp_devsel_in && !bckp_stop_in)
|
target_rd <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus
|
target_rd <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus
|
else if ((!same_read_reg) || (last_reg_in && target_rd))
|
else if ((!same_read_reg) || (last_reg_in && target_rd))
|
target_rd <= #`FF_DELAY 1'b0 ;// Signal indicates when target ready is deaserted on PCI bus
|
target_rd <= #`FF_DELAY 1'b0 ;// Signal indicates when target ready is deaserted on PCI bus
|
end
|
end
|
end
|
end
|
// '1' indicates asserted TRDY signal when same read operation is performed
|
// '1' indicates asserted TRDY signal when same read operation is performed
|
wire target_rd_completed = target_rd ;
|
wire target_rd_completed = target_rd ;
|
|
|
reg same_read_request ;
|
reg same_read_request ;
|
|
|
// When delayed read is completed on WB, addres and bc must be compered, if there is the same read request
|
// When delayed read is completed on WB, addres and bc must be compered, if there is the same read request
|
always@(address or strd_addr_in or bc_in or strd_bc_in)
|
always@(address or strd_addr_in or bc_in or strd_bc_in)
|
begin
|
begin
|
if ((address == strd_addr_in) & (bc_in == strd_bc_in))
|
if ((address == strd_addr_in) & (bc_in == strd_bc_in))
|
same_read_request <= 1'b1 ;
|
same_read_request <= 1'b1 ;
|
else
|
else
|
same_read_request <= 1'b0 ;
|
same_read_request <= 1'b0 ;
|
end
|
end
|
|
|
assign same_read_out = (same_read_request) ; // && ~pcir_fifo_empty_in) ;
|
assign same_read_out = (same_read_request) ; // && ~pcir_fifo_empty_in) ;
|
|
|
// Signals for byte enable checking
|
// Signals for byte enable checking
|
reg addr_burst_ok ;
|
reg addr_burst_ok ;
|
reg io_be_ok ;
|
reg io_be_ok ;
|
|
|
// Byte enable checking for IO, MEMORY and CONFIGURATION spaces - be_in is active low!
|
// Byte enable checking for IO, MEMORY and CONFIGURATION spaces - be_in is active low!
|
always@(strd_address or be_in)
|
always@(strd_address or be_in)
|
begin
|
begin
|
case (strd_address[1:0])
|
case (strd_address[1:0])
|
2'b11 :
|
2'b11 :
|
begin
|
begin
|
addr_burst_ok <= 1'b0 ;
|
addr_burst_ok <= 1'b0 ;
|
io_be_ok <= (be_in[2] && be_in[1] && be_in[0]) ; // only be3 can be active
|
io_be_ok <= (be_in[2] && be_in[1] && be_in[0]) ; // only be3 can be active
|
end
|
end
|
2'b10 :
|
2'b10 :
|
begin
|
begin
|
addr_burst_ok <= 1'b0 ;
|
addr_burst_ok <= 1'b0 ;
|
io_be_ok <= (~be_in[2] && be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
|
io_be_ok <= (~be_in[2] && be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
|
end
|
end
|
2'b01 :
|
2'b01 :
|
begin
|
begin
|
addr_burst_ok <= 1'b0 ;
|
addr_burst_ok <= 1'b0 ;
|
io_be_ok <= (~be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
|
io_be_ok <= (~be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
|
end
|
end
|
default : // 2'b00
|
default : // 2'b00
|
begin
|
begin
|
addr_burst_ok <= 1'b1 ;
|
addr_burst_ok <= 1'b1 ;
|
io_be_ok <= (~be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
|
io_be_ok <= (~be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
wire calc_target_abort = (norm_bc[3:1] == `BC_IO_RW) ? !io_be_ok : 1'b0 ;
|
wire calc_target_abort = (norm_bc[3:1] == `BC_IO_RW) ? !io_be_ok : 1'b0 ;
|
|
|
wire [3:0] pcir_fifo_control_input = pcir_fifo_empty_in ? 4'h0 : pcir_fifo_control_in ;
|
wire [3:0] pcir_fifo_control_input = pcir_fifo_empty_in ? 4'h0 : pcir_fifo_control_in ;
|
|
|
// Medium registers for data and control busses from PCIR_FIFO
|
// Medium registers for data and control busses from PCIR_FIFO
|
reg [31:0] pcir_fifo_data_reg ;
|
reg [31:0] pcir_fifo_data_reg ;
|
reg [3:0] pcir_fifo_ctrl_reg ;
|
reg [3:0] pcir_fifo_ctrl_reg ;
|
|
|
always@(posedge clk_in or posedge reset_in)
|
always@(posedge clk_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
begin
|
begin
|
pcir_fifo_data_reg <= #`FF_DELAY 32'h0000_0000 ;
|
pcir_fifo_data_reg <= #`FF_DELAY 32'h0000_0000 ;
|
pcir_fifo_ctrl_reg <= #`FF_DELAY 4'h0 ;
|
pcir_fifo_ctrl_reg <= #`FF_DELAY 4'h0 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (load_medium_reg_in)
|
if (load_medium_reg_in)
|
begin
|
begin
|
pcir_fifo_data_reg <= #`FF_DELAY pcir_fifo_data_in ;
|
pcir_fifo_data_reg <= #`FF_DELAY pcir_fifo_data_in ;
|
pcir_fifo_ctrl_reg <= #`FF_DELAY pcir_fifo_control_input ;
|
pcir_fifo_ctrl_reg <= #`FF_DELAY pcir_fifo_control_input ;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
// when disconnect is signalled, the next data written to fifo will be the last
|
// when disconnect is signalled, the next data written to fifo will be the last
|
// also when this happens, disconnect must stay asserted until last data is written to the fifo
|
// also when this happens, disconnect must stay asserted until last data is written to the fifo
|
reg next_write_to_pciw_fifo_is_last ;
|
reg next_write_to_pciw_fifo_is_last ;
|
|
|
// selecting "fifo data" from medium registers or from PCIR_FIFO
|
// selecting "fifo data" from medium registers or from PCIR_FIFO
|
wire [31:0] pcir_fifo_data = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_data_in : pcir_fifo_data_reg ;
|
wire [31:0] pcir_fifo_data = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_data_in : pcir_fifo_data_reg ;
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wire [3:0] pcir_fifo_ctrl = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_control_input : pcir_fifo_ctrl_reg ;
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wire [3:0] pcir_fifo_ctrl = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_control_input : pcir_fifo_ctrl_reg ;
|
|
|
// signal assignments to PCI Target FSM
|
// signal assignments to PCI Target FSM
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assign read_completed_out = req_comp_pending_in ; // completion pending input for requesting side of the bridge
|
assign read_completed_out = req_comp_pending_in ; // completion pending input for requesting side of the bridge
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assign read_processing_out = req_req_pending_in ; // request pending input for requesting side
|
assign read_processing_out = req_req_pending_in ; // request pending input for requesting side
|
// when '1', the bus command is IO command - not supported commands are checked in pci_decoder modules
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// when '1', the bus command is IO command - not supported commands are checked in pci_decoder modules
|
wire io_memory_bus_command = !norm_bc[3] && !norm_bc[2] ;
|
wire io_memory_bus_command = !norm_bc[3] && !norm_bc[2] ;
|
assign disconect_wo_data_out = (
|
assign disconect_wo_data_out = (
|
((/*pcir_fifo_ctrl[`LAST_CTRL_BIT] ||*/ pcir_fifo_empty_in || ~burst_ok_out/*addr_burst_ok*/ || io_memory_bus_command) &&
|
((/*pcir_fifo_ctrl[`LAST_CTRL_BIT] ||*/ pcir_fifo_empty_in || ~burst_ok_out/*addr_burst_ok*/ || io_memory_bus_command) &&
|
~bc0_in && ~frame_reg_in) ||
|
~bc0_in && ~frame_reg_in) ||
|
((pciw_fifo_full_in || pciw_fifo_almost_full_in || next_write_to_pciw_fifo_is_last || (pciw_fifo_two_left_in && pciw_fifo_wenable_out) || ~addr_burst_ok || io_memory_bus_command) &&
|
((pciw_fifo_full_in || pciw_fifo_almost_full_in || next_write_to_pciw_fifo_is_last || (pciw_fifo_two_left_in && pciw_fifo_wenable_out) || ~addr_burst_ok || io_memory_bus_command) &&
|
bc0_in && ~frame_reg_in)
|
bc0_in && ~frame_reg_in)
|
) ;
|
) ;
|
assign disconect_w_data_out = (
|
assign disconect_w_data_out = (
|
( burst_ok_out && !io_memory_bus_command && ~bc0_in ) ||
|
( burst_ok_out && !io_memory_bus_command && ~bc0_in ) ||
|
( addr_burst_ok && !io_memory_bus_command && bc0_in )
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( addr_burst_ok && !io_memory_bus_command && bc0_in )
|
) ;
|
) ;
|
assign target_abort_out = ( ~addr_phase_in && calc_target_abort ) ;
|
assign target_abort_out = ( ~addr_phase_in && calc_target_abort ) ;
|
|
|
`ifdef HOST
|
`ifdef HOST
|
`ifdef NO_CNF_IMAGE
|
`ifdef NO_CNF_IMAGE
|
// signal assignments to PCI Target FSM
|
// signal assignments to PCI Target FSM
|
assign norm_access_to_config_out = 1'b0 ;
|
assign norm_access_to_config_out = 1'b0 ;
|
// control signal assignments to read request sinchronization module
|
// control signal assignments to read request sinchronization module
|
assign done_out = (target_rd_completed && last_reg_in) ;
|
assign done_out = (target_rd_completed && last_reg_in) ;
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assign in_progress_out = (same_read_reg && ~bckp_trdy_in) ;
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assign in_progress_out = (same_read_reg && ~bckp_trdy_in) ;
|
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
|
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
|
wire pcir_fifo_flush = (target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
|
wire pcir_fifo_flush = (target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
|
`else
|
`else
|
// signal assignments to PCI Target FSM
|
// signal assignments to PCI Target FSM
|
assign norm_access_to_config_out = (hit0_in && hit0_conf) ;
|
assign norm_access_to_config_out = (hit0_in && hit0_conf) ;
|
// control signal assignments to read request sinchronization module
|
// control signal assignments to read request sinchronization module
|
assign done_out = (~sel_conf_fifo_in && target_rd_completed && last_reg_in) ;
|
assign done_out = (~sel_conf_fifo_in && target_rd_completed && last_reg_in) ;
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assign in_progress_out = (~sel_conf_fifo_in && same_read_reg && ~bckp_trdy_in) ;
|
assign in_progress_out = (~sel_conf_fifo_in && same_read_reg && ~bckp_trdy_in) ;
|
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
|
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
|
wire pcir_fifo_flush = (~sel_conf_fifo_in && target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
|
wire pcir_fifo_flush = (~sel_conf_fifo_in && target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
|
`endif
|
`endif
|
`else
|
`else
|
// signal assignments to PCI Target FSM
|
// signal assignments to PCI Target FSM
|
assign norm_access_to_config_out = (hit0_in && hit0_conf) ;
|
assign norm_access_to_config_out = (hit0_in && hit0_conf) ;
|
// control signal assignments to read request sinchronization module
|
// control signal assignments to read request sinchronization module
|
assign done_out = (~sel_conf_fifo_in && target_rd_completed && last_reg_in) ;
|
assign done_out = (~sel_conf_fifo_in && target_rd_completed && last_reg_in) ;
|
assign in_progress_out = (~sel_conf_fifo_in && same_read_reg && ~bckp_trdy_in) ;
|
assign in_progress_out = (~sel_conf_fifo_in && same_read_reg && ~bckp_trdy_in) ;
|
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
|
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
|
wire pcir_fifo_flush = (~sel_conf_fifo_in && target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
|
wire pcir_fifo_flush = (~sel_conf_fifo_in && target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
|
`endif
|
`endif
|
|
|
// flush signal for PCIR_FIFO must be registered, since it asinchronously resets some status registers
|
// flush signal for PCIR_FIFO must be registered, since it asinchronously resets some status registers
|
wire pcir_fifo_flush_reg ;
|
wire pcir_fifo_flush_reg ;
|
async_reset_flop async_reset_as_pcir_flush
|
async_reset_flop async_reset_as_pcir_flush
|
(
|
(
|
.data_in (comp_flush_in || pcir_fifo_flush),
|
.data_in (comp_flush_in || pcir_fifo_flush),
|
.clk_in (clk_in),
|
.clk_in (clk_in),
|
.async_reset_data_out (pcir_fifo_flush_reg),
|
.async_reset_data_out (pcir_fifo_flush_reg),
|
.reset_in (reset_in)
|
.reset_in (reset_in)
|
) ;
|
) ;
|
|
|
always@(posedge clk_in or posedge reset_in)
|
always@(posedge clk_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
next_write_to_pciw_fifo_is_last <= #1 1'b0 ;
|
next_write_to_pciw_fifo_is_last <= #1 1'b0 ;
|
else if (next_write_to_pciw_fifo_is_last && pciw_fifo_wenable_out)
|
else if (next_write_to_pciw_fifo_is_last && pciw_fifo_wenable_out)
|
next_write_to_pciw_fifo_is_last <= #1 1'b0 ;
|
next_write_to_pciw_fifo_is_last <= #1 1'b0 ;
|
else if (pciw_fifo_wenable_out && disconect_wo_data_out)
|
else if (pciw_fifo_wenable_out && disconect_wo_data_out)
|
next_write_to_pciw_fifo_is_last <= #1 1'b1 ;
|
next_write_to_pciw_fifo_is_last <= #1 1'b1 ;
|
end
|
end
|
|
|
// signal assignments from fifo to PCI Target FSM
|
// signal assignments from fifo to PCI Target FSM
|
assign wbw_fifo_empty_out = wbw_fifo_empty_in ;
|
assign wbw_fifo_empty_out = wbw_fifo_empty_in ;
|
assign wbu_del_read_comp_pending_out = wbu_del_read_comp_pending_in ;
|
assign wbu_del_read_comp_pending_out = wbu_del_read_comp_pending_in ;
|
assign pciw_fifo_full_out = (pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in) ;
|
assign pciw_fifo_full_out = (pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in) ;
|
assign pcir_fifo_data_err_out = pcir_fifo_ctrl[`DATA_ERROR_CTRL_BIT] && !sel_conf_fifo_in ;
|
assign pcir_fifo_data_err_out = pcir_fifo_ctrl[`DATA_ERROR_CTRL_BIT] && !sel_conf_fifo_in ;
|
// signal assignments to fifo
|
// signal assignments to fifo
|
assign pcir_fifo_flush_out = pcir_fifo_flush_reg ;
|
assign pcir_fifo_flush_out = pcir_fifo_flush_reg ;
|
assign pcir_fifo_renable_out = fetch_pcir_fifo_in && !pcir_fifo_empty_in ;
|
assign pcir_fifo_renable_out = fetch_pcir_fifo_in && !pcir_fifo_empty_in ;
|
assign pciw_fifo_wenable_out = load_to_pciw_fifo_in ;
|
assign pciw_fifo_wenable_out = load_to_pciw_fifo_in ;
|
assign pciw_fifo_control_out[`ADDR_CTRL_BIT] = ~rdy_in ;
|
assign pciw_fifo_control_out[`ADDR_CTRL_BIT] = ~rdy_in ;
|
assign pciw_fifo_control_out[`BURST_BIT] = rdy_in ? ~frame_reg_in : 1'b0 ;
|
assign pciw_fifo_control_out[`BURST_BIT] = rdy_in ? ~frame_reg_in : 1'b0 ;
|
assign pciw_fifo_control_out[`DATA_ERROR_CTRL_BIT] = 1'b0 ;
|
assign pciw_fifo_control_out[`DATA_ERROR_CTRL_BIT] = 1'b0 ;
|
assign pciw_fifo_control_out[`LAST_CTRL_BIT] = rdy_in &&
|
assign pciw_fifo_control_out[`LAST_CTRL_BIT] = rdy_in &&
|
(next_write_to_pciw_fifo_is_last || last_reg_in || pciw_fifo_almost_full_in || ~addr_burst_ok || io_memory_bus_command);
|
(next_write_to_pciw_fifo_is_last || last_reg_in || pciw_fifo_almost_full_in || ~addr_burst_ok || io_memory_bus_command);
|
|
|
`ifdef HOST
|
`ifdef HOST
|
`ifdef NO_CNF_IMAGE
|
`ifdef NO_CNF_IMAGE
|
// data and address outputs assignments to PCI Target FSM
|
// data and address outputs assignments to PCI Target FSM
|
assign data_out = pcir_fifo_data ;
|
assign data_out = pcir_fifo_data ;
|
`else
|
`else
|
// data and address outputs assignments to PCI Target FSM
|
// data and address outputs assignments to PCI Target FSM
|
assign data_out = sel_conf_fifo_in ? conf_data_in : pcir_fifo_data ;
|
assign data_out = sel_conf_fifo_in ? conf_data_in : pcir_fifo_data ;
|
`endif
|
`endif
|
`else
|
`else
|
// data and address outputs assignments to PCI Target FSM
|
// data and address outputs assignments to PCI Target FSM
|
assign data_out = sel_conf_fifo_in ? conf_data_in : pcir_fifo_data ;
|
assign data_out = sel_conf_fifo_in ? conf_data_in : pcir_fifo_data ;
|
`endif
|
`endif
|
|
|
// data and address outputs assignments to read request sinchronization module
|
// data and address outputs assignments to read request sinchronization module
|
assign req_out = req_in ;
|
assign req_out = req_in ;
|
// this address is stored in delayed_sync module and is connected back as strd_addr_in
|
// this address is stored in delayed_sync module and is connected back as strd_addr_in
|
assign addr_out = norm_address[31:0] ; // correction of 2 LSBits is done in wb_master module, original address must be saved
|
assign addr_out = norm_address[31:0] ; // correction of 2 LSBits is done in wb_master module, original address must be saved
|
assign be_out = be_in ;
|
assign be_out = be_in ;
|
assign we_out = 1'b0 ;
|
assign we_out = 1'b0 ;
|
assign bc_out = norm_bc ;
|
assign bc_out = norm_bc ;
|
// burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR
|
// burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR
|
// (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00)
|
// (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00)
|
assign burst_ok_out = (norm_bc[3] && addr_burst_ok) || (norm_bc[2] && norm_prf_en && addr_burst_ok) ;
|
assign burst_ok_out = (norm_bc[3] && addr_burst_ok) || (norm_bc[2] && norm_prf_en && addr_burst_ok) ;
|
// data and address outputs assignments to PCIW_FIFO - correction of 2 LSBits
|
// data and address outputs assignments to PCIW_FIFO - correction of 2 LSBits
|
assign pciw_fifo_addr_data_out = rdy_in ? data_in : {norm_address[31:2], norm_address[1] && io_memory_bus_command,
|
assign pciw_fifo_addr_data_out = rdy_in ? data_in : {norm_address[31:2], norm_address[1] && io_memory_bus_command,
|
norm_address[0] && io_memory_bus_command} ;
|
norm_address[0] && io_memory_bus_command} ;
|
assign pciw_fifo_cbe_out = rdy_in ? be_in : norm_bc ;
|
assign pciw_fifo_cbe_out = rdy_in ? be_in : norm_bc ;
|
// data and address outputs assignments to Configuration space
|
// data and address outputs assignments to Configuration space
|
`ifdef HOST
|
`ifdef HOST
|
`ifdef NO_CNF_IMAGE
|
`ifdef NO_CNF_IMAGE
|
assign conf_data_out = 32'h0 ;
|
assign conf_data_out = 32'h0 ;
|
assign conf_addr_out = 12'h0 ;
|
assign conf_addr_out = 12'h0 ;
|
assign conf_be_out = 4'b0 ;
|
assign conf_be_out = 4'b0 ;
|
assign conf_we_out = 1'h0 ;
|
assign conf_we_out = 1'h0 ;
|
`else
|
`else
|
assign conf_data_out = data_in ;
|
assign conf_data_out = data_in ;
|
assign conf_addr_out = strd_address[11:0] ;
|
assign conf_addr_out = strd_address[11:0] ;
|
assign conf_be_out = be_in ;
|
assign conf_be_out = be_in ;
|
assign conf_we_out = load_to_conf_in ;
|
assign conf_we_out = load_to_conf_in ;
|
`endif
|
`endif
|
`else
|
`else
|
assign conf_data_out = data_in ;
|
assign conf_data_out = data_in ;
|
assign conf_addr_out = strd_address[11:0] ;
|
assign conf_addr_out = strd_address[11:0] ;
|
assign conf_be_out = be_in ;
|
assign conf_be_out = be_in ;
|
assign conf_we_out = load_to_conf_in ;
|
assign conf_we_out = load_to_conf_in ;
|
`endif
|
`endif
|
// NOT USED NOW, SONCE READ IS ASYNCHRONOUS
|
// NOT USED NOW, SONCE READ IS ASYNCHRONOUS
|
//assign conf_re_out = fetch_conf_in ;
|
//assign conf_re_out = fetch_conf_in ;
|
assign conf_re_out = 1'b0 ;
|
assign conf_re_out = 1'b0 ;
|
|
|
endmodule
|
endmodule
|
|
|
