//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// File name: pci_target32_sm.v ////
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//// File name: pci_target32_sm.v ////
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//// ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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//
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//
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//
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`define FSM_BITS 2 // number of bits needed for FSM states
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`define FSM_BITS 2 // number of bits needed for FSM states
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`include "bus_commands.v"
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`include "bus_commands.v"
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`include "constants.v"
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`include "constants.v"
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`include "timescale.v"
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module PCI_TARGET32_SM
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module PCI_TARGET32_SM
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(
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(
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// system inputs
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// system inputs
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clk_in,
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clk_in,
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reset_in,
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reset_in,
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// master inputs
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// master inputs
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pci_frame_in,
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pci_frame_in,
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pci_irdy_in,
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pci_irdy_in,
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pci_idsel_in,
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pci_idsel_in,
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pci_frame_reg_in,
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pci_frame_reg_in,
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pci_irdy_reg_in,
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pci_irdy_reg_in,
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pci_idsel_reg_in,
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pci_idsel_reg_in,
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// target response outputs
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// target response outputs
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pci_trdy_out,
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pci_trdy_out,
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pci_stop_out,
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pci_stop_out,
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pci_devsel_out,
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pci_devsel_out,
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pci_trdy_en_out,
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pci_trdy_en_out,
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pci_stop_en_out,
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pci_stop_en_out,
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pci_devsel_en_out,
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pci_devsel_en_out,
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pci_target_load_out,
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pci_target_load_out,
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// address, data, bus command, byte enable in/outs
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// address, data, bus command, byte enable in/outs
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pci_ad_reg_in,
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pci_ad_reg_in,
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pci_ad_out,
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pci_ad_out,
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pci_ad_en_out,
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pci_ad_en_out,
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pci_cbe_reg_in,
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pci_cbe_reg_in,
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bckp_trdy_en_in,
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bckp_trdy_en_in,
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bckp_devsel_in,
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bckp_devsel_in,
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bckp_trdy_in,
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bckp_trdy_in,
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bckp_stop_in,
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bckp_stop_in,
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// backend side of state machine with control signals to pci_io_mux ...
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// backend side of state machine with control signals to pci_io_mux ...
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address_out,
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address_out,
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addr_claim_in,
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addr_claim_in,
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bc_out,
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bc_out,
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bc0_out,
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bc0_out,
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data_out,
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data_out,
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data_in,
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data_in,
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be_out,
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be_out,
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req_out,
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req_out,
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rdy_out,
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rdy_out,
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addr_phase_out,
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addr_phase_out,
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bckp_trdy_out,
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bckp_trdy_out,
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last_reg_out,
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last_reg_out,
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frame_reg_out,
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frame_reg_out,
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fetch_pcir_fifo_out,
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fetch_pcir_fifo_out,
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load_medium_reg_out,
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load_medium_reg_out,
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sel_fifo_mreg_out,
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sel_fifo_mreg_out,
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sel_conf_fifo_out,
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sel_conf_fifo_out,
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fetch_conf_out,
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fetch_conf_out,
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load_to_pciw_fifo_out,
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load_to_pciw_fifo_out,
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load_to_conf_out,
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load_to_conf_out,
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same_read_in,
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same_read_in,
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norm_access_to_config_in,
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norm_access_to_config_in,
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read_completed_in,
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read_completed_in,
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read_processing_in,
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read_processing_in,
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target_abort_in,
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target_abort_in,
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disconect_wo_data_in,
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disconect_wo_data_in,
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target_abort_set_out,
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target_abort_set_out,
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pciw_fifo_full_in,
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pciw_fifo_full_in,
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pcir_fifo_data_err_in,
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pcir_fifo_data_err_in,
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wbw_fifo_empty_in,
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wbw_fifo_empty_in,
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wbu_frame_en_in
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wbu_frame_en_in
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) ;
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) ;
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/*----------------------------------------------------------------------------------------------------------------------
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/*----------------------------------------------------------------------------------------------------------------------
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Various parameters needed for state machine and other stuff
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Various parameters needed for state machine and other stuff
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----------------------------------------------------------------------------------------------------------------------*/
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----------------------------------------------------------------------------------------------------------------------*/
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parameter S_IDLE = `FSM_BITS'h0 ;
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parameter S_IDLE = `FSM_BITS'h0 ;
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parameter S_WAIT = `FSM_BITS'h1 ;
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parameter S_WAIT = `FSM_BITS'h1 ;
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parameter S_TRANSFERE = `FSM_BITS'h2 ;
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parameter S_TRANSFERE = `FSM_BITS'h2 ;
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parameter S_BACKOFF = `FSM_BITS'h3 ;
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parameter S_BACKOFF = `FSM_BITS'h3 ;
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/*==================================================================================================================
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/*==================================================================================================================
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System inputs.
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System inputs.
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==================================================================================================================*/
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==================================================================================================================*/
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// PCI side clock and reset
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// PCI side clock and reset
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input clk_in,
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input clk_in,
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reset_in ;
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reset_in ;
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/*==================================================================================================================
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/*==================================================================================================================
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PCI interface signals - bidirectional signals are divided to inputs and outputs in I/O cells instantiation
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PCI interface signals - bidirectional signals are divided to inputs and outputs in I/O cells instantiation
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module. Enables are separate signals.
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module. Enables are separate signals.
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==================================================================================================================*/
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==================================================================================================================*/
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// master inputs
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// master inputs
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input pci_frame_in,
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input pci_frame_in,
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pci_irdy_in,
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pci_irdy_in,
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pci_idsel_in ;
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pci_idsel_in ;
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input pci_frame_reg_in,
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input pci_frame_reg_in,
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pci_irdy_reg_in,
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pci_irdy_reg_in,
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pci_idsel_reg_in ;
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pci_idsel_reg_in ;
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// target response outputs
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// target response outputs
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output pci_trdy_out,
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output pci_trdy_out,
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pci_stop_out,
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pci_stop_out,
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pci_devsel_out ;
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pci_devsel_out ;
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output pci_trdy_en_out,
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output pci_trdy_en_out,
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pci_stop_en_out,
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pci_stop_en_out,
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pci_devsel_en_out ;
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pci_devsel_en_out ;
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output pci_target_load_out ;
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output pci_target_load_out ;
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// address, data, bus command, byte enable in/outs
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// address, data, bus command, byte enable in/outs
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input [31:0] pci_ad_reg_in ;
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input [31:0] pci_ad_reg_in ;
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output [31:0] pci_ad_out ;
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output [31:0] pci_ad_out ;
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output pci_ad_en_out ;
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output pci_ad_en_out ;
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input [3:0] pci_cbe_reg_in ;
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input [3:0] pci_cbe_reg_in ;
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input bckp_trdy_en_in ;
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input bckp_trdy_en_in ;
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input bckp_devsel_in ;
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input bckp_devsel_in ;
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input bckp_trdy_in ;
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input bckp_trdy_in ;
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input bckp_stop_in ;
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input bckp_stop_in ;
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/*==================================================================================================================
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/*==================================================================================================================
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Other side of PCI Target state machine
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Other side of PCI Target state machine
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==================================================================================================================*/
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==================================================================================================================*/
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// Data, byte enables, bus commands and address ports
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// Data, byte enables, bus commands and address ports
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output [31:0] address_out ; // current request address output - registered
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output [31:0] address_out ; // current request address output - registered
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input addr_claim_in ; // current request address claim input
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input addr_claim_in ; // current request address claim input
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output [3:0] bc_out ; // current request bus command output - registered
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output [3:0] bc_out ; // current request bus command output - registered
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output bc0_out ; // current cycle RW signal output
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output bc0_out ; // current cycle RW signal output
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input [31:0] data_in ; // for read operations - current dataphase data input
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input [31:0] data_in ; // for read operations - current dataphase data input
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output [31:0] data_out ; // for write operations - current request data output - registered
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output [31:0] data_out ; // for write operations - current request data output - registered
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output [3:0] be_out ; // current dataphase byte enable outputs - registered
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output [3:0] be_out ; // current dataphase byte enable outputs - registered
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// Port connection control signals from PCI FSM
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// Port connection control signals from PCI FSM
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output req_out ; // Read is requested to WB master
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output req_out ; // Read is requested to WB master
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output rdy_out ; // DATA / ADDRESS selection when read or write - registered
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output rdy_out ; // DATA / ADDRESS selection when read or write - registered
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output addr_phase_out ; // Indicates address phase and also fast-back-to-back address phase - registered
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output addr_phase_out ; // Indicates address phase and also fast-back-to-back address phase - registered
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output bckp_trdy_out ; // TRDY output (which is registered) equivalent
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output bckp_trdy_out ; // TRDY output (which is registered) equivalent
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output last_reg_out ; // Indicates last data phase - registered
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output last_reg_out ; // Indicates last data phase - registered
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output frame_reg_out ; // FRAME output signal - registered
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output frame_reg_out ; // FRAME output signal - registered
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output fetch_pcir_fifo_out ;// Read enable for PCIR_FIFO when when read is finishen on WB side
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output fetch_pcir_fifo_out ;// Read enable for PCIR_FIFO when when read is finishen on WB side
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output load_medium_reg_out ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
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output load_medium_reg_out ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
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output sel_fifo_mreg_out ; // Read data selection between PCIR_FIFO and medium register
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output sel_fifo_mreg_out ; // Read data selection between PCIR_FIFO and medium register
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output sel_conf_fifo_out ; // Read data selection between Configuration registers and "FIFO"
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output sel_conf_fifo_out ; // Read data selection between Configuration registers and "FIFO"
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output fetch_conf_out ; // Read enable for configuration space registers
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output fetch_conf_out ; // Read enable for configuration space registers
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output load_to_pciw_fifo_out ;// Write enable to PCIW_FIFO
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output load_to_pciw_fifo_out ;// Write enable to PCIW_FIFO
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output load_to_conf_out ; // Write enable to Configuration space registers
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output load_to_conf_out ; // Write enable to Configuration space registers
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/*==================================================================================================================
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/*==================================================================================================================
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Status
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Status
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==================================================================================================================*/
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==================================================================================================================*/
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input same_read_in ; // Indicates the same read request (important when read is finished on WB side)
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input same_read_in ; // Indicates the same read request (important when read is finished on WB side)
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input norm_access_to_config_in ; // Indicates the access to Configuration space with MEMORY commands
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input norm_access_to_config_in ; // Indicates the access to Configuration space with MEMORY commands
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input read_completed_in ; // Indicates that read request is completed on WB side
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input read_completed_in ; // Indicates that read request is completed on WB side
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input read_processing_in ; // Indicates that read request is processing on WB side
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input read_processing_in ; // Indicates that read request is processing on WB side
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input target_abort_in ; // Indicates target abort termination
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input target_abort_in ; // Indicates target abort termination
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input disconect_wo_data_in ; // Indicates disconnect with OR without data termination
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input disconect_wo_data_in ; // Indicates disconnect with OR without data termination
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input pciw_fifo_full_in ; // Indicates that write PCIW_FIFO is full
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input pciw_fifo_full_in ; // Indicates that write PCIW_FIFO is full
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input pcir_fifo_data_err_in ; // Indicates data error on current data read from PCIR_FIFO
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input pcir_fifo_data_err_in ; // Indicates data error on current data read from PCIR_FIFO
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input wbw_fifo_empty_in ; // Indicates that WB SLAVE UNIT has no data to be written to PCI bus
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input wbw_fifo_empty_in ; // Indicates that WB SLAVE UNIT has no data to be written to PCI bus
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input wbu_frame_en_in ; // Indicates that WB SLAVE UNIT is accessing the PCI bus (important if
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input wbu_frame_en_in ; // Indicates that WB SLAVE UNIT is accessing the PCI bus (important if
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// address on PCI bus is also claimed by decoder in this PCI TARGET UNIT
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// address on PCI bus is also claimed by decoder in this PCI TARGET UNIT
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output target_abort_set_out ; // Signal used to be set in configuration space registers
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output target_abort_set_out ; // Signal used to be set in configuration space registers
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/*==================================================================================================================
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/*==================================================================================================================
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END of input / output PORT DEFINITONS !!!
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END of input / output PORT DEFINITONS !!!
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==================================================================================================================*/
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==================================================================================================================*/
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// Delayed frame signal for determining the address phase
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// Delayed frame signal for determining the address phase
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reg previous_frame ;
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reg previous_frame ;
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// Delayed read completed signal for preparing the data from pcir fifo
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// Delayed read completed signal for preparing the data from pcir fifo
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reg read_completed_reg ;
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reg read_completed_reg ;
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// Delayed disconnect with/without data for stop loading data to PCIW_FIFO
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// Delayed disconnect with/without data for stop loading data to PCIW_FIFO
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reg disconect_wo_data_reg ;
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reg disconect_wo_data_reg ;
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// Delayed frame signal for determining the address phase!
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// Delayed frame signal for determining the address phase!
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always@(posedge clk_in or posedge reset_in)
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always@(posedge clk_in or posedge reset_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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begin
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begin
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previous_frame <= 1'b1 ;
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previous_frame <= 1'b1 ;
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read_completed_reg <= 1'b0 ;
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read_completed_reg <= 1'b0 ;
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disconect_wo_data_reg <= 1'b0 ;
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disconect_wo_data_reg <= 1'b0 ;
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end
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end
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else
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else
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begin
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begin
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previous_frame <= pci_frame_reg_in ;
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previous_frame <= pci_frame_reg_in ;
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read_completed_reg <= read_completed_in ;
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read_completed_reg <= read_completed_in ;
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disconect_wo_data_reg <= disconect_wo_data_in ;
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disconect_wo_data_reg <= disconect_wo_data_in ;
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end
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end
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end
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end
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// Address phase is when previous frame was 1 and this frame is 0 and frame isn't generated from pci master (in WBU)
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// Address phase is when previous frame was 1 and this frame is 0 and frame isn't generated from pci master (in WBU)
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wire addr_phase = (previous_frame && ~pci_frame_reg_in && ~wbu_frame_en_in) ;
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wire addr_phase = (previous_frame && ~pci_frame_reg_in && ~wbu_frame_en_in) ;
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// Wire tells when there is configuration (read or write) command with IDSEL signal active
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// Wire tells when there is configuration (read or write) command with IDSEL signal active
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wire config_access = ((pci_idsel_reg_in && pci_cbe_reg_in[3]) && (~pci_cbe_reg_in[2] && pci_cbe_reg_in[1])) ;
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wire config_access = ((pci_idsel_reg_in && pci_cbe_reg_in[3]) && (~pci_cbe_reg_in[2] && pci_cbe_reg_in[1])) ;
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// Signal for loadin data to medium register from pcir fifo when read completed from WB side!
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// Signal for loadin data to medium register from pcir fifo when read completed from WB side!
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wire prepare_rd_fifo_data = (read_completed_in && ~read_completed_reg) ;
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wire prepare_rd_fifo_data = (read_completed_in && ~read_completed_reg) ;
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// Write and read progresses are used for determining next state
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// Write and read progresses are used for determining next state
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wire write_progress = (
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wire write_progress = (
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(norm_access_to_config_in) || (read_completed_in && ~pciw_fifo_full_in) ||
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(norm_access_to_config_in) || (read_completed_in && ~pciw_fifo_full_in) ||
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(~read_processing_in && ~pciw_fifo_full_in)
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(~read_processing_in && ~pciw_fifo_full_in)
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) ;
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) ;
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wire read_progress = ((~read_completed_in && norm_access_to_config_in) || (read_completed_in && wbw_fifo_empty_in)) ;
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wire read_progress = ((~read_completed_in && norm_access_to_config_in) || (read_completed_in && wbw_fifo_empty_in)) ;
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// Write allowed to PCIW_FIFO
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// Write allowed to PCIW_FIFO
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wire write_to_fifo = ((read_completed_in && ~pciw_fifo_full_in) || (~read_processing_in && ~pciw_fifo_full_in)) ;
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wire write_to_fifo = ((read_completed_in && ~pciw_fifo_full_in) || (~read_processing_in && ~pciw_fifo_full_in)) ;
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// Read allowed from PCIR_FIFO
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// Read allowed from PCIR_FIFO
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wire read_from_fifo = (read_completed_in && wbw_fifo_empty_in) ;
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wire read_from_fifo = (read_completed_in && wbw_fifo_empty_in) ;
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// Read request is allowed to be proceed regarding the WB side
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// Read request is allowed to be proceed regarding the WB side
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wire read_request = (~read_completed_in && ~read_processing_in && ~norm_access_to_config_in) ;
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wire read_request = (~read_completed_in && ~read_processing_in && ~norm_access_to_config_in) ;
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// Critically calculated signals are latched in this clock period (address phase) to be used in the next clock period
|
// Critically calculated signals are latched in this clock period (address phase) to be used in the next clock period
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reg rw_cbe0 ;
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reg rw_cbe0 ;
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reg wr_progress ;
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reg wr_progress ;
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reg rd_progress ;
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reg rd_progress ;
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reg rd_from_fifo ;
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reg rd_from_fifo ;
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reg rd_request ;
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reg rd_request ;
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reg wr_to_fifo ;
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reg wr_to_fifo ;
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reg norm_access_to_conf_reg ;
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reg norm_access_to_conf_reg ;
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reg same_read_reg ;
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reg same_read_reg ;
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reg cnf_progress ;
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reg cnf_progress ;
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reg addr_claim_reg ;
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reg addr_claim_reg ;
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always@(posedge clk_in or posedge reset_in)
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always@(posedge clk_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
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if (reset_in)
|
begin
|
begin
|
rw_cbe0 <= 1'b0 ;
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rw_cbe0 <= 1'b0 ;
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wr_progress <= 1'b0 ;
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wr_progress <= 1'b0 ;
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rd_progress <= 1'b0 ;
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rd_progress <= 1'b0 ;
|
rd_from_fifo <= 1'b0 ;
|
rd_from_fifo <= 1'b0 ;
|
rd_request <= 1'b0 ;
|
rd_request <= 1'b0 ;
|
wr_to_fifo <= 1'b0 ;
|
wr_to_fifo <= 1'b0 ;
|
norm_access_to_conf_reg <= 1'b0 ;
|
norm_access_to_conf_reg <= 1'b0 ;
|
same_read_reg <= 1'b0 ;
|
same_read_reg <= 1'b0 ;
|
cnf_progress <= 1'b0 ;
|
cnf_progress <= 1'b0 ;
|
addr_claim_reg <= 1'b0 ;
|
addr_claim_reg <= 1'b0 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (addr_phase)
|
if (addr_phase)
|
begin
|
begin
|
rw_cbe0 <= pci_cbe_reg_in[0] ;
|
rw_cbe0 <= pci_cbe_reg_in[0] ;
|
wr_progress <= write_progress ;
|
wr_progress <= write_progress ;
|
rd_progress <= read_progress ;
|
rd_progress <= read_progress ;
|
rd_from_fifo <= read_from_fifo ;
|
rd_from_fifo <= read_from_fifo ;
|
rd_request <= read_request ;
|
rd_request <= read_request ;
|
wr_to_fifo <= write_to_fifo ;
|
wr_to_fifo <= write_to_fifo ;
|
norm_access_to_conf_reg <= norm_access_to_config_in ;
|
norm_access_to_conf_reg <= norm_access_to_config_in ;
|
same_read_reg <= same_read_in ;
|
same_read_reg <= same_read_in ;
|
cnf_progress <= config_access ;
|
cnf_progress <= config_access ;
|
addr_claim_reg <= addr_claim_in ;
|
addr_claim_reg <= addr_claim_in ;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
// Signal used in S_WAIT state to determin next state
|
// Signal used in S_WAIT state to determin next state
|
wire s_wait_progress = (
|
wire s_wait_progress = (
|
(~cnf_progress && rw_cbe0 && wr_progress && ~target_abort_in) ||
|
(~cnf_progress && rw_cbe0 && wr_progress && ~target_abort_in) ||
|
(~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && ~target_abort_in) ||
|
(~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && ~target_abort_in) ||
|
(~cnf_progress && ~rw_cbe0 && ~same_read_reg && norm_access_to_conf_reg && ~target_abort_in) ||
|
(~cnf_progress && ~rw_cbe0 && ~same_read_reg && norm_access_to_conf_reg && ~target_abort_in) ||
|
(cnf_progress && ~target_abort_in)
|
(cnf_progress && ~target_abort_in)
|
) ;
|
) ;
|
|
|
// Signal used in S_TRANSFERE state to determin next state
|
// Signal used in S_TRANSFERE state to determin next state
|
wire s_tran_progress = (
|
wire s_tran_progress = (
|
(rw_cbe0 && ~disconect_wo_data_in) ||
|
(rw_cbe0 && ~disconect_wo_data_in) ||
|
(~rw_cbe0 && ~disconect_wo_data_in && ~target_abort_in && ~pcir_fifo_data_err_in)
|
(~rw_cbe0 && ~disconect_wo_data_in && ~target_abort_in && ~pcir_fifo_data_err_in)
|
) ;
|
) ;
|
|
|
// Clock enable for PCI state machine driven directly from critical inputs - FRAME and IRDY
|
// Clock enable for PCI state machine driven directly from critical inputs - FRAME and IRDY
|
wire pcit_sm_clk_en ;
|
wire pcit_sm_clk_en ;
|
// FSM states signals indicating the current state
|
// FSM states signals indicating the current state
|
reg state_idle ;
|
reg state_idle ;
|
reg state_wait ;
|
reg state_wait ;
|
reg state_transfere ;
|
reg state_transfere ;
|
reg state_backoff ;
|
reg state_backoff ;
|
reg state_default ;
|
reg state_default ;
|
// Clock enable module used for preserving the architecture because of minimum delay for critical inputs
|
// Clock enable module used for preserving the architecture because of minimum delay for critical inputs
|
PCI_TARGET32_CLK_EN pci_target_clock_en
|
PCI_TARGET32_CLK_EN pci_target_clock_en
|
(
|
(
|
.addr_phase (addr_phase),
|
.addr_phase (addr_phase),
|
.config_access (config_access),
|
.config_access (config_access),
|
.addr_claim_in (addr_claim_in),
|
.addr_claim_in (addr_claim_in),
|
.disconect_wo_data_in (disconect_wo_data_in),
|
.disconect_wo_data_in (disconect_wo_data_in),
|
.pcir_fifo_data_err_in (pcir_fifo_data_err_in),
|
.pcir_fifo_data_err_in (pcir_fifo_data_err_in),
|
.rw_cbe0 (rw_cbe0),
|
.rw_cbe0 (rw_cbe0),
|
.pci_frame_in (pci_frame_in),
|
.pci_frame_in (pci_frame_in),
|
.pci_irdy_in (pci_irdy_in),
|
.pci_irdy_in (pci_irdy_in),
|
.state_wait (state_wait),
|
.state_wait (state_wait),
|
.state_transfere (state_transfere),
|
.state_transfere (state_transfere),
|
.state_backoff (state_backoff),
|
.state_backoff (state_backoff),
|
.state_default (state_default),
|
.state_default (state_default),
|
.clk_enable (pcit_sm_clk_en)
|
.clk_enable (pcit_sm_clk_en)
|
);
|
);
|
|
|
reg [(`FSM_BITS - 1):0] c_state ; //current state register
|
reg [(`FSM_BITS - 1):0] c_state ; //current state register
|
reg [(`FSM_BITS - 1):0] n_state ; //next state input to current state register
|
reg [(`FSM_BITS - 1):0] n_state ; //next state input to current state register
|
|
|
// state machine register control
|
// state machine register control
|
always@(posedge clk_in or posedge reset_in)
|
always@(posedge clk_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in) // reset state machine to S_IDLE state
|
if (reset_in) // reset state machine to S_IDLE state
|
c_state <= #`FF_DELAY S_IDLE ;
|
c_state <= #`FF_DELAY S_IDLE ;
|
else
|
else
|
if (pcit_sm_clk_en) // if conditions are true, then FSM goes to next state!
|
if (pcit_sm_clk_en) // if conditions are true, then FSM goes to next state!
|
c_state <= #`FF_DELAY n_state ;
|
c_state <= #`FF_DELAY n_state ;
|
end
|
end
|
|
|
// state machine logic
|
// state machine logic
|
always@(c_state or
|
always@(c_state or
|
s_wait_progress or
|
s_wait_progress or
|
s_tran_progress
|
s_tran_progress
|
)
|
)
|
begin
|
begin
|
case (c_state)
|
case (c_state)
|
S_IDLE :
|
S_IDLE :
|
begin
|
begin
|
state_idle <= 1'b1 ;
|
state_idle <= 1'b1 ;
|
state_wait <= 1'b0 ;
|
state_wait <= 1'b0 ;
|
state_transfere <= 1'b0 ;
|
state_transfere <= 1'b0 ;
|
state_backoff <= 1'b0 ;
|
state_backoff <= 1'b0 ;
|
state_default <= 1'b0 ;
|
state_default <= 1'b0 ;
|
n_state <= S_WAIT ;
|
n_state <= S_WAIT ;
|
end
|
end
|
S_WAIT :
|
S_WAIT :
|
begin
|
begin
|
state_idle <= 1'b0 ;
|
state_idle <= 1'b0 ;
|
state_wait <= 1'b1 ;
|
state_wait <= 1'b1 ;
|
state_transfere <= 1'b0 ;
|
state_transfere <= 1'b0 ;
|
state_backoff <= 1'b0 ;
|
state_backoff <= 1'b0 ;
|
state_default <= 1'b0 ;
|
state_default <= 1'b0 ;
|
if (s_wait_progress)
|
if (s_wait_progress)
|
n_state <= S_TRANSFERE ;
|
n_state <= S_TRANSFERE ;
|
else
|
else
|
n_state <= S_BACKOFF ;
|
n_state <= S_BACKOFF ;
|
end
|
end
|
S_TRANSFERE :
|
S_TRANSFERE :
|
begin
|
begin
|
state_idle <= 1'b0 ;
|
state_idle <= 1'b0 ;
|
state_wait <= 1'b0 ;
|
state_wait <= 1'b0 ;
|
state_transfere <= 1'b1 ;
|
state_transfere <= 1'b1 ;
|
state_backoff <= 1'b0 ;
|
state_backoff <= 1'b0 ;
|
state_default <= 1'b0 ;
|
state_default <= 1'b0 ;
|
if (s_tran_progress)
|
if (s_tran_progress)
|
n_state <= S_IDLE ;
|
n_state <= S_IDLE ;
|
else
|
else
|
n_state <= S_BACKOFF ;
|
n_state <= S_BACKOFF ;
|
end
|
end
|
S_BACKOFF :
|
S_BACKOFF :
|
begin
|
begin
|
state_idle <= 1'b0 ;
|
state_idle <= 1'b0 ;
|
state_wait <= 1'b0 ;
|
state_wait <= 1'b0 ;
|
state_transfere <= 1'b0 ;
|
state_transfere <= 1'b0 ;
|
state_backoff <= 1'b1 ;
|
state_backoff <= 1'b1 ;
|
state_default <= 1'b0 ;
|
state_default <= 1'b0 ;
|
n_state <= S_IDLE ;
|
n_state <= S_IDLE ;
|
end
|
end
|
default :
|
default :
|
begin
|
begin
|
state_idle <= 1'b0 ;
|
state_idle <= 1'b0 ;
|
state_wait <= 1'b0 ;
|
state_wait <= 1'b0 ;
|
state_transfere <= 1'b0 ;
|
state_transfere <= 1'b0 ;
|
state_backoff <= 1'b0 ;
|
state_backoff <= 1'b0 ;
|
state_default <= 1'b1 ;
|
state_default <= 1'b1 ;
|
n_state <= S_IDLE ;
|
n_state <= S_IDLE ;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
// if not retry and not target abort
|
// if not retry and not target abort
|
// NO CRITICAL SIGNALS
|
// NO CRITICAL SIGNALS
|
wire trdy_w = (
|
wire trdy_w = (
|
(state_wait && ~cnf_progress && rw_cbe0 && wr_progress && ~target_abort_in) ||
|
(state_wait && ~cnf_progress && rw_cbe0 && wr_progress && ~target_abort_in) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && ~target_abort_in) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && ~target_abort_in) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && ~same_read_reg && norm_access_to_conf_reg && ~target_abort_in) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && ~same_read_reg && norm_access_to_conf_reg && ~target_abort_in) ||
|
(state_wait && cnf_progress && ~target_abort_in)
|
(state_wait && cnf_progress && ~target_abort_in)
|
) ;
|
) ;
|
// if not disconnect without data and not target abort (only during reads)
|
// if not disconnect without data and not target abort (only during reads)
|
// MUST BE ANDED WITH CRITICAL ~FRAME
|
// MUST BE ANDED WITH CRITICAL ~FRAME
|
wire trdy_w_frm = (
|
wire trdy_w_frm = (
|
(state_transfere && ~disconect_wo_data_in) ||
|
(state_transfere && ~disconect_wo_data_in) ||
|
(state_transfere && disconect_wo_data_in && pci_irdy_reg_in) ||
|
(state_transfere && disconect_wo_data_in && pci_irdy_reg_in) ||
|
(state_transfere && ~rw_cbe0 && ~pcir_fifo_data_err_in)
|
(state_transfere && ~rw_cbe0 && ~pcir_fifo_data_err_in)
|
) ;
|
) ;
|
// if not disconnect without data and not target abort (only during reads)
|
// if not disconnect without data and not target abort (only during reads)
|
// MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
|
// MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
|
wire trdy_w_frm_irdy = (
|
wire trdy_w_frm_irdy = (
|
(state_transfere && disconect_wo_data_in) ||
|
(state_transfere && disconect_wo_data_in) ||
|
(state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in) ||
|
(state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in) ||
|
(state_backoff && ~bckp_trdy_in)
|
(state_backoff && ~bckp_trdy_in)
|
) ;
|
) ;
|
// TRDY critical module used for preserving the architecture because of minimum delay for critical inputs
|
// TRDY critical module used for preserving the architecture because of minimum delay for critical inputs
|
PCI_TARGET32_TRDY_CRIT pci_target_trdy_critical
|
PCI_TARGET32_TRDY_CRIT pci_target_trdy_critical
|
(
|
(
|
.trdy_w (trdy_w),
|
.trdy_w (trdy_w),
|
.trdy_w_frm (trdy_w_frm),
|
.trdy_w_frm (trdy_w_frm),
|
.trdy_w_frm_irdy (trdy_w_frm_irdy),
|
.trdy_w_frm_irdy (trdy_w_frm_irdy),
|
.pci_frame_in (pci_frame_in),
|
.pci_frame_in (pci_frame_in),
|
.pci_irdy_in (pci_irdy_in),
|
.pci_irdy_in (pci_irdy_in),
|
.pci_trdy_out (pci_trdy_out)
|
.pci_trdy_out (pci_trdy_out)
|
);
|
);
|
|
|
// if target abort or retry
|
// if target abort or retry
|
// NO CRITICAL SIGNALS
|
// NO CRITICAL SIGNALS
|
wire stop_w = (
|
wire stop_w = (
|
(state_wait && target_abort_in) ||
|
(state_wait && target_abort_in) ||
|
(state_wait && ~cnf_progress && rw_cbe0 && ~wr_progress) ||
|
(state_wait && ~cnf_progress && rw_cbe0 && ~wr_progress) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && ~rd_progress) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && ~rd_progress) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && ~same_read_reg && ~norm_access_to_conf_reg)
|
(state_wait && ~cnf_progress && ~rw_cbe0 && ~same_read_reg && ~norm_access_to_conf_reg)
|
) ;
|
) ;
|
// if asserted, wait for deactivating the frame
|
// if asserted, wait for deactivating the frame
|
// MUST BE ANDED WITH CRITICAL ~FRAME
|
// MUST BE ANDED WITH CRITICAL ~FRAME
|
wire stop_w_frm = (
|
wire stop_w_frm = (
|
(state_backoff && ~bckp_stop_in)
|
(state_backoff && ~bckp_stop_in)
|
) ;
|
) ;
|
// if target abort or if disconnect without data (after data transfere)
|
// if target abort or if disconnect without data (after data transfere)
|
// MUST BE ANDED WITH CRITICAL ~FRAME AND ~IRDY
|
// MUST BE ANDED WITH CRITICAL ~FRAME AND ~IRDY
|
wire stop_w_frm_irdy = (
|
wire stop_w_frm_irdy = (
|
(state_transfere && disconect_wo_data_in) ||
|
(state_transfere && disconect_wo_data_in) ||
|
(state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in)
|
(state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in)
|
) ;
|
) ;
|
// STOP critical module used for preserving the architecture because of minimum delay for critical inputs
|
// STOP critical module used for preserving the architecture because of minimum delay for critical inputs
|
PCI_TARGET32_STOP_CRIT pci_target_stop_critical
|
PCI_TARGET32_STOP_CRIT pci_target_stop_critical
|
(
|
(
|
.stop_w (stop_w),
|
.stop_w (stop_w),
|
.stop_w_frm (stop_w_frm),
|
.stop_w_frm (stop_w_frm),
|
.stop_w_frm_irdy (stop_w_frm_irdy),
|
.stop_w_frm_irdy (stop_w_frm_irdy),
|
.pci_frame_in (pci_frame_in),
|
.pci_frame_in (pci_frame_in),
|
.pci_irdy_in (pci_irdy_in),
|
.pci_irdy_in (pci_irdy_in),
|
.pci_stop_out (pci_stop_out)
|
.pci_stop_out (pci_stop_out)
|
);
|
);
|
|
|
// if OK to respond and not target abort
|
// if OK to respond and not target abort
|
// NO CRITICAL SIGNALS
|
// NO CRITICAL SIGNALS
|
wire devs_w = (
|
wire devs_w = (
|
(addr_phase && config_access) ||
|
(addr_phase && config_access) ||
|
(addr_phase && ~config_access && addr_claim_in) ||
|
(addr_phase && ~config_access && addr_claim_in) ||
|
(state_wait && ~target_abort_in)
|
(state_wait && ~target_abort_in)
|
) ;
|
) ;
|
// if not target abort (only during reads) or if asserted, wait for deactivating the frame
|
// if not target abort (only during reads) or if asserted, wait for deactivating the frame
|
// MUST BE ANDED WITH CRITICAL ~FRAME
|
// MUST BE ANDED WITH CRITICAL ~FRAME
|
wire devs_w_frm = (
|
wire devs_w_frm = (
|
(state_transfere && rw_cbe0) ||
|
(state_transfere && rw_cbe0) ||
|
(state_transfere && ~rw_cbe0 && ~pcir_fifo_data_err_in) ||
|
(state_transfere && ~rw_cbe0 && ~pcir_fifo_data_err_in) ||
|
(state_backoff && ~bckp_devsel_in)
|
(state_backoff && ~bckp_devsel_in)
|
) ;
|
) ;
|
// if not target abort (only during reads)
|
// if not target abort (only during reads)
|
// MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
|
// MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
|
wire devs_w_frm_irdy = (
|
wire devs_w_frm_irdy = (
|
(state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in)
|
(state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in)
|
) ;
|
) ;
|
// DEVSEL critical module used for preserving the architecture because of minimum delay for critical inputs
|
// DEVSEL critical module used for preserving the architecture because of minimum delay for critical inputs
|
PCI_TARGET32_DEVS_CRIT pci_target_devsel_critical
|
PCI_TARGET32_DEVS_CRIT pci_target_devsel_critical
|
(
|
(
|
.devs_w (devs_w),
|
.devs_w (devs_w),
|
.devs_w_frm (devs_w_frm),
|
.devs_w_frm (devs_w_frm),
|
.devs_w_frm_irdy (devs_w_frm_irdy),
|
.devs_w_frm_irdy (devs_w_frm_irdy),
|
.pci_frame_in (pci_frame_in),
|
.pci_frame_in (pci_frame_in),
|
.pci_irdy_in (pci_irdy_in),
|
.pci_irdy_in (pci_irdy_in),
|
.pci_devsel_out (pci_devsel_out)
|
.pci_devsel_out (pci_devsel_out)
|
);
|
);
|
|
|
// if address is claimed when read
|
// if address is claimed when read
|
// NO CRITICAL SIGNALS
|
// NO CRITICAL SIGNALS
|
wire ad_en_w = (
|
wire ad_en_w = (
|
(addr_phase && config_access && ~pci_cbe_reg_in[0]) ||
|
(addr_phase && config_access && ~pci_cbe_reg_in[0]) ||
|
(addr_phase && ~config_access && addr_claim_in && ~pci_cbe_reg_in[0]) ||
|
(addr_phase && ~config_access && addr_claim_in && ~pci_cbe_reg_in[0]) ||
|
(state_wait && ~rw_cbe0)
|
(state_wait && ~rw_cbe0)
|
) ;
|
) ;
|
// if read
|
// if read
|
// MUST BE ANDED WITH CRITICAL ~FRAME
|
// MUST BE ANDED WITH CRITICAL ~FRAME
|
wire ad_en_w_frm = (
|
wire ad_en_w_frm = (
|
(state_transfere && ~rw_cbe0) ||
|
(state_transfere && ~rw_cbe0) ||
|
(state_backoff && ~rw_cbe0)
|
(state_backoff && ~rw_cbe0)
|
) ;
|
) ;
|
// AD enable module used for preserving the architecture because of minimum delay for critical inputs
|
// AD enable module used for preserving the architecture because of minimum delay for critical inputs
|
PCI_TARGET32_AD_EN_CRIT pci_target_ad_enable_critical
|
PCI_TARGET32_AD_EN_CRIT pci_target_ad_enable_critical
|
(
|
(
|
.ad_en_w (ad_en_w),
|
.ad_en_w (ad_en_w),
|
.ad_en_w_frm (ad_en_w_frm),
|
.ad_en_w_frm (ad_en_w_frm),
|
.pci_frame_in (pci_frame_in),
|
.pci_frame_in (pci_frame_in),
|
.pci_ad_en_out (pci_ad_en_out)
|
.pci_ad_en_out (pci_ad_en_out)
|
);
|
);
|
|
|
wire fast_back_to_back = (addr_phase && ~pci_irdy_reg_in) ;
|
wire fast_back_to_back = (addr_phase && ~pci_irdy_reg_in) ;
|
|
|
// if cycle will progress or will not be stopped
|
// if cycle will progress or will not be stopped
|
// NO CRITICAL SIGNALS
|
// NO CRITICAL SIGNALS
|
wire ctrl_en_w = (
|
wire ctrl_en_w = (
|
(~wbu_frame_en_in && fast_back_to_back) ||
|
(~wbu_frame_en_in && fast_back_to_back) ||
|
(addr_phase && config_access) ||
|
(addr_phase && config_access) ||
|
(addr_phase && ~config_access && addr_claim_in) ||
|
(addr_phase && ~config_access && addr_claim_in) ||
|
(state_wait) ||
|
(state_wait) ||
|
(state_transfere && ~pci_frame_reg_in) ||
|
(state_transfere && ~pci_frame_reg_in) ||
|
(state_backoff && ~pci_frame_reg_in)
|
(state_backoff && ~pci_frame_reg_in)
|
) ;
|
) ;
|
// if cycle is progressing
|
// if cycle is progressing
|
// MUST BE ANDED WITH CRITICAL ~IRDY
|
// MUST BE ANDED WITH CRITICAL ~IRDY
|
wire ctrl_en_w_irdy = (
|
wire ctrl_en_w_irdy = (
|
(state_transfere) ||
|
(state_transfere) ||
|
(state_backoff)
|
(state_backoff)
|
) ;
|
) ;
|
// Clock enable module used for preserving the architecture because of minimum delay for critical inputs
|
// Clock enable module used for preserving the architecture because of minimum delay for critical inputs
|
PCI_TARGET32_CTRL_EN_CRIT pci_target_control_enable_critical
|
PCI_TARGET32_CTRL_EN_CRIT pci_target_control_enable_critical
|
(
|
(
|
.ctrl_en_w (ctrl_en_w),
|
.ctrl_en_w (ctrl_en_w),
|
.ctrl_en_w_irdy (ctrl_en_w_irdy),
|
.ctrl_en_w_irdy (ctrl_en_w_irdy),
|
.pci_irdy_in (pci_irdy_in),
|
.pci_irdy_in (pci_irdy_in),
|
.pci_trdy_en_out (pci_trdy_en_out),
|
.pci_trdy_en_out (pci_trdy_en_out),
|
.pci_stop_en_out (pci_stop_en_out),
|
.pci_stop_en_out (pci_stop_en_out),
|
.pci_devsel_en_out (pci_devsel_en_out)
|
.pci_devsel_en_out (pci_devsel_en_out)
|
);
|
);
|
|
|
// target ready output signal delayed for one clock used in conjunction with irdy_reg to select which
|
// target ready output signal delayed for one clock used in conjunction with irdy_reg to select which
|
// data are registered in io mux module - from fifo or medoum register
|
// data are registered in io mux module - from fifo or medoum register
|
reg bckp_trdy_reg ;
|
reg bckp_trdy_reg ;
|
// delayed indicators for states transfere and backoff
|
// delayed indicators for states transfere and backoff
|
reg state_transfere_reg ;
|
reg state_transfere_reg ;
|
reg state_backoff_reg ;
|
reg state_backoff_reg ;
|
always@(posedge clk_in or posedge reset_in)
|
always@(posedge clk_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
begin
|
begin
|
bckp_trdy_reg <= 1'b1 ;
|
bckp_trdy_reg <= 1'b1 ;
|
state_transfere_reg <= 1'b0 ;
|
state_transfere_reg <= 1'b0 ;
|
state_backoff_reg <= 1'b0 ;
|
state_backoff_reg <= 1'b0 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
bckp_trdy_reg <= bckp_trdy_in ;
|
bckp_trdy_reg <= bckp_trdy_in ;
|
state_transfere_reg <= state_transfere ;
|
state_transfere_reg <= state_transfere ;
|
state_backoff_reg <= state_backoff ;
|
state_backoff_reg <= state_backoff ;
|
end
|
end
|
end
|
end
|
|
|
// Read control signals assignments
|
// Read control signals assignments
|
assign
|
assign
|
fetch_pcir_fifo_out = (
|
fetch_pcir_fifo_out = (
|
(prepare_rd_fifo_data) ||
|
(prepare_rd_fifo_data) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo && ~target_abort_in) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo && ~target_abort_in) ||
|
(bckp_trdy_en_in && ~bckp_trdy_reg && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo && ~pci_irdy_reg_in)
|
(bckp_trdy_en_in && ~bckp_trdy_reg && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo && ~pci_irdy_reg_in)
|
) ;
|
) ;
|
|
|
// NO CRITICAL SIGNALS
|
// NO CRITICAL SIGNALS
|
wire tar_load_out_w = (state_wait) ;
|
wire tar_load_out_w = (state_wait) ;
|
// MUST BE ANDED WITH CRITICAL ~IRDY
|
// MUST BE ANDED WITH CRITICAL ~IRDY
|
wire tar_load_out_w_irdy = (bckp_trdy_en_in && ~rw_cbe0) ;
|
wire tar_load_out_w_irdy = (bckp_trdy_en_in && ~rw_cbe0) ;
|
// NO CRITICAL SIGNALS
|
// NO CRITICAL SIGNALS
|
wire load_med_reg_w = (
|
wire load_med_reg_w = (
|
(prepare_rd_fifo_data) ||
|
(prepare_rd_fifo_data) ||
|
(state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo && ~target_abort_in)
|
(state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo && ~target_abort_in)
|
) ;
|
) ;
|
// MUST BE ANDED WITH CRITICAL ~IRDY
|
// MUST BE ANDED WITH CRITICAL ~IRDY
|
wire load_med_reg_w_irdy =
|
wire load_med_reg_w_irdy =
|
(bckp_trdy_en_in && ~bckp_trdy_in && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo) ;
|
(bckp_trdy_en_in && ~bckp_trdy_in && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo) ;
|
// Clock enable module used for preserving the architecture because of minimum delay for critical inputs
|
// Clock enable module used for preserving the architecture because of minimum delay for critical inputs
|
PCI_TARGET32_LOAD_CRIT pci_target_load_critical
|
PCI_TARGET32_LOAD_CRIT pci_target_load_critical
|
(
|
(
|
.tar_load_out_w (tar_load_out_w),
|
.tar_load_out_w (tar_load_out_w),
|
.tar_load_out_w_irdy (tar_load_out_w_irdy),
|
.tar_load_out_w_irdy (tar_load_out_w_irdy),
|
.load_med_reg_w (load_med_reg_w),
|
.load_med_reg_w (load_med_reg_w),
|
.load_med_reg_w_irdy (load_med_reg_w_irdy),
|
.load_med_reg_w_irdy (load_med_reg_w_irdy),
|
.pci_irdy_in (pci_irdy_in),
|
.pci_irdy_in (pci_irdy_in),
|
.pci_target_load_out (pci_target_load_out),
|
.pci_target_load_out (pci_target_load_out),
|
.load_medium_reg_out (load_medium_reg_out)
|
.load_medium_reg_out (load_medium_reg_out)
|
);
|
);
|
|
|
assign sel_fifo_mreg_out = (~pci_irdy_reg_in && ~bckp_trdy_reg) ;
|
assign sel_fifo_mreg_out = (~pci_irdy_reg_in && ~bckp_trdy_reg) ;
|
|
|
assign sel_conf_fifo_out = (cnf_progress || norm_access_to_conf_reg) ;
|
assign sel_conf_fifo_out = (cnf_progress || norm_access_to_conf_reg) ;
|
|
|
assign fetch_conf_out = ((cnf_progress || norm_access_to_conf_reg) && ~rw_cbe0 && ~bckp_devsel_in) ;
|
assign fetch_conf_out = ((cnf_progress || norm_access_to_conf_reg) && ~rw_cbe0 && ~bckp_devsel_in) ;
|
|
|
// Write control signals assignments
|
// Write control signals assignments
|
assign
|
assign
|
load_to_pciw_fifo_out = (
|
load_to_pciw_fifo_out = (
|
(state_wait && (~cnf_progress && ~norm_access_to_conf_reg) && rw_cbe0 && wr_to_fifo && ~target_abort_in) ||
|
(state_wait && (~cnf_progress && ~norm_access_to_conf_reg) && rw_cbe0 && wr_to_fifo && ~target_abort_in) ||
|
(state_transfere_reg && ~state_backoff && rw_cbe0 && wr_to_fifo && ~disconect_wo_data_reg && ~pci_irdy_reg_in && ~bckp_trdy_reg && (~cnf_progress && ~norm_access_to_conf_reg)) ||
|
(state_transfere_reg && ~state_backoff && rw_cbe0 && wr_to_fifo && ~disconect_wo_data_reg && ~pci_irdy_reg_in && ~bckp_trdy_reg && (~cnf_progress && ~norm_access_to_conf_reg)) ||
|
((state_backoff || state_backoff_reg) && rw_cbe0 && wr_to_fifo && ~pci_irdy_reg_in && ~bckp_trdy_reg && (~cnf_progress && ~norm_access_to_conf_reg))
|
((state_backoff || state_backoff_reg) && rw_cbe0 && wr_to_fifo && ~pci_irdy_reg_in && ~bckp_trdy_reg && (~cnf_progress && ~norm_access_to_conf_reg))
|
) ;
|
) ;
|
|
|
assign load_to_conf_out = (
|
assign load_to_conf_out = (
|
(state_transfere_reg && cnf_progress && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg) ||
|
(state_transfere_reg && cnf_progress && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg) ||
|
(state_transfere_reg && norm_access_to_conf_reg && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg)
|
(state_transfere_reg && norm_access_to_conf_reg && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg)
|
) ;
|
) ;
|
|
|
// General control sigal assignments
|
// General control sigal assignments
|
assign addr_phase_out = addr_phase ;
|
assign addr_phase_out = addr_phase ;
|
assign last_reg_out = (pci_frame_reg_in && ~pci_irdy_reg_in) ;
|
assign last_reg_out = (pci_frame_reg_in && ~pci_irdy_reg_in) ;
|
assign frame_reg_out = pci_frame_reg_in ;
|
assign frame_reg_out = pci_frame_reg_in ;
|
assign bckp_trdy_out = bckp_trdy_in ;
|
assign bckp_trdy_out = bckp_trdy_in ;
|
assign target_abort_set_out = (bckp_devsel_in && bckp_trdy_in && ~bckp_stop_in) ;
|
assign target_abort_set_out = (bckp_devsel_in && bckp_trdy_in && ~bckp_stop_in) ;
|
// request signal for delayed sinc. module
|
// request signal for delayed sinc. module
|
assign req_out = (state_wait && ~cnf_progress && ~norm_access_to_conf_reg && ~rw_cbe0 && rd_request && ~target_abort_in) ;
|
assign req_out = (state_wait && ~cnf_progress && ~norm_access_to_conf_reg && ~rw_cbe0 && rd_request && ~target_abort_in) ;
|
// ready tells when address or data are written into fifo - RDY ? DATA : ADDRESS
|
// ready tells when address or data are written into fifo - RDY ? DATA : ADDRESS
|
assign rdy_out = ~bckp_trdy_reg ;
|
assign rdy_out = ~bckp_trdy_reg ;
|
|
|
// data and address outputs assignments!
|
// data and address outputs assignments!
|
assign pci_ad_out = data_in ;
|
assign pci_ad_out = data_in ;
|
|
|
assign data_out = pci_ad_reg_in ;
|
assign data_out = pci_ad_reg_in ;
|
assign be_out = pci_cbe_reg_in ;
|
assign be_out = pci_cbe_reg_in ;
|
assign address_out = pci_ad_reg_in ;
|
assign address_out = pci_ad_reg_in ;
|
assign bc_out = pci_cbe_reg_in ;
|
assign bc_out = pci_cbe_reg_in ;
|
assign bc0_out = rw_cbe0 ;
|
assign bc0_out = rw_cbe0 ;
|
|
|
|
|
|
|
