//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// File name "sync_module.v" ////
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//// File name "sync_module.v" ////
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//// ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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//
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//
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module SYNC_MODULE
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module SYNC_MODULE
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(
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(
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set_clk_in,
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set_clk_in,
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delete_clk_in,
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delete_clk_in,
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reset_in,
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reset_in,
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delete_set_out,
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delete_set_out,
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block_set_out,
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block_set_out,
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delete_in
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delete_in
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);
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);
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// system inputs from two clock domains
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// system inputs from two clock domains
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input set_clk_in;
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input set_clk_in;
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input delete_clk_in;
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input delete_clk_in;
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input reset_in;
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input reset_in;
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// control outputs
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// control outputs
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output delete_set_out;
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output delete_set_out;
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output block_set_out;
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output block_set_out;
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// control input
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// control input
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input delete_in;
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input delete_in;
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// internal signals
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// internal signals
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reg del_bit;
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reg del_bit;
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wire meta_del_bit;
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wire meta_del_bit;
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reg sync_del_bit;
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reg sync_del_bit;
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reg delayed_del_bit;
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reg delayed_del_bit;
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wire meta_bckp_bit;
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wire meta_bckp_bit;
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reg sync_bckp_bit;
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reg sync_bckp_bit;
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reg delayed_bckp_bit;
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reg delayed_bckp_bit;
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// DELETE_IN input FF - when set must be active, until it is sinchronously cleared
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// DELETE_IN input FF - when set must be active, until it is sinchronously cleared
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always@(posedge delete_clk_in or posedge reset_in)
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always@(posedge delete_clk_in or posedge reset_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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del_bit <= 1'b0;
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del_bit <= 1'b0;
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else
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else
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begin
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begin
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if (!delayed_bckp_bit && sync_bckp_bit)
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if (!delayed_bckp_bit && sync_bckp_bit)
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del_bit <= 1'b0;
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del_bit <= 1'b0;
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else if (delete_in)
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else if (delete_in)
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del_bit <= 1'b1;
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del_bit <= 1'b1;
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end
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end
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end
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end
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assign block_set_out = del_bit;
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assign block_set_out = del_bit;
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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synchronizer_flop delete_sync
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synchronizer_flop delete_sync
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(
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(
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.data_in (del_bit),
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.data_in (del_bit),
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.clk_out (set_clk_in),
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.clk_out (set_clk_in),
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.sync_data_out (meta_del_bit),
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.sync_data_out (meta_del_bit),
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.async_reset (reset_in)
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.async_reset (reset_in)
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) ;
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) ;
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// Final synchronization of del_bit signal to the set clock domain
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// Final synchronization of del_bit signal to the set clock domain
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always@(posedge set_clk_in or posedge reset_in)
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always@(posedge set_clk_in or posedge reset_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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sync_del_bit <= 1'b0;
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sync_del_bit <= 1'b0;
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else
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else
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sync_del_bit <= meta_del_bit;
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sync_del_bit <= meta_del_bit;
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end
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end
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// Delayed sync_del_bit signal for one clock period pulse generation
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// Delayed sync_del_bit signal for one clock period pulse generation
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always@(posedge set_clk_in or posedge reset_in)
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always@(posedge set_clk_in or posedge reset_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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delayed_del_bit <= 1'b0;
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delayed_del_bit <= 1'b0;
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else
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else
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delayed_del_bit <= sync_del_bit;
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delayed_del_bit <= sync_del_bit;
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end
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end
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assign delete_set_out = !delayed_del_bit && sync_del_bit;
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assign delete_set_out = !delayed_del_bit && sync_del_bit;
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
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synchronizer_flop clear_delete_sync
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synchronizer_flop clear_delete_sync
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(
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(
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.data_in (sync_del_bit),
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.data_in (sync_del_bit),
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.clk_out (delete_clk_in),
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.clk_out (delete_clk_in),
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.sync_data_out (meta_bckp_bit),
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.sync_data_out (meta_bckp_bit),
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.async_reset (reset_in)
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.async_reset (reset_in)
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) ;
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) ;
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// Final synchronization of sync_del_bit signal to the delete clock domain
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// Final synchronization of sync_del_bit signal to the delete clock domain
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always@(posedge delete_clk_in or posedge reset_in)
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always@(posedge delete_clk_in or posedge reset_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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sync_bckp_bit <= 1'b0;
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sync_bckp_bit <= 1'b0;
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else
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else
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sync_bckp_bit <= meta_bckp_bit;
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sync_bckp_bit <= meta_bckp_bit;
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end
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end
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// Delayed sync_bckp_bit signal for one clock period pulse generation
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// Delayed sync_bckp_bit signal for one clock period pulse generation
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always@(posedge delete_clk_in or posedge reset_in)
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always@(posedge delete_clk_in or posedge reset_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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delayed_bckp_bit <= 1'b0;
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delayed_bckp_bit <= 1'b0;
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else
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else
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delayed_bckp_bit <= sync_bckp_bit;
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delayed_bckp_bit <= sync_bckp_bit;
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end
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end
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