//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// File name "wbw_wbr_fifos.v" ////
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//// File name "wbw_wbr_fifos.v" ////
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//// ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README ////
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//// All additional information is avaliable in the README ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
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//// later version. ////
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//// ////
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//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
|
//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2002/10/17 22:49:22 tadejm
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// Revision 1.8 2002/10/17 22:49:22 tadejm
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// Changed BIST signals for RAMs.
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// Changed BIST signals for RAMs.
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//
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//
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// Revision 1.7 2002/10/11 10:09:01 mihad
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// Revision 1.7 2002/10/11 10:09:01 mihad
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// Added additional testcase and changed rst name in BIST to trst
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// Added additional testcase and changed rst name in BIST to trst
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//
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//
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// Revision 1.6 2002/10/08 17:17:06 mihad
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// Revision 1.6 2002/10/08 17:17:06 mihad
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// Added BIST signals for RAMs.
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// Added BIST signals for RAMs.
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//
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//
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// Revision 1.5 2002/09/30 16:03:04 mihad
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// Revision 1.5 2002/09/30 16:03:04 mihad
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// Added meta flop module for easier meta stable FF identification during synthesis
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// Added meta flop module for easier meta stable FF identification during synthesis
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//
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//
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// Revision 1.4 2002/09/25 15:53:52 mihad
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// Revision 1.4 2002/09/25 15:53:52 mihad
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// Removed all logic from asynchronous reset network
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// Removed all logic from asynchronous reset network
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//
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//
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// Revision 1.3 2002/02/01 15:25:14 mihad
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// Revision 1.3 2002/02/01 15:25:14 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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//
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// Revision 1.2 2001/10/05 08:20:12 mihad
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// Revision 1.2 2001/10/05 08:20:12 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
|
// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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|
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`include "pci_constants.v"
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`include "pci_constants.v"
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|
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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|
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module WBW_WBR_FIFOS
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module WBW_WBR_FIFOS
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(
|
(
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wb_clock_in,
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wb_clock_in,
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pci_clock_in,
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pci_clock_in,
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reset_in,
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reset_in,
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wbw_wenable_in,
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wbw_wenable_in,
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wbw_addr_data_in,
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wbw_addr_data_in,
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wbw_cbe_in,
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wbw_cbe_in,
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wbw_control_in,
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wbw_control_in,
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wbw_renable_in,
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wbw_renable_in,
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wbw_addr_data_out,
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wbw_addr_data_out,
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wbw_cbe_out,
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wbw_cbe_out,
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wbw_control_out,
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wbw_control_out,
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// wbw_flush_in, write fifo flush not used
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// wbw_flush_in, write fifo flush not used
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wbw_almost_full_out,
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wbw_almost_full_out,
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wbw_full_out,
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wbw_full_out,
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wbw_empty_out,
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wbw_empty_out,
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wbw_transaction_ready_out,
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wbw_transaction_ready_out,
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wbr_wenable_in,
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wbr_wenable_in,
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wbr_data_in,
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wbr_data_in,
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wbr_be_in,
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wbr_be_in,
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wbr_control_in,
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wbr_control_in,
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wbr_renable_in,
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wbr_renable_in,
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wbr_data_out,
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wbr_data_out,
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wbr_be_out,
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wbr_be_out,
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wbr_control_out,
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wbr_control_out,
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wbr_flush_in,
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wbr_flush_in,
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wbr_empty_out
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wbr_empty_out
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|
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`ifdef PCI_BIST
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`ifdef PCI_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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scanb_rst, // bist scan reset
|
scanb_rst, // bist scan reset
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scanb_clk, // bist scan clock
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scanb_clk, // bist scan clock
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scanb_si, // bist scan serial in
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scanb_si, // bist scan serial in
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scanb_so, // bist scan serial out
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scanb_so, // bist scan serial out
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scanb_en // bist scan shift enable
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scanb_en // bist scan shift enable
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`endif
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`endif
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) ;
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) ;
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|
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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System inputs:
|
System inputs:
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wb_clock_in - WISHBONE bus clock
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wb_clock_in - WISHBONE bus clock
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pci_clock_in - PCI bus clock
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pci_clock_in - PCI bus clock
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reset_in - reset from control logic
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reset_in - reset from control logic
|
-------------------------------------------------------------------------------------------------------------*/
|
-------------------------------------------------------------------------------------------------------------*/
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input wb_clock_in, pci_clock_in, reset_in ;
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input wb_clock_in, pci_clock_in, reset_in ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
WISHBONE WRITE FIFO interface signals prefixed with wbw_ - FIFO is used for posted writes initiated by
|
WISHBONE WRITE FIFO interface signals prefixed with wbw_ - FIFO is used for posted writes initiated by
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WISHBONE master, traveling through FIFO and are completed on PCI by PCI master interface
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WISHBONE master, traveling through FIFO and are completed on PCI by PCI master interface
|
|
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write enable signal:
|
write enable signal:
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wbw_wenable_in = write enable input for WBW_FIFO - driven by WISHBONE slave interface
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wbw_wenable_in = write enable input for WBW_FIFO - driven by WISHBONE slave interface
|
|
|
data input signals:
|
data input signals:
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wbw_addr_data_in = data input - data from WISHBONE bus - first entry of transaction is address others are data entries
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wbw_addr_data_in = data input - data from WISHBONE bus - first entry of transaction is address others are data entries
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wbw_cbe_in = bus command/byte enable(~SEL[3:0]) input - first entry of transaction is bus command, other are byte enables
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wbw_cbe_in = bus command/byte enable(~SEL[3:0]) input - first entry of transaction is bus command, other are byte enables
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wbw_control_in = control input - encoded control bus input
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wbw_control_in = control input - encoded control bus input
|
|
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read enable signal:
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read enable signal:
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wbw_renable_in = read enable input driven by PCI master interface
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wbw_renable_in = read enable input driven by PCI master interface
|
|
|
data output signals:
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data output signals:
|
wbw_addr_data_out = data output - data from WISHBONE bus - first entry of transaction is address, others are data entries
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wbw_addr_data_out = data output - data from WISHBONE bus - first entry of transaction is address, others are data entries
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wbw_cbe_out = bus command/byte enable output - first entry of transaction is bus command, others are byte enables
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wbw_cbe_out = bus command/byte enable output - first entry of transaction is bus command, others are byte enables
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wbw_control_out = control input - encoded control bus input
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wbw_control_out = control input - encoded control bus input
|
|
|
status signals - monitored by various resources in the core
|
status signals - monitored by various resources in the core
|
wbw_flush_in = flush signal input for WBW_FIFO - when asserted, fifo is flushed(emptied)
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wbw_flush_in = flush signal input for WBW_FIFO - when asserted, fifo is flushed(emptied)
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wbw_almost_full_out = almost full output from WBW_FIFO
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wbw_almost_full_out = almost full output from WBW_FIFO
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wbw_full_out = full output from WBW_FIFO
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wbw_full_out = full output from WBW_FIFO
|
wbw_empty_out = empty output from WBW_FIFO
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wbw_empty_out = empty output from WBW_FIFO
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wbw_transaction_ready_out = output indicating that one complete transaction is waiting in WBW_FIFO
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wbw_transaction_ready_out = output indicating that one complete transaction is waiting in WBW_FIFO
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
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// input control and data
|
// input control and data
|
input wbw_wenable_in ;
|
input wbw_wenable_in ;
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input [31:0] wbw_addr_data_in ;
|
input [31:0] wbw_addr_data_in ;
|
input [3:0] wbw_cbe_in ;
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input [3:0] wbw_cbe_in ;
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input [3:0] wbw_control_in ;
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input [3:0] wbw_control_in ;
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|
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// output control and data
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// output control and data
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input wbw_renable_in ;
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input wbw_renable_in ;
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output [31:0] wbw_addr_data_out ;
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output [31:0] wbw_addr_data_out ;
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output [3:0] wbw_cbe_out ;
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output [3:0] wbw_cbe_out ;
|
output [3:0] wbw_control_out ;
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output [3:0] wbw_control_out ;
|
|
|
// flush input
|
// flush input
|
// input wbw_flush_in ; // not used
|
// input wbw_flush_in ; // not used
|
|
|
// status outputs
|
// status outputs
|
output wbw_almost_full_out ;
|
output wbw_almost_full_out ;
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output wbw_full_out ;
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output wbw_full_out ;
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output wbw_empty_out ;
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output wbw_empty_out ;
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output wbw_transaction_ready_out ;
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output wbw_transaction_ready_out ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
WISHBONE READ FIFO interface signals prefixed with wbr_ - FIFO is used for holding delayed read completions
|
WISHBONE READ FIFO interface signals prefixed with wbr_ - FIFO is used for holding delayed read completions
|
initiated by master on WISHBONE bus and completed on PCI bus,
|
initiated by master on WISHBONE bus and completed on PCI bus,
|
|
|
write enable signal:
|
write enable signal:
|
wbr_wenable_in = write enable input for WBR_FIFO - driven by PCI master interface
|
wbr_wenable_in = write enable input for WBR_FIFO - driven by PCI master interface
|
|
|
data input signals:
|
data input signals:
|
wbr_data_in = data input - data from PCI bus - there is no address entry here, since address is stored in separate register
|
wbr_data_in = data input - data from PCI bus - there is no address entry here, since address is stored in separate register
|
wbr_be_in = byte enable(~BE#[3:0]) input - byte enables - same through one transaction
|
wbr_be_in = byte enable(~BE#[3:0]) input - byte enables - same through one transaction
|
wbr_control_in = control input - encoded control bus input
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wbr_control_in = control input - encoded control bus input
|
|
|
read enable signal:
|
read enable signal:
|
wbr_renable_in = read enable input driven by WISHBONE slave interface
|
wbr_renable_in = read enable input driven by WISHBONE slave interface
|
|
|
data output signals:
|
data output signals:
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wbr_data_out = data output - data from PCI bus
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wbr_data_out = data output - data from PCI bus
|
wbr_be_out = byte enable output(~#BE)
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wbr_be_out = byte enable output(~#BE)
|
wbr_control_out = control output - encoded control bus output
|
wbr_control_out = control output - encoded control bus output
|
|
|
status signals - monitored by various resources in the core
|
status signals - monitored by various resources in the core
|
wbr_flush_in = flush signal input for WBR_FIFO - when asserted, fifo is flushed(emptied)
|
wbr_flush_in = flush signal input for WBR_FIFO - when asserted, fifo is flushed(emptied)
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wbr full_out = full output from WBR_FIFO
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wbr full_out = full output from WBR_FIFO
|
wbr_empty_out = empty output from WBR_FIFO
|
wbr_empty_out = empty output from WBR_FIFO
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
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// input control and data
|
// input control and data
|
input wbr_wenable_in ;
|
input wbr_wenable_in ;
|
input [31:0] wbr_data_in ;
|
input [31:0] wbr_data_in ;
|
input [3:0] wbr_be_in ;
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input [3:0] wbr_be_in ;
|
input [3:0] wbr_control_in ;
|
input [3:0] wbr_control_in ;
|
|
|
// output control and data
|
// output control and data
|
input wbr_renable_in ;
|
input wbr_renable_in ;
|
output [31:0] wbr_data_out ;
|
output [31:0] wbr_data_out ;
|
output [3:0] wbr_be_out ;
|
output [3:0] wbr_be_out ;
|
output [3:0] wbr_control_out ;
|
output [3:0] wbr_control_out ;
|
|
|
// flush input
|
// flush input
|
input wbr_flush_in ;
|
input wbr_flush_in ;
|
|
|
output wbr_empty_out ;
|
output wbr_empty_out ;
|
|
|
`ifdef PCI_BIST
|
`ifdef PCI_BIST
|
/*-----------------------------------------------------
|
/*-----------------------------------------------------
|
BIST debug chain port signals
|
BIST debug chain port signals
|
-----------------------------------------------------*/
|
-----------------------------------------------------*/
|
input scanb_rst; // bist scan reset
|
input scanb_rst; // bist scan reset
|
input scanb_clk; // bist scan clock
|
input scanb_clk; // bist scan clock
|
input scanb_si; // bist scan serial in
|
input scanb_si; // bist scan serial in
|
output scanb_so; // bist scan serial out
|
output scanb_so; // bist scan serial out
|
input scanb_en; // bist scan shift enable
|
input scanb_en; // bist scan shift enable
|
`endif
|
`endif
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
FIFO depth parameters:
|
FIFO depth parameters:
|
WBW_DEPTH = defines WBW_FIFO depth
|
WBW_DEPTH = defines WBW_FIFO depth
|
WBR_DEPTH = defines WBR_FIFO depth
|
WBR_DEPTH = defines WBR_FIFO depth
|
WBW_ADDR_LENGTH = defines WBW_FIFO's location address length = log2(WBW_DEPTH)
|
WBW_ADDR_LENGTH = defines WBW_FIFO's location address length = log2(WBW_DEPTH)
|
WBR_ADDR_LENGTH = defines WBR_FIFO's location address length = log2(WBR_DEPTH)
|
WBR_ADDR_LENGTH = defines WBR_FIFO's location address length = log2(WBR_DEPTH)
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
parameter WBW_DEPTH = `WBW_DEPTH ;
|
parameter WBW_DEPTH = `WBW_DEPTH ;
|
parameter WBW_ADDR_LENGTH = `WBW_ADDR_LENGTH ;
|
parameter WBW_ADDR_LENGTH = `WBW_ADDR_LENGTH ;
|
parameter WBR_DEPTH = `WBR_DEPTH ;
|
parameter WBR_DEPTH = `WBR_DEPTH ;
|
parameter WBR_ADDR_LENGTH = `WBR_ADDR_LENGTH ;
|
parameter WBR_ADDR_LENGTH = `WBR_ADDR_LENGTH ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
wbw_wallow = WBW_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
|
wbw_wallow = WBW_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
|
wbw_rallow = WBW_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
|
wbw_rallow = WBW_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire wbw_wallow ;
|
wire wbw_wallow ;
|
wire wbw_rallow ;
|
wire wbw_rallow ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
wbr_wallow = WBR_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
|
wbr_wallow = WBR_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
|
wbr_rallow = WBR_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
|
wbr_rallow = WBR_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire wbr_wallow ;
|
wire wbr_wallow ;
|
wire wbr_rallow ;
|
wire wbr_rallow ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
wires for address port conections from WBW_FIFO control logic to RAM blocks used for WBW_FIFO
|
wires for address port conections from WBW_FIFO control logic to RAM blocks used for WBW_FIFO
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire [(WBW_ADDR_LENGTH - 1):0] wbw_raddr ;
|
wire [(WBW_ADDR_LENGTH - 1):0] wbw_raddr ;
|
wire [(WBW_ADDR_LENGTH - 1):0] wbw_waddr ;
|
wire [(WBW_ADDR_LENGTH - 1):0] wbw_waddr ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
wires for address port conections from WBR_FIFO control logic to RAM blocks used for WBR_FIFO
|
wires for address port conections from WBR_FIFO control logic to RAM blocks used for WBR_FIFO
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire [(WBR_ADDR_LENGTH - 1):0] wbr_raddr ;
|
wire [(WBR_ADDR_LENGTH - 1):0] wbr_raddr ;
|
wire [(WBR_ADDR_LENGTH - 1):0] wbr_waddr ;
|
wire [(WBR_ADDR_LENGTH - 1):0] wbr_waddr ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
WBW_FIFO transaction counters: used to count incoming transactions and outgoing transactions. When number of
|
WBW_FIFO transaction counters: used to count incoming transactions and outgoing transactions. When number of
|
input transactions is equal to number of output transactions, it means that there isn't any complete transaction
|
input transactions is equal to number of output transactions, it means that there isn't any complete transaction
|
currently present in the FIFO.
|
currently present in the FIFO.
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
reg [(WBW_ADDR_LENGTH - 2):0] wbw_inTransactionCount ;
|
reg [(WBW_ADDR_LENGTH - 2):0] wbw_inTransactionCount ;
|
reg [(WBW_ADDR_LENGTH - 2):0] wbw_outTransactionCount ;
|
reg [(WBW_ADDR_LENGTH - 2):0] wbw_outTransactionCount ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
wires monitoring control bus. When control bus on a write transaction has a value of `LAST, it means that
|
wires monitoring control bus. When control bus on a write transaction has a value of `LAST, it means that
|
complete transaction is in the FIFO. When control bus on a read transaction has a value of `LAST,
|
complete transaction is in the FIFO. When control bus on a read transaction has a value of `LAST,
|
it means that there was one complete transaction taken out of FIFO.
|
it means that there was one complete transaction taken out of FIFO.
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire wbw_last_in = wbw_control_in[`LAST_CTRL_BIT] ;
|
wire wbw_last_in = wbw_control_in[`LAST_CTRL_BIT] ;
|
wire wbw_last_out = wbw_control_out[`LAST_CTRL_BIT] ;
|
wire wbw_last_out = wbw_control_out[`LAST_CTRL_BIT] ;
|
|
|
wire wbw_empty ;
|
wire wbw_empty ;
|
wire wbr_empty ;
|
wire wbr_empty ;
|
|
|
assign wbw_empty_out = wbw_empty ;
|
assign wbw_empty_out = wbw_empty ;
|
assign wbr_empty_out = wbr_empty ;
|
assign wbr_empty_out = wbr_empty ;
|
|
|
// clear wires for fifos
|
// clear wires for fifos
|
wire wbw_clear = reset_in /*|| wbw_flush_in*/ ; // WBW_FIFO clear flush not used
|
wire wbw_clear = reset_in /*|| wbw_flush_in*/ ; // WBW_FIFO clear flush not used
|
wire wbr_clear = reset_in /*|| wbr_flush_in*/ ; // WBR_FIFO clear - flush changed from asynchronous to synchronous
|
wire wbr_clear = reset_in /*|| wbr_flush_in*/ ; // WBR_FIFO clear - flush changed from asynchronous to synchronous
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Definitions of wires for connecting RAM instances
|
Definitions of wires for connecting RAM instances
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire [39:0] dpram_portA_output ;
|
wire [39:0] dpram_portA_output ;
|
wire [39:0] dpram_portB_output ;
|
wire [39:0] dpram_portB_output ;
|
|
|
wire [39:0] dpram_portA_input = {wbw_control_in, wbw_cbe_in, wbw_addr_data_in} ;
|
wire [39:0] dpram_portA_input = {wbw_control_in, wbw_cbe_in, wbw_addr_data_in} ;
|
wire [39:0] dpram_portB_input = {wbr_control_in, wbr_be_in, wbr_data_in} ;
|
wire [39:0] dpram_portB_input = {wbr_control_in, wbr_be_in, wbr_data_in} ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Fifo output assignments - each ram port provides data for different fifo
|
Fifo output assignments - each ram port provides data for different fifo
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
assign wbw_control_out = dpram_portB_output[39:36] ;
|
assign wbw_control_out = dpram_portB_output[39:36] ;
|
assign wbr_control_out = dpram_portA_output[39:36] ;
|
assign wbr_control_out = dpram_portA_output[39:36] ;
|
|
|
assign wbw_cbe_out = dpram_portB_output[35:32] ;
|
assign wbw_cbe_out = dpram_portB_output[35:32] ;
|
assign wbr_be_out = dpram_portA_output[35:32] ;
|
assign wbr_be_out = dpram_portA_output[35:32] ;
|
|
|
assign wbw_addr_data_out = dpram_portB_output[31:0] ;
|
assign wbw_addr_data_out = dpram_portB_output[31:0] ;
|
assign wbr_data_out = dpram_portA_output[31:0] ;
|
assign wbr_data_out = dpram_portA_output[31:0] ;
|
|
|
`ifdef WB_RAM_DONT_SHARE
|
`ifdef WB_RAM_DONT_SHARE
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Piece of code in this ifdef section is used in applications which can provide enough RAM instances to
|
Piece of code in this ifdef section is used in applications which can provide enough RAM instances to
|
accomodate four fifos - each occupying its own instance of ram. Ports are connected in such a way,
|
accomodate four fifos - each occupying its own instance of ram. Ports are connected in such a way,
|
that instances of RAMs can be changed from two port to dual port ( async read/write port ). In that case,
|
that instances of RAMs can be changed from two port to dual port ( async read/write port ). In that case,
|
write port is always port a and read port is port b.
|
write port is always port a and read port is port b.
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Pad redundant address lines with zeros. This may seem stupid, but it comes in perfect for FPGA impl.
|
Pad redundant address lines with zeros. This may seem stupid, but it comes in perfect for FPGA impl.
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
/*
|
/*
|
wire [(`WBW_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WBW_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
|
wire [(`WBW_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WBW_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
|
wire [(`WBR_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WBR_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b0}} ;
|
wire [(`WBR_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WBR_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b0}} ;
|
*/
|
*/
|
|
|
// compose complete port addresses
|
// compose complete port addresses
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_waddr = wbw_waddr ;
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_waddr = wbw_waddr ;
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_raddr = wbw_raddr ;
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_raddr = wbw_raddr ;
|
|
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_waddr = wbr_waddr ;
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_waddr = wbr_waddr ;
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_raddr = wbr_raddr ;
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_raddr = wbr_raddr ;
|
|
|
wire wbw_read_enable = 1'b1 ;
|
wire wbw_read_enable = 1'b1 ;
|
wire wbr_read_enable = 1'b1 ;
|
wire wbr_read_enable = 1'b1 ;
|
|
|
`ifdef PCI_BIST
|
`ifdef PCI_BIST
|
wire scanb_so_internal ; // wires for connection of debug ports on two rams
|
wire scanb_so_internal ; // wires for connection of debug ports on two rams
|
wire scanb_si_internal = scanb_so_internal ;
|
wire scanb_si_internal = scanb_so_internal ;
|
`endif
|
`endif
|
|
|
// instantiate and connect two generic rams - one for wishbone write fifo and one for wishbone read fifo
|
// instantiate and connect two generic rams - one for wishbone write fifo and one for wishbone read fifo
|
WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbw_fifo_storage
|
WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbw_fifo_storage
|
(
|
(
|
// Generic synchronous two-port RAM interface
|
// Generic synchronous two-port RAM interface
|
.clk_a(wb_clock_in),
|
.clk_a(wb_clock_in),
|
.rst_a(reset_in),
|
.rst_a(reset_in),
|
.ce_a(1'b1),
|
.ce_a(1'b1),
|
.we_a(wbw_wallow),
|
.we_a(wbw_wallow),
|
.oe_a(1'b1),
|
.oe_a(1'b1),
|
.addr_a(wbw_whole_waddr),
|
.addr_a(wbw_whole_waddr),
|
.di_a(dpram_portA_input),
|
.di_a(dpram_portA_input),
|
.do_a(),
|
.do_a(),
|
|
|
.clk_b(pci_clock_in),
|
.clk_b(pci_clock_in),
|
.rst_b(reset_in),
|
.rst_b(reset_in),
|
.ce_b(wbw_read_enable),
|
.ce_b(wbw_read_enable),
|
.we_b(1'b0),
|
.we_b(1'b0),
|
.oe_b(1'b1),
|
.oe_b(1'b1),
|
.addr_b(wbw_whole_raddr),
|
.addr_b(wbw_whole_raddr),
|
.di_b(40'h00_0000_0000),
|
.di_b(40'h00_0000_0000),
|
.do_b(dpram_portB_output)
|
.do_b(dpram_portB_output)
|
|
|
`ifdef PCI_BIST
|
`ifdef PCI_BIST
|
,
|
,
|
.scanb_rst (scanb_rst),
|
.scanb_rst (scanb_rst),
|
.scanb_clk (scanb_clk),
|
.scanb_clk (scanb_clk),
|
.scanb_si (scanb_si),
|
.scanb_si (scanb_si),
|
.scanb_so (scanb_so_internal),
|
.scanb_so (scanb_so_internal),
|
.scanb_en (scanb_en)
|
.scanb_en (scanb_en)
|
`endif
|
`endif
|
);
|
);
|
|
|
WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbr_fifo_storage
|
WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbr_fifo_storage
|
(
|
(
|
// Generic synchronous two-port RAM interface
|
// Generic synchronous two-port RAM interface
|
.clk_a(pci_clock_in),
|
.clk_a(pci_clock_in),
|
.rst_a(reset_in),
|
.rst_a(reset_in),
|
.ce_a(1'b1),
|
.ce_a(1'b1),
|
.we_a(wbr_wallow),
|
.we_a(wbr_wallow),
|
.oe_a(1'b1),
|
.oe_a(1'b1),
|
.addr_a(wbr_whole_waddr),
|
.addr_a(wbr_whole_waddr),
|
.di_a(dpram_portB_input),
|
.di_a(dpram_portB_input),
|
.do_a(),
|
.do_a(),
|
|
|
.clk_b(wb_clock_in),
|
.clk_b(wb_clock_in),
|
.rst_b(reset_in),
|
.rst_b(reset_in),
|
.ce_b(wbr_read_enable),
|
.ce_b(wbr_read_enable),
|
.we_b(1'b0),
|
.we_b(1'b0),
|
.oe_b(1'b1),
|
.oe_b(1'b1),
|
.addr_b(wbr_whole_raddr),
|
.addr_b(wbr_whole_raddr),
|
.di_b(40'h00_0000_0000),
|
.di_b(40'h00_0000_0000),
|
.do_b(dpram_portA_output)
|
.do_b(dpram_portA_output)
|
|
|
`ifdef PCI_BIST
|
`ifdef PCI_BIST
|
,
|
,
|
.scanb_rst (scanb_rst),
|
.scanb_rst (scanb_rst),
|
.scanb_clk (scanb_clk),
|
.scanb_clk (scanb_clk),
|
.scanb_si (scanb_si_internal),
|
.scanb_si (scanb_si_internal),
|
.scanb_so (scanb_so),
|
.scanb_so (scanb_so),
|
.scanb_en (scanb_en)
|
.scanb_en (scanb_en)
|
`endif
|
`endif
|
);
|
);
|
|
|
`else // RAM blocks sharing between two fifos
|
`else // RAM blocks sharing between two fifos
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Code section under this ifdef is used for implementation where RAM instances are too expensive. In this
|
Code section under this ifdef is used for implementation where RAM instances are too expensive. In this
|
case one RAM instance is used for both - WISHBONE read and WISHBONE write fifo.
|
case one RAM instance is used for both - WISHBONE read and WISHBONE write fifo.
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Address prefix definition - since both FIFOs reside in same RAM instance, storage is separated by MSB
|
Address prefix definition - since both FIFOs reside in same RAM instance, storage is separated by MSB
|
addresses. WISHBONE write fifo addresses are padded with zeros on the MSB side ( at least one address line
|
addresses. WISHBONE write fifo addresses are padded with zeros on the MSB side ( at least one address line
|
must be used for this ), WISHBONE read fifo addresses are padded with ones on the right ( at least one ).
|
must be used for this ), WISHBONE read fifo addresses are padded with ones on the right ( at least one ).
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b1}} ;
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b1}} ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Port A address generation for RAM instance. RAM instance must be full two port RAM - read and write capability
|
Port A address generation for RAM instance. RAM instance must be full two port RAM - read and write capability
|
on both sides.
|
on both sides.
|
Port A is clocked by WISHBONE clock, DIA is input for wbw_fifo, DOA is output for wbr_fifo.
|
Port A is clocked by WISHBONE clock, DIA is input for wbw_fifo, DOA is output for wbr_fifo.
|
Address is multiplexed so operation can be switched between fifos. Default is a read on port.
|
Address is multiplexed so operation can be switched between fifos. Default is a read on port.
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portA_addr = wbw_wallow ? {wbw_addr_prefix, wbw_waddr} : {wbr_addr_prefix, wbr_raddr} ;
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portA_addr = wbw_wallow ? {wbw_addr_prefix, wbw_waddr} : {wbr_addr_prefix, wbr_raddr} ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Port B is clocked by PCI clock, DIB is input for wbr_fifo, DOB is output for wbw_fifo.
|
Port B is clocked by PCI clock, DIB is input for wbr_fifo, DOB is output for wbw_fifo.
|
Address is multiplexed so operation can be switched between fifos. Default is a read on port.
|
Address is multiplexed so operation can be switched between fifos. Default is a read on port.
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portB_addr = wbr_wallow ? {wbr_addr_prefix, wbr_waddr} : {wbw_addr_prefix, wbw_raddr} ;
|
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portB_addr = wbr_wallow ? {wbr_addr_prefix, wbr_waddr} : {wbw_addr_prefix, wbw_raddr} ;
|
|
|
wire portA_enable = 1'b1 ;
|
wire portA_enable = 1'b1 ;
|
|
|
wire portB_enable = 1'b1 ;
|
wire portB_enable = 1'b1 ;
|
|
|
// instantiate RAM for these two fifos
|
// instantiate RAM for these two fifos
|
WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbu_fifo_storage
|
WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbu_fifo_storage
|
(
|
(
|
// Generic synchronous two-port RAM interface
|
// Generic synchronous two-port RAM interface
|
.clk_a(wb_clock_in),
|
.clk_a(wb_clock_in),
|
.rst_a(reset_in),
|
.rst_a(reset_in),
|
.ce_a(portA_enable),
|
.ce_a(portA_enable),
|
.we_a(wbw_wallow),
|
.we_a(wbw_wallow),
|
.oe_a(1'b1),
|
.oe_a(1'b1),
|
.addr_a(portA_addr),
|
.addr_a(portA_addr),
|
.di_a(dpram_portA_input),
|
.di_a(dpram_portA_input),
|
.do_a(dpram_portA_output),
|
.do_a(dpram_portA_output),
|
.clk_b(pci_clock_in),
|
.clk_b(pci_clock_in),
|
.rst_b(reset_in),
|
.rst_b(reset_in),
|
.ce_b(portB_enable),
|
.ce_b(portB_enable),
|
.we_b(wbr_wallow),
|
.we_b(wbr_wallow),
|
.oe_b(1'b1),
|
.oe_b(1'b1),
|
.addr_b(portB_addr),
|
.addr_b(portB_addr),
|
.di_b(dpram_portB_input),
|
.di_b(dpram_portB_input),
|
.do_b(dpram_portB_output)
|
.do_b(dpram_portB_output)
|
|
|
`ifdef PCI_BIST
|
`ifdef PCI_BIST
|
,
|
,
|
.scanb_rst (scanb_rst),
|
.scanb_rst (scanb_rst),
|
.scanb_clk (scanb_clk),
|
.scanb_clk (scanb_clk),
|
.scanb_si (scanb_si),
|
.scanb_si (scanb_si),
|
.scanb_so (scanb_so),
|
.scanb_so (scanb_so),
|
.scanb_en (scanb_en)
|
.scanb_en (scanb_en)
|
`endif
|
`endif
|
);
|
);
|
|
|
`endif
|
`endif
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Instantiation of two control logic modules - one for WBW_FIFO and one for WBR_FIFO
|
Instantiation of two control logic modules - one for WBW_FIFO and one for WBR_FIFO
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
WBW_FIFO_CONTROL #(WBW_ADDR_LENGTH) wbw_fifo_ctrl
|
WBW_FIFO_CONTROL #(WBW_ADDR_LENGTH) wbw_fifo_ctrl
|
(
|
(
|
.rclock_in(pci_clock_in),
|
.rclock_in(pci_clock_in),
|
.wclock_in(wb_clock_in),
|
.wclock_in(wb_clock_in),
|
.renable_in(wbw_renable_in),
|
.renable_in(wbw_renable_in),
|
.wenable_in(wbw_wenable_in),
|
.wenable_in(wbw_wenable_in),
|
.reset_in(reset_in),
|
.reset_in(reset_in),
|
// .flush_in(wbw_flush_in),
|
// .flush_in(wbw_flush_in),
|
.almost_full_out(wbw_almost_full_out),
|
.almost_full_out(wbw_almost_full_out),
|
.full_out(wbw_full_out),
|
.full_out(wbw_full_out),
|
.empty_out(wbw_empty),
|
.empty_out(wbw_empty),
|
.waddr_out(wbw_waddr),
|
.waddr_out(wbw_waddr),
|
.raddr_out(wbw_raddr),
|
.raddr_out(wbw_raddr),
|
.rallow_out(wbw_rallow),
|
.rallow_out(wbw_rallow),
|
.wallow_out(wbw_wallow)
|
.wallow_out(wbw_wallow)
|
);
|
);
|
|
|
WBR_FIFO_CONTROL #(WBR_ADDR_LENGTH) wbr_fifo_ctrl
|
WBR_FIFO_CONTROL #(WBR_ADDR_LENGTH) wbr_fifo_ctrl
|
( .rclock_in(wb_clock_in),
|
( .rclock_in(wb_clock_in),
|
.wclock_in(pci_clock_in),
|
.wclock_in(pci_clock_in),
|
.renable_in(wbr_renable_in),
|
.renable_in(wbr_renable_in),
|
.wenable_in(wbr_wenable_in),
|
.wenable_in(wbr_wenable_in),
|
.reset_in(reset_in),
|
.reset_in(reset_in),
|
.flush_in(wbr_flush_in),
|
.flush_in(wbr_flush_in),
|
.empty_out(wbr_empty),
|
.empty_out(wbr_empty),
|
.waddr_out(wbr_waddr),
|
.waddr_out(wbr_waddr),
|
.raddr_out(wbr_raddr),
|
.raddr_out(wbr_raddr),
|
.rallow_out(wbr_rallow),
|
.rallow_out(wbr_rallow),
|
.wallow_out(wbr_wallow)
|
.wallow_out(wbr_wallow)
|
);
|
);
|
|
|
|
|
// in and out transaction counters and grey codes
|
// in and out transaction counters and grey codes
|
reg [(WBW_ADDR_LENGTH-2):0] inGreyCount ;
|
reg [(WBW_ADDR_LENGTH-2):0] inGreyCount ;
|
reg [(WBW_ADDR_LENGTH-2):0] outGreyCount ;
|
reg [(WBW_ADDR_LENGTH-2):0] outGreyCount ;
|
wire [(WBW_ADDR_LENGTH-2):0] inNextGreyCount = {wbw_inTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_inTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_inTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
|
wire [(WBW_ADDR_LENGTH-2):0] inNextGreyCount = {wbw_inTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_inTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_inTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
|
wire [(WBW_ADDR_LENGTH-2):0] outNextGreyCount = {wbw_outTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_outTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_outTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
|
wire [(WBW_ADDR_LENGTH-2):0] outNextGreyCount = {wbw_outTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_outTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_outTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
|
|
|
// input transaction counter increment - when last data of transaction is written to fifo
|
// input transaction counter increment - when last data of transaction is written to fifo
|
wire in_count_en = wbw_wallow && wbw_last_in ;
|
wire in_count_en = wbw_wallow && wbw_last_in ;
|
|
|
// output transaction counter increment - when last data is on top of fifo and read from it
|
// output transaction counter increment - when last data is on top of fifo and read from it
|
wire out_count_en = wbw_renable_in && wbw_last_out ;
|
wire out_count_en = wbw_renable_in && wbw_last_out ;
|
|
|
// register holding grey coded count of incoming transactions
|
// register holding grey coded count of incoming transactions
|
always@(posedge wb_clock_in or posedge wbw_clear)
|
always@(posedge wb_clock_in or posedge wbw_clear)
|
begin
|
begin
|
if (wbw_clear)
|
if (wbw_clear)
|
begin
|
begin
|
inGreyCount[(WBW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
|
inGreyCount[(WBW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
|
inGreyCount[(WBW_ADDR_LENGTH-3):0] <= #`FF_DELAY {(WBW_ADDR_LENGTH-2),1'b0} ;
|
inGreyCount[(WBW_ADDR_LENGTH-3):0] <= #`FF_DELAY {(WBW_ADDR_LENGTH-2),1'b0} ;
|
end
|
end
|
else
|
else
|
if (in_count_en)
|
if (in_count_en)
|
inGreyCount <= #`FF_DELAY inNextGreyCount ;
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inGreyCount <= #`FF_DELAY inNextGreyCount ;
|
end
|
end
|
|
|
// register holding grey coded count of outgoing transactions
|
// register holding grey coded count of outgoing transactions
|
always@(posedge pci_clock_in or posedge wbw_clear)
|
always@(posedge pci_clock_in or posedge wbw_clear)
|
begin
|
begin
|
if (wbw_clear)
|
if (wbw_clear)
|
begin
|
begin
|
outGreyCount[(WBW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
|
outGreyCount[(WBW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
|
outGreyCount[(WBW_ADDR_LENGTH-3):0] <= #`FF_DELAY {(WBW_ADDR_LENGTH-2),1'b0} ;
|
outGreyCount[(WBW_ADDR_LENGTH-3):0] <= #`FF_DELAY {(WBW_ADDR_LENGTH-2),1'b0} ;
|
end
|
end
|
else
|
else
|
if (out_count_en)
|
if (out_count_en)
|
outGreyCount <= #`FF_DELAY outNextGreyCount ;
|
outGreyCount <= #`FF_DELAY outNextGreyCount ;
|
end
|
end
|
|
|
// incoming transactions counter
|
// incoming transactions counter
|
always@(posedge wb_clock_in or posedge wbw_clear)
|
always@(posedge wb_clock_in or posedge wbw_clear)
|
begin
|
begin
|
if (wbw_clear)
|
if (wbw_clear)
|
wbw_inTransactionCount <= #`FF_DELAY {(WBW_ADDR_LENGTH-1){1'b0}} ;
|
wbw_inTransactionCount <= #`FF_DELAY {(WBW_ADDR_LENGTH-1){1'b0}} ;
|
else
|
else
|
if (in_count_en)
|
if (in_count_en)
|
wbw_inTransactionCount <= #`FF_DELAY wbw_inTransactionCount + 1'b1 ;
|
wbw_inTransactionCount <= #`FF_DELAY wbw_inTransactionCount + 1'b1 ;
|
end
|
end
|
|
|
// outgoing transactions counter
|
// outgoing transactions counter
|
always@(posedge pci_clock_in or posedge wbw_clear)
|
always@(posedge pci_clock_in or posedge wbw_clear)
|
begin
|
begin
|
if (wbw_clear)
|
if (wbw_clear)
|
wbw_outTransactionCount <= #`FF_DELAY {(WBW_ADDR_LENGTH-1){1'b0}} ;
|
wbw_outTransactionCount <= #`FF_DELAY {(WBW_ADDR_LENGTH-1){1'b0}} ;
|
else
|
else
|
if (out_count_en)
|
if (out_count_en)
|
wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
|
wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
|
end
|
end
|
|
|
// synchronize transaction ready output to reading clock
|
// synchronize transaction ready output to reading clock
|
// transaction ready is set when incoming transaction count is not equal to outgoing transaction count (what goes in must come out logic)
|
// transaction ready is set when incoming transaction count is not equal to outgoing transaction count (what goes in must come out logic)
|
// transaction ready is cleared when whole transaction is pulled out of fifo (otherwise it could stay set for additional cycle and result in wrong op.)
|
// transaction ready is cleared when whole transaction is pulled out of fifo (otherwise it could stay set for additional cycle and result in wrong op.)
|
wire wbw_transaction_ready_flop_i = inGreyCount != outGreyCount ;
|
wire wbw_transaction_ready_flop_i = inGreyCount != outGreyCount ;
|
|
|
meta_flop #(0) i_meta_flop_wbw_transaction_ready
|
meta_flop #(0) i_meta_flop_wbw_transaction_ready
|
(
|
(
|
.rst_i (wbw_clear),
|
.rst_i (wbw_clear),
|
.clk_i (pci_clock_in),
|
.clk_i (pci_clock_in),
|
.ld_i (out_count_en),
|
.ld_i (out_count_en),
|
.ld_val_i (1'b0),
|
.ld_val_i (1'b0),
|
.en_i (1'b1),
|
.en_i (1'b1),
|
.d_i (wbw_transaction_ready_flop_i),
|
.d_i (wbw_transaction_ready_flop_i),
|
.meta_q_o (wbw_transaction_ready_out)
|
.meta_q_o (wbw_transaction_ready_out)
|
) ;
|
) ;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
