//===========================================================================
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//===========================================================================
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// $Id: pci_behaviorial_master.v,v 1.2 2002-03-21 07:35:50 mihad Exp $
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// $Id: pci_behaviorial_master.v,v 1.2 2002-03-21 07:35:50 mihad Exp $
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//
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//
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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//
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//
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// Summary: A PCI Behaviorial Master. This module accepts commands from
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// Summary: A PCI Behaviorial Master. This module accepts commands from
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// the top-level Stimulus generator. Based on arguments supplied
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// the top-level Stimulus generator. Based on arguments supplied
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// to it, it generates a reference containing paramaters to the
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// to it, it generates a reference containing paramaters to the
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// Target in the middle 16 bits of PCI Address. It also arbitrates
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// Target in the middle 16 bits of PCI Address. It also arbitrates
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// for the bus, sends data when writing, and compares returned data
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// for the bus, sends data when writing, and compares returned data
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// when reading.
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// when reading.
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// This interface does not understand retries after Target Disconnect
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// This interface does not understand retries after Target Disconnect
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// commands, and does not implement a disconnect counter.
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// commands, and does not implement a disconnect counter.
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//
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//
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// This library is free software; you can distribute it and/or modify it
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// This library is free software; you can distribute it and/or modify it
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// under the terms of the GNU Lesser General Public License as published
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// under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This library is distributed in the hope that it will be useful, but
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// This library is distributed in the hope that it will be useful, but
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// WITHOUT ANY WARRANTY; without even the implied warranty of
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// WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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// See the GNU Lesser General Public License for more details.
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// See the GNU Lesser General Public License for more details.
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//
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//
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// You should have received a copy of the GNU Lesser General Public License
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// You should have received a copy of the GNU Lesser General Public License
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// along with this library. If not, write to
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// along with this library. If not, write to
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// Free Software Foundation, Inc.
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// Free Software Foundation, Inc.
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// 59 Temple Place, Suite 330
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// 59 Temple Place, Suite 330
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// Boston, MA 02111-1307 USA
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// Boston, MA 02111-1307 USA
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//
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//
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// Author's note about this license: The intention of the Author and of
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// Author's note about this license: The intention of the Author and of
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// the Gnu Lesser General Public License is that users should be able to
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// the Gnu Lesser General Public License is that users should be able to
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// use this code for any purpose, including combining it with other source
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// use this code for any purpose, including combining it with other source
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// code, combining it with other logic, translated it into a gate-level
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// code, combining it with other logic, translated it into a gate-level
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// representation, or projected it into gates in a programmable or
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// representation, or projected it into gates in a programmable or
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// hardwired chip, as long as the users of the resulting source, compiled
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// hardwired chip, as long as the users of the resulting source, compiled
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// source, or chip are given the means to get a copy of this source code
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// source, or chip are given the means to get a copy of this source code
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// with no new restrictions on redistribution of this source.
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// with no new restrictions on redistribution of this source.
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//
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//
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// If you make changes, even substantial changes, to this code, or use
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// If you make changes, even substantial changes, to this code, or use
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// substantial parts of this code as an inseparable part of another work
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// substantial parts of this code as an inseparable part of another work
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// of authorship, the users of the resulting IP must be given the means
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// of authorship, the users of the resulting IP must be given the means
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// to get a copy of the modified or combined source code, with no new
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// to get a copy of the modified or combined source code, with no new
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// restrictions on redistribution of the resulting source.
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// restrictions on redistribution of the resulting source.
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//
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//
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// Separate parts of the combined source code, compiled code, or chip,
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// Separate parts of the combined source code, compiled code, or chip,
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// which are NOT derived from this source code do NOT need to be offered
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// which are NOT derived from this source code do NOT need to be offered
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// to the final user of the chip merely because they are used in
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// to the final user of the chip merely because they are used in
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// combination with this code. Other code is not forced to fall under
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// combination with this code. Other code is not forced to fall under
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// the GNU Lesser General Public License when it is linked to this code.
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// the GNU Lesser General Public License when it is linked to this code.
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// The license terms of other source code linked to this code might require
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// The license terms of other source code linked to this code might require
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// that it NOT be made available to users. The GNU Lesser General Public
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// that it NOT be made available to users. The GNU Lesser General Public
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// License does not prevent this code from being used in such a situation,
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// License does not prevent this code from being used in such a situation,
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// as long as the user of the resulting IP is given the means to get a
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// as long as the user of the resulting IP is given the means to get a
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// copy of this component of the IP with no new restrictions on
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// copy of this component of the IP with no new restrictions on
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// redistribution of this source.
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// redistribution of this source.
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//
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//
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// This code was developed using VeriLogger Pro, by Synapticad.
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// This code was developed using VeriLogger Pro, by Synapticad.
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// Their support is greatly appreciated.
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// Their support is greatly appreciated.
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//
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//
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// NOTE: This Test Chip instantiates one PCI interface and connects it
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// NOTE: This Test Chip instantiates one PCI interface and connects it
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// to its IO pads and to logic representing a real application.
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// to its IO pads and to logic representing a real application.
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//
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//
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// NOTE TODO: Horrible. Tasks can't depend on their Arguments being safe
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// NOTE TODO: Horrible. Tasks can't depend on their Arguments being safe
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// if there are several instances ofthe tasl running at once.
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// if there are several instances ofthe tasl running at once.
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// NOTE TODO: Verify that Fast-Back-To-Back references are done correctly
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// NOTE TODO: Verify that Fast-Back-To-Back references are done correctly
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// NOTE TODO: Verify that PERR and SERR are driven correctly, and that signals
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// NOTE TODO: Verify that PERR and SERR are driven correctly, and that signals
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// reflecting their detection are available for use in the Config Regs
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// reflecting their detection are available for use in the Config Regs
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// Detect and report PERR and SERR reports as enabled. 3.7.4
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// Detect and report PERR and SERR reports as enabled. 3.7.4
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// Start adding the address register needed to handle retries
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// Start adding the address register needed to handle retries
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// Start trying to understand the latency register. Why not simply
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// Start trying to understand the latency register. Why not simply
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// get off the bus when grant goes away?
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// get off the bus when grant goes away?
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// Do not do a retry or disconnect if all 4 BE wires are 1's. End of 3.8
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// Do not do a retry or disconnect if all 4 BE wires are 1's. End of 3.8
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// Start adding Latency Counter
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// Start adding Latency Counter
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// Complain if SERR caused by address parity error not seen when expected
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// Complain if SERR caused by address parity error not seen when expected
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// complain if data parity error not seen when expected
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// complain if data parity error not seen when expected
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//
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//
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//===========================================================================
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//===========================================================================
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module pci_behaviorial_master (
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module pci_behaviorial_master (
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ad_now, ad_prev, master_ad_out, master_ad_oe,
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ad_now, ad_prev, master_ad_out, master_ad_oe,
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master_cbe_l_out, master_cbe_oe,
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master_cbe_l_out, master_cbe_oe,
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calc_input_parity_prev,
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calc_input_parity_prev,
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par_now, par_prev,
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par_now, par_prev,
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frame_now, frame_prev, master_frame_out, master_frame_oe,
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frame_now, frame_prev, master_frame_out, master_frame_oe,
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irdy_now, irdy_prev, master_irdy_out, master_irdy_oe,
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irdy_now, irdy_prev, master_irdy_out, master_irdy_oe,
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devsel_now, devsel_prev, trdy_now, trdy_prev, stop_now, stop_prev,
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devsel_now, devsel_prev, trdy_now, trdy_prev, stop_now, stop_prev,
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perr_now, perr_prev, master_perr_out, master_perr_oe, master_serr_oe,
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perr_now, perr_prev, master_perr_out, master_perr_oe, master_serr_oe,
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master_req_out, master_gnt_now,
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master_req_out, master_gnt_now,
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pci_reset_comb, pci_ext_clk,
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pci_reset_comb, pci_ext_clk,
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// Signals from the master to the target to set bits in the Status Register
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// Signals from the master to the target to set bits in the Status Register
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master_got_parity_error, master_asserted_serr, master_got_master_abort,
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master_got_parity_error, master_asserted_serr, master_got_master_abort,
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master_got_target_abort, master_caused_parity_error,
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master_got_target_abort, master_caused_parity_error,
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master_enable, master_fast_b2b_en, master_perr_enable, master_serr_enable,
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master_enable, master_fast_b2b_en, master_perr_enable, master_serr_enable,
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master_latency_value,
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master_latency_value,
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// Signals used by the test bench instead of using "." notation
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// Signals used by the test bench instead of using "." notation
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master_debug_force_bad_par,
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master_debug_force_bad_par,
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test_master_number, test_address, test_command,
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test_master_number, test_address, test_command,
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test_data, test_byte_enables_l, test_size,
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test_data, test_byte_enables_l, test_size,
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test_make_addr_par_error, test_make_data_par_error,
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test_make_addr_par_error, test_make_data_par_error,
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test_master_initial_wait_states, test_master_subsequent_wait_states,
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test_master_initial_wait_states, test_master_subsequent_wait_states,
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test_target_initial_wait_states, test_target_subsequent_wait_states,
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test_target_initial_wait_states, test_target_subsequent_wait_states,
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test_target_devsel_speed, test_fast_back_to_back,
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test_target_devsel_speed, test_fast_back_to_back,
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test_target_termination,
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test_target_termination,
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test_expect_master_abort,
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test_expect_master_abort,
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test_start, test_accepted_l, test_error_event,
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test_start, test_accepted_l, test_error_event,
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test_device_id,
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test_device_id,
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master_received_data,
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master_received_data,
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master_received_data_valid,
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master_received_data_valid,
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master_check_received_data
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master_check_received_data
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);
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);
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`include "pci_blue_options.vh"
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`include "pci_blue_options.vh"
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`include "pci_blue_constants.vh"
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`include "pci_blue_constants.vh"
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input [PCI_BUS_DATA_RANGE:0] ad_now;
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input [PCI_BUS_DATA_RANGE:0] ad_now;
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input [PCI_BUS_DATA_RANGE:0] ad_prev;
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input [PCI_BUS_DATA_RANGE:0] ad_prev;
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output [PCI_BUS_DATA_RANGE:0] master_ad_out;
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output [PCI_BUS_DATA_RANGE:0] master_ad_out;
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output master_ad_oe;
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output master_ad_oe;
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output [PCI_BUS_CBE_RANGE:0] master_cbe_l_out;
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output [PCI_BUS_CBE_RANGE:0] master_cbe_l_out;
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output master_cbe_oe;
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output master_cbe_oe;
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input calc_input_parity_prev;
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input calc_input_parity_prev;
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input par_now, par_prev;
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input par_now, par_prev;
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input frame_now, frame_prev;
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input frame_now, frame_prev;
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output master_frame_out, master_frame_oe;
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output master_frame_out, master_frame_oe;
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input irdy_now, irdy_prev;
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input irdy_now, irdy_prev;
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output master_irdy_out, master_irdy_oe;
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output master_irdy_out, master_irdy_oe;
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input devsel_now, devsel_prev, trdy_now, trdy_prev, stop_now, stop_prev;
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input devsel_now, devsel_prev, trdy_now, trdy_prev, stop_now, stop_prev;
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input perr_now, perr_prev;
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input perr_now, perr_prev;
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output master_perr_out, master_perr_oe, master_serr_oe;
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output master_perr_out, master_perr_oe, master_serr_oe;
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output master_req_out;
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output master_req_out;
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input master_gnt_now;
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input master_gnt_now;
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input pci_reset_comb, pci_ext_clk;
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input pci_reset_comb, pci_ext_clk;
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// Signals from the master to the target to set bits in the Status Register
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// Signals from the master to the target to set bits in the Status Register
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output master_got_parity_error, master_asserted_serr, master_got_master_abort;
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output master_got_parity_error, master_asserted_serr, master_got_master_abort;
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output master_got_target_abort, master_caused_parity_error;
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output master_got_target_abort, master_caused_parity_error;
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input master_enable, master_fast_b2b_en, master_perr_enable, master_serr_enable;
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input master_enable, master_fast_b2b_en, master_perr_enable, master_serr_enable;
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input [7:0] master_latency_value; // NOTE WORKING
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input [7:0] master_latency_value; // NOTE WORKING
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// Signals used by the test bench instead of using "." notation
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// Signals used by the test bench instead of using "." notation
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output master_debug_force_bad_par;
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output master_debug_force_bad_par;
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input [2:0] test_master_number;
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input [2:0] test_master_number;
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input [PCI_BUS_DATA_RANGE:0] test_address;
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input [PCI_BUS_DATA_RANGE:0] test_address;
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input [PCI_BUS_CBE_RANGE:0] test_command;
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input [PCI_BUS_CBE_RANGE:0] test_command;
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input [PCI_BUS_DATA_RANGE:0] test_data;
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input [PCI_BUS_DATA_RANGE:0] test_data;
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input [PCI_BUS_CBE_RANGE:0] test_byte_enables_l;
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input [PCI_BUS_CBE_RANGE:0] test_byte_enables_l;
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input [9:0] test_size;
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input [9:0] test_size;
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input test_make_addr_par_error, test_make_data_par_error;
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input test_make_addr_par_error, test_make_data_par_error;
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input [3:0] test_master_initial_wait_states;
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input [3:0] test_master_initial_wait_states;
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input [3:0] test_master_subsequent_wait_states;
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input [3:0] test_master_subsequent_wait_states;
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input [3:0] test_target_initial_wait_states;
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input [3:0] test_target_initial_wait_states;
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input [3:0] test_target_subsequent_wait_states;
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input [3:0] test_target_subsequent_wait_states;
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input [1:0] test_target_devsel_speed;
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input [1:0] test_target_devsel_speed;
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input test_fast_back_to_back;
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input test_fast_back_to_back;
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input [2:0] test_target_termination;
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input [2:0] test_target_termination;
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input test_expect_master_abort;
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input test_expect_master_abort;
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input test_start;
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input test_start;
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output test_accepted_l;
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output test_accepted_l;
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output test_error_event;
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output test_error_event;
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input [2:0] test_device_id;
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input [2:0] test_device_id;
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output [PCI_BUS_DATA_RANGE:0] master_received_data ;
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output [PCI_BUS_DATA_RANGE:0] master_received_data ;
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output master_received_data_valid ;
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output master_received_data_valid ;
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input master_check_received_data ;
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input master_check_received_data ;
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reg [PCI_BUS_DATA_RANGE:0] master_ad_out;
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reg [PCI_BUS_DATA_RANGE:0] master_ad_out;
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reg master_ad_oe;
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reg master_ad_oe;
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reg [PCI_BUS_CBE_RANGE:0] master_cbe_l_out;
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reg [PCI_BUS_CBE_RANGE:0] master_cbe_l_out;
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reg master_cbe_oe;
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reg master_cbe_oe;
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reg master_frame_out, master_irdy_out;
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reg master_frame_out, master_irdy_out;
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wire master_frame_oe, master_irdy_oe, master_perr_oe, master_serr_oe;
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wire master_frame_oe, master_irdy_oe, master_perr_oe, master_serr_oe;
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reg master_perr_out;
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reg master_perr_out;
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reg master_req_out;
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reg master_req_out;
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reg master_debug_force_bad_par;
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reg master_debug_force_bad_par;
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reg [PCI_BUS_DATA_RANGE:0] master_received_data ;
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reg [PCI_BUS_DATA_RANGE:0] master_received_data ;
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reg master_received_data_valid ;
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reg master_received_data_valid ;
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// Let test commander know when this PCI Master has accepted the command.
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// Let test commander know when this PCI Master has accepted the command.
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reg test_accepted_next, test_accepted_int;
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reg test_accepted_next, test_accepted_int;
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// Display on negative edge so easy to see
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// Display on negative edge so easy to see
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always @(negedge pci_ext_clk or posedge pci_reset_comb)
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always @(negedge pci_ext_clk or posedge pci_reset_comb)
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begin
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begin
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if (pci_reset_comb)
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if (pci_reset_comb)
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begin
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begin
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test_accepted_int <= 1'b0;
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test_accepted_int <= 1'b0;
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master_received_data_valid <= 1'b0 ;
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master_received_data_valid <= 1'b0 ;
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end
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end
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else
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else
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begin
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begin
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test_accepted_int <= test_accepted_next;
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test_accepted_int <= test_accepted_next;
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end
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end
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end
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end
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assign test_accepted_l = test_accepted_int ? 1'b0 : 1'bZ;
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assign test_accepted_l = test_accepted_int ? 1'b0 : 1'bZ;
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// Make temporary Bip every time an error is detected
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// Make temporary Bip every time an error is detected
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reg test_error_event;
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reg test_error_event;
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initial test_error_event <= 1'bZ;
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initial test_error_event <= 1'bZ;
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reg error_detected;
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reg error_detected;
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initial error_detected <= 1'b0;
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initial error_detected <= 1'b0;
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always @(error_detected)
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always @(error_detected)
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begin
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begin
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test_error_event <= 1'b0;
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test_error_event <= 1'b0;
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#2;
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#2;
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test_error_event <= 1'bZ;
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test_error_event <= 1'bZ;
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end
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end
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// Make the FRAME_OE and IRDY_OE output enable signals. They must
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// Make the FRAME_OE and IRDY_OE output enable signals. They must
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// become asserted as soon as each of those signals become asserted, and
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// become asserted as soon as each of those signals become asserted, and
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// must stay asserted one clock after the signal becomes deasserted.
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// must stay asserted one clock after the signal becomes deasserted.
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reg prev_frame_asserted, prev_irdy_asserted;
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reg prev_frame_asserted, prev_irdy_asserted;
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always @(posedge pci_ext_clk or posedge pci_reset_comb)
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always @(posedge pci_ext_clk or posedge pci_reset_comb)
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begin
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begin
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if (pci_reset_comb)
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if (pci_reset_comb)
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begin
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begin
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prev_frame_asserted <= 1'b0;
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prev_frame_asserted <= 1'b0;
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prev_irdy_asserted <= 1'b0;
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prev_irdy_asserted <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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prev_frame_asserted <= master_frame_out;
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prev_frame_asserted <= master_frame_out;
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prev_irdy_asserted <= master_irdy_out;
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prev_irdy_asserted <= master_irdy_out;
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end
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end
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end
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end
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assign master_frame_oe = master_frame_out | prev_frame_asserted;
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assign master_frame_oe = master_frame_out | prev_frame_asserted;
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assign master_irdy_oe = master_irdy_out | prev_irdy_asserted;
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assign master_irdy_oe = master_irdy_out | prev_irdy_asserted;
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|
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// Make the PERR_OE signal.
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// Make the PERR_OE signal.
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// See the PCI Local Bus Spec Revision 2.2 section 3.7.4.1
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// See the PCI Local Bus Spec Revision 2.2 section 3.7.4.1
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// At time N, master_perr_check_next is set
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// At time N, master_perr_check_next is set
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// At time N+1, external data is latched, and trdy is also latched
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// At time N+1, external data is latched, and trdy is also latched
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// At time N+1, master_perr_check is latched
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// At time N+1, master_perr_check is latched
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// At time N+2, calc_input_parity_prev is valid
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// At time N+2, calc_input_parity_prev is valid
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// Also at N+2, external parity is valid
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// Also at N+2, external parity is valid
|
// Target can assert data slowly the first reference.
|
// Target can assert data slowly the first reference.
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// Qualify PERR with TRDY (?)
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// Qualify PERR with TRDY (?)
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reg master_perr_prev, master_perr_check_next, master_perr_check;
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reg master_perr_prev, master_perr_check_next, master_perr_check;
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reg master_oe_prev, master_oe_prev_prev;
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reg master_oe_prev, master_oe_prev_prev;
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reg master_perr_detected, master_target_perr_received;
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reg master_perr_detected, master_target_perr_received;
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reg master_debug_force_bad_perr ;
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reg master_debug_force_bad_perr ;
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|
|
always @(posedge pci_ext_clk or posedge pci_reset_comb)
|
always @(posedge pci_ext_clk or posedge pci_reset_comb)
|
begin
|
begin
|
if (pci_reset_comb)
|
if (pci_reset_comb)
|
master_debug_force_bad_perr <= 1'b0 ;
|
master_debug_force_bad_perr <= 1'b0 ;
|
else
|
else
|
master_debug_force_bad_perr <= master_debug_force_bad_par ;
|
master_debug_force_bad_perr <= master_debug_force_bad_par ;
|
end
|
end
|
|
|
always @(posedge pci_ext_clk or posedge pci_reset_comb)
|
always @(posedge pci_ext_clk or posedge pci_reset_comb)
|
begin
|
begin
|
if (pci_reset_comb)
|
if (pci_reset_comb)
|
begin
|
begin
|
master_perr_check <= 1'b0;
|
master_perr_check <= 1'b0;
|
master_perr_detected <= 1'b0;
|
master_perr_detected <= 1'b0;
|
master_target_perr_received <= 1'b0;
|
master_target_perr_received <= 1'b0;
|
master_perr_out <= 1'b0;
|
master_perr_out <= 1'b0;
|
master_perr_prev <= 1'b0;
|
master_perr_prev <= 1'b0;
|
master_oe_prev <= 1'b0;
|
master_oe_prev <= 1'b0;
|
master_oe_prev_prev <= 1'b0;
|
master_oe_prev_prev <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
master_perr_check <= master_perr_check_next;
|
master_perr_check <= master_perr_check_next;
|
master_perr_detected <= master_perr_check & trdy_prev
|
master_perr_detected <= master_perr_check & trdy_prev
|
& (calc_input_parity_prev != par_now);
|
& (calc_input_parity_prev != par_now);
|
master_oe_prev <= master_ad_oe;
|
master_oe_prev <= master_ad_oe;
|
master_oe_prev_prev <= master_oe_prev;
|
master_oe_prev_prev <= master_oe_prev;
|
master_target_perr_received <= master_oe_prev_prev & perr_now;
|
master_target_perr_received <= master_oe_prev_prev & perr_now;
|
master_perr_out <= master_perr_check & trdy_prev & master_perr_enable
|
master_perr_out <= master_perr_check & trdy_prev & master_perr_enable
|
& (calc_input_parity_prev != ( par_now ^ master_debug_force_bad_perr));
|
& (calc_input_parity_prev != ( par_now ^ master_debug_force_bad_perr));
|
master_perr_prev <= master_perr_out;
|
master_perr_prev <= master_perr_out;
|
end
|
end
|
end
|
end
|
assign master_perr_oe = master_perr_out | master_perr_prev;
|
assign master_perr_oe = master_perr_out | master_perr_prev;
|
|
|
// Tell the Config Status Register when errors occur
|
// Tell the Config Status Register when errors occur
|
assign master_got_parity_error = master_perr_detected;
|
assign master_got_parity_error = master_perr_detected;
|
assign master_serr_oe = 1'b0; // This master NEVER asserts SERR
|
assign master_serr_oe = 1'b0; // This master NEVER asserts SERR
|
assign master_asserted_serr = 1'b0; // This master NEVER asserts SERR
|
assign master_asserted_serr = 1'b0; // This master NEVER asserts SERR
|
reg master_got_master_abort, master_got_target_abort, master_got_target_retry; // assigned in state machine
|
reg master_got_master_abort, master_got_target_abort, master_got_target_retry; // assigned in state machine
|
// PERR_detected or PERR pin seen while master
|
// PERR_detected or PERR pin seen while master
|
// See the PCI Local Bus Spec Revision 2.2 section 6.2.3
|
// See the PCI Local Bus Spec Revision 2.2 section 6.2.3
|
assign master_caused_parity_error = master_perr_out
|
assign master_caused_parity_error = master_perr_out
|
| (master_target_perr_received & master_perr_enable);
|
| (master_target_perr_received & master_perr_enable);
|
|
|
// Remember whether this device drove the AD Bus last clock, which allows
|
// Remember whether this device drove the AD Bus last clock, which allows
|
// Zero-Wait-State Back-to-Back references
|
// Zero-Wait-State Back-to-Back references
|
wire This_Master_Drove_The_AD_Bus_The_Last_Clock = master_ad_oe;
|
wire This_Master_Drove_The_AD_Bus_The_Last_Clock = master_ad_oe;
|
|
|
// Model of a Master Source of Data, which writes whatever it wants on bursts
|
// Model of a Master Source of Data, which writes whatever it wants on bursts
|
task Compare_Read_Data_With_Expected_Data;
|
task Compare_Read_Data_With_Expected_Data;
|
input [PCI_BUS_DATA_RANGE:0] target_read_data;
|
input [PCI_BUS_DATA_RANGE:0] target_read_data;
|
input [PCI_BUS_DATA_RANGE:0] master_check_data;
|
input [PCI_BUS_DATA_RANGE:0] master_check_data;
|
input [PCI_BUS_CBE_RANGE:0] mask_l;// Added by Tadej M. on 11.12.2001
|
input [PCI_BUS_CBE_RANGE:0] mask_l;// Added by Tadej M. on 11.12.2001
|
begin // Added by Tadej M. on 11.12.2001
|
begin // Added by Tadej M. on 11.12.2001
|
if (~pci_reset_comb & ((target_read_data[31:24] != master_check_data[31:24]) & ~mask_l[3]) &
|
if (~pci_reset_comb & ((target_read_data[31:24] != master_check_data[31:24]) & ~mask_l[3]) &
|
((target_read_data[23:16] != master_check_data[23:16]) & ~mask_l[2]) &
|
((target_read_data[23:16] != master_check_data[23:16]) & ~mask_l[2]) &
|
((target_read_data[15:8] != master_check_data[15:8]) & ~mask_l[1]) &
|
((target_read_data[15:8] != master_check_data[15:8]) & ~mask_l[1]) &
|
((target_read_data[7:0] != master_check_data[7:0]) & ~mask_l[0]) )
|
((target_read_data[7:0] != master_check_data[7:0]) & ~mask_l[0]) )
|
begin
|
begin
|
$display ("*** test master %h - Master Read Data 'h%x not as expected 'h%x, at %t",
|
$display ("*** test master %h - Master Read Data 'h%x not as expected 'h%x, at %t",
|
test_device_id[2:0], target_read_data[PCI_BUS_DATA_RANGE:0],
|
test_device_id[2:0], target_read_data[PCI_BUS_DATA_RANGE:0],
|
master_check_data[PCI_BUS_DATA_RANGE:0], $time);
|
master_check_data[PCI_BUS_DATA_RANGE:0], $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
endtask
|
endtask
|
|
|
// Tasks can't have local storage! have to be module global
|
// Tasks can't have local storage! have to be module global
|
reg [PCI_BUS_DATA_RANGE:0] up_temp;
|
reg [PCI_BUS_DATA_RANGE:0] up_temp;
|
task Update_Write_Data;
|
task Update_Write_Data;
|
input [PCI_BUS_DATA_RANGE:0] master_write_data;
|
input [PCI_BUS_DATA_RANGE:0] master_write_data;
|
input [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
input [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
output [PCI_BUS_DATA_RANGE:0] master_write_data_next;
|
output [PCI_BUS_DATA_RANGE:0] master_write_data_next;
|
output [PCI_BUS_CBE_RANGE:0] master_mask_l_next;
|
output [PCI_BUS_CBE_RANGE:0] master_mask_l_next;
|
begin
|
begin
|
up_temp[31:24] = master_write_data[31:24] + 8'h01;
|
up_temp[31:24] = master_write_data[31:24] + 8'h01;
|
up_temp[23:16] = master_write_data[23:16] + 8'h01;
|
up_temp[23:16] = master_write_data[23:16] + 8'h01;
|
up_temp[15: 8] = master_write_data[15: 8] + 8'h01;
|
up_temp[15: 8] = master_write_data[15: 8] + 8'h01;
|
up_temp[ 7: 0] = master_write_data[ 7: 0] + 8'h01;
|
up_temp[ 7: 0] = master_write_data[ 7: 0] + 8'h01;
|
// Wrap adds so that things repeat in the 256 Byte (64 Word) Target SRAM
|
// Wrap adds so that things repeat in the 256 Byte (64 Word) Target SRAM
|
master_write_data_next[PCI_BUS_DATA_RANGE:0] = up_temp[PCI_BUS_DATA_RANGE:0];// & 32'h3F3F3F3F; commented by Tadej M. on 07.12.2001
|
master_write_data_next[PCI_BUS_DATA_RANGE:0] = up_temp[PCI_BUS_DATA_RANGE:0];// & 32'h3F3F3F3F; commented by Tadej M. on 07.12.2001
|
master_mask_l_next[PCI_BUS_CBE_RANGE:0] = {master_mask_l[2:0], master_mask_l[3]};
|
master_mask_l_next[PCI_BUS_CBE_RANGE:0] = {master_mask_l[2:0], master_mask_l[3]};
|
end
|
end
|
endtask
|
endtask
|
|
|
// Counter to detect unexpected master aborts
|
// Counter to detect unexpected master aborts
|
reg [2:0] Master_Abort_Counter;
|
reg [2:0] Master_Abort_Counter;
|
|
|
task Init_Master_Abort_Counter;
|
task Init_Master_Abort_Counter;
|
begin
|
begin
|
Master_Abort_Counter <= 3'h1;
|
Master_Abort_Counter <= 3'h1;
|
end
|
end
|
endtask
|
endtask
|
|
|
task Inc_Master_Abort_Counter;
|
task Inc_Master_Abort_Counter;
|
begin
|
begin
|
if (Master_Abort_Counter < 3'h7) // count up cycles since Address
|
if (Master_Abort_Counter < 3'h7) // count up cycles since Address
|
begin
|
begin
|
Master_Abort_Counter <= Master_Abort_Counter + 3'h1;
|
Master_Abort_Counter <= Master_Abort_Counter + 3'h1;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
endtask
|
endtask
|
|
|
task Check_Master_Abort_Counter;
|
task Check_Master_Abort_Counter;
|
output got_master_abort;
|
output got_master_abort;
|
begin
|
begin
|
got_master_abort = (Master_Abort_Counter >= 3'h5);
|
got_master_abort = (Master_Abort_Counter >= 3'h5);
|
end
|
end
|
endtask
|
endtask
|
|
|
// Signals used by Master test code to apply correct info to the PCI bus
|
// Signals used by Master test code to apply correct info to the PCI bus
|
reg [23:9] hold_master_address;
|
reg [23:9] hold_master_address;
|
reg [PCI_BUS_CBE_RANGE:0] hold_master_command;
|
reg [PCI_BUS_CBE_RANGE:0] hold_master_command;
|
reg [PCI_BUS_DATA_RANGE:0] hold_master_data;
|
reg [PCI_BUS_DATA_RANGE:0] hold_master_data;
|
reg [PCI_BUS_CBE_RANGE:0] hold_master_byte_enables_l;
|
reg [PCI_BUS_CBE_RANGE:0] hold_master_byte_enables_l;
|
reg [9:0] hold_master_size;
|
reg [9:0] hold_master_size;
|
reg hold_master_addr_par_err, hold_master_data_par_err;
|
reg hold_master_addr_par_err, hold_master_data_par_err;
|
reg [3:0] hold_master_initial_waitstates;
|
reg [3:0] hold_master_initial_waitstates;
|
reg [3:0] hold_master_subsequent_waitstates;
|
reg [3:0] hold_master_subsequent_waitstates;
|
reg [3:0] hold_master_target_initial_waitstates;
|
reg [3:0] hold_master_target_initial_waitstates;
|
reg [3:0] hold_master_target_subsequent_waitstates;
|
reg [3:0] hold_master_target_subsequent_waitstates;
|
reg [1:0] hold_master_target_devsel_speed;
|
reg [1:0] hold_master_target_devsel_speed;
|
reg hold_master_fast_b2b;
|
reg hold_master_fast_b2b;
|
reg [2:0] hold_master_target_termination;
|
reg [2:0] hold_master_target_termination;
|
reg hold_master_expect_master_abort;
|
reg hold_master_expect_master_abort;
|
reg [PCI_BUS_DATA_RANGE:0] modified_master_address;
|
reg [PCI_BUS_DATA_RANGE:0] modified_master_address;
|
|
|
// Tasks to do behaviorial PCI references
|
// Tasks to do behaviorial PCI references
|
// NOTE all tasks end with an @(posedge pci_ext_clk) statement
|
// NOTE all tasks end with an @(posedge pci_ext_clk) statement
|
// to let any signals asserted during that task settle out.
|
// to let any signals asserted during that task settle out.
|
// If a task DOESN'T end with @(posedge pci_ext_clk), then it must
|
// If a task DOESN'T end with @(posedge pci_ext_clk), then it must
|
// be called just before some other task which does.
|
// be called just before some other task which does.
|
|
|
parameter TEST_MASTER_SPINLOOP_MAX = 20;
|
parameter TEST_MASTER_SPINLOOP_MAX = 20;
|
|
|
task Clock_Wait_Unless_Reset;
|
task Clock_Wait_Unless_Reset;
|
begin
|
begin
|
if (~pci_reset_comb)
|
if (~pci_reset_comb)
|
begin
|
begin
|
@ (posedge pci_ext_clk or posedge pci_reset_comb) ;
|
@ (posedge pci_ext_clk or posedge pci_reset_comb) ;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
endtask
|
endtask
|
|
|
task Assert_FRAME;
|
task Assert_FRAME;
|
begin
|
begin
|
master_frame_out <= 1'b1;
|
master_frame_out <= 1'b1;
|
end
|
end
|
endtask
|
endtask
|
|
|
task Deassert_FRAME;
|
task Deassert_FRAME;
|
begin
|
begin
|
master_frame_out <= 1'b0;
|
master_frame_out <= 1'b0;
|
end
|
end
|
endtask
|
endtask
|
|
|
task Assert_IRDY;
|
task Assert_IRDY;
|
begin
|
begin
|
master_irdy_out <= 1'b1;
|
master_irdy_out <= 1'b1;
|
end
|
end
|
endtask
|
endtask
|
|
|
task Deassert_IRDY;
|
task Deassert_IRDY;
|
begin
|
begin
|
master_irdy_out <= 1'b0;
|
master_irdy_out <= 1'b0;
|
end
|
end
|
endtask
|
endtask
|
|
|
task Assert_Master_Continue_Or_Terminate;
|
task Assert_Master_Continue_Or_Terminate;
|
input do_master_terminate;
|
input do_master_terminate;
|
begin
|
begin
|
if (do_master_terminate)
|
if (do_master_terminate)
|
begin
|
begin
|
Deassert_FRAME; Assert_IRDY;
|
Deassert_FRAME; Assert_IRDY;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Assert_FRAME; Assert_IRDY;
|
Assert_FRAME; Assert_IRDY;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
task Indicate_Start;
|
task Indicate_Start;
|
begin
|
begin
|
`ifdef VERBOSE_TEST_DEVICE
|
`ifdef VERBOSE_TEST_DEVICE
|
$display (" test %h - Task Started, at %t", test_device_id[2:0], $time);
|
$display (" test %h - Task Started, at %t", test_device_id[2:0], $time);
|
`endif // VERBOSE_TEST_DEVICE
|
`endif // VERBOSE_TEST_DEVICE
|
test_accepted_next <= 1'b1;
|
test_accepted_next <= 1'b1;
|
end
|
end
|
endtask
|
endtask
|
|
|
task Indicate_Done;
|
task Indicate_Done;
|
begin
|
begin
|
// `ifdef VERBOSE_TEST_DEVICE
|
// `ifdef VERBOSE_TEST_DEVICE
|
// $display (" test %h - Task Done, at %t", test_device_id[2:0], $time);
|
// $display (" test %h - Task Done, at %t", test_device_id[2:0], $time);
|
// `endif // VERBOSE_TEST_DEVICE
|
// `endif // VERBOSE_TEST_DEVICE
|
test_accepted_next <= 1'b0;
|
test_accepted_next <= 1'b0;
|
end
|
end
|
endtask
|
endtask
|
|
|
task Master_Req_Bus; // must be followed by an address assertion task
|
task Master_Req_Bus; // must be followed by an address assertion task
|
begin
|
begin
|
`ifdef VERBOSE_TEST_DEVICE
|
`ifdef VERBOSE_TEST_DEVICE
|
$display (" test %h - Requesting the bus, at %t",
|
$display (" test %h - Requesting the bus, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
`endif // VERBOSE_TEST_DEVICE
|
`endif // VERBOSE_TEST_DEVICE
|
master_req_out <= 1'b1;
|
master_req_out <= 1'b1;
|
end
|
end
|
endtask
|
endtask
|
|
|
task Master_Unreq_Bus; // must be followed by SOMETHING???
|
task Master_Unreq_Bus; // must be followed by SOMETHING???
|
begin
|
begin
|
`ifdef VERBOSE_TEST_DEVICE
|
`ifdef VERBOSE_TEST_DEVICE
|
$display (" test %h - Un-Requesting the bus, at %t",
|
$display (" test %h - Un-Requesting the bus, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
`endif // VERBOSE_TEST_DEVICE
|
`endif // VERBOSE_TEST_DEVICE
|
master_req_out <= 1'b0;
|
master_req_out <= 1'b0;
|
end
|
end
|
endtask
|
endtask
|
|
|
parameter TEST_MASTER_IMMEDIATE_ADDRESS = 1'b0;
|
parameter TEST_MASTER_IMMEDIATE_ADDRESS = 1'b0;
|
parameter TEST_MASTER_STEP_ADDRESS = 1'b1;
|
parameter TEST_MASTER_STEP_ADDRESS = 1'b1;
|
|
|
// Tasks can't have local storage! have to be module global
|
// Tasks can't have local storage! have to be module global
|
integer ii; // sequential code, so OK to use "=" assignment operator
|
integer ii; // sequential code, so OK to use "=" assignment operator
|
reg first_step_delay;
|
reg first_step_delay;
|
task Master_Assert_Address;
|
task Master_Assert_Address;
|
input [PCI_BUS_DATA_RANGE:0] address;
|
input [PCI_BUS_DATA_RANGE:0] address;
|
input [PCI_BUS_CBE_RANGE:0] command;
|
input [PCI_BUS_CBE_RANGE:0] command;
|
input address_speed, enable_fast_back_to_back, force_addr_par_error;
|
input address_speed, enable_fast_back_to_back, force_addr_par_error;
|
begin
|
begin
|
`ifdef VERBOSE_TEST_DEVICE
|
`ifdef VERBOSE_TEST_DEVICE
|
$display (" test %h - Driving Address 'h%x, CBE 'h%x, at %t",
|
$display (" test %h - Driving Address 'h%x, CBE 'h%x, at %t",
|
test_device_id[2:0], address[PCI_BUS_DATA_RANGE:0],
|
test_device_id[2:0], address[PCI_BUS_DATA_RANGE:0],
|
command[PCI_BUS_CBE_RANGE:0], $time);
|
command[PCI_BUS_CBE_RANGE:0], $time);
|
`endif // VERBOSE_TEST_DEVICE
|
`endif // VERBOSE_TEST_DEVICE
|
first_step_delay = (address_speed == TEST_MASTER_STEP_ADDRESS);
|
first_step_delay = (address_speed == TEST_MASTER_STEP_ADDRESS);
|
for (ii = 0; ii < TEST_MASTER_SPINLOOP_MAX; ii = ii + 1)
|
for (ii = 0; ii < TEST_MASTER_SPINLOOP_MAX; ii = ii + 1)
|
begin
|
begin
|
if (master_gnt_now
|
if (master_gnt_now
|
& ( (~frame_now & ~irdy_now) // and bus previously idle
|
& ( (~frame_now & ~irdy_now) // and bus previously idle
|
// ... or we previously were driving data, so fast back-to-back is possible.
|
// ... or we previously were driving data, so fast back-to-back is possible.
|
| ( ~frame_now & irdy_now
|
| ( ~frame_now & irdy_now
|
& This_Master_Drove_The_AD_Bus_The_Last_Clock
|
& This_Master_Drove_The_AD_Bus_The_Last_Clock
|
& enable_fast_back_to_back & master_fast_b2b_en) ) )
|
& enable_fast_back_to_back & master_fast_b2b_en) ) )
|
begin
|
begin
|
if (first_step_delay == 1'b1)
|
if (first_step_delay == 1'b1)
|
begin // stepping, so drive address with some unknown bits
|
begin // stepping, so drive address with some unknown bits
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= address[PCI_BUS_DATA_RANGE:0] ^ 32'hXX00XX00;
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= address[PCI_BUS_DATA_RANGE:0] ^ 32'hXX00XX00;
|
master_ad_oe <= 1'b1;
|
master_ad_oe <= 1'b1;
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= command[PCI_BUS_CBE_RANGE:0] ^ 4'bX0X0;
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= command[PCI_BUS_CBE_RANGE:0] ^ 4'bX0X0;
|
master_cbe_oe <= 1'b1;
|
master_cbe_oe <= 1'b1;
|
master_debug_force_bad_par <= 1'b1;
|
master_debug_force_bad_par <= 1'b1;
|
master_got_master_abort <= 1'b0;
|
master_got_master_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_perr_check_next <= 1'b0;
|
master_perr_check_next <= 1'b0;
|
Deassert_FRAME;
|
Deassert_FRAME;
|
Deassert_IRDY;
|
Deassert_IRDY;
|
first_step_delay = 1'b0; // next time through, make frame
|
first_step_delay = 1'b0; // next time through, make frame
|
end
|
end
|
else
|
else
|
begin // drive address AND frame
|
begin // drive address AND frame
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= address[PCI_BUS_DATA_RANGE:0];
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= address[PCI_BUS_DATA_RANGE:0];
|
master_ad_oe <= 1'b1;
|
master_ad_oe <= 1'b1;
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= command[PCI_BUS_CBE_RANGE:0];
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= command[PCI_BUS_CBE_RANGE:0];
|
master_cbe_oe <= 1'b1;
|
master_cbe_oe <= 1'b1;
|
master_debug_force_bad_par <= force_addr_par_error;
|
master_debug_force_bad_par <= force_addr_par_error;
|
master_got_master_abort <= 1'b0;
|
master_got_master_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_perr_check_next <= 1'b0;
|
master_perr_check_next <= 1'b0;
|
Assert_FRAME;
|
Assert_FRAME;
|
Deassert_IRDY;
|
Deassert_IRDY;
|
Init_Master_Abort_Counter; // just completed master cycle 1
|
Init_Master_Abort_Counter; // just completed master cycle 1
|
first_step_delay = 1'b0; // next time through, make frame
|
first_step_delay = 1'b0; // next time through, make frame
|
ii = TEST_MASTER_SPINLOOP_MAX + 1; // break
|
ii = TEST_MASTER_SPINLOOP_MAX + 1; // break
|
end
|
end
|
end
|
end
|
else
|
else
|
begin // might have lost things after first step. Undrive everything.
|
begin // might have lost things after first step. Undrive everything.
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
|
master_ad_oe <= 1'b0;
|
master_ad_oe <= 1'b0;
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4; // easy to see
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4; // easy to see
|
master_cbe_oe <= 1'b0;
|
master_cbe_oe <= 1'b0;
|
master_debug_force_bad_par <= 1'b0;
|
master_debug_force_bad_par <= 1'b0;
|
master_got_master_abort <= 1'b0;
|
master_got_master_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_perr_check_next <= 1'b0;
|
master_perr_check_next <= 1'b0;
|
Deassert_FRAME;
|
Deassert_FRAME;
|
Deassert_IRDY;
|
Deassert_IRDY;
|
first_step_delay = (address_speed == TEST_MASTER_STEP_ADDRESS);
|
first_step_delay = (address_speed == TEST_MASTER_STEP_ADDRESS);
|
end
|
end
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
Indicate_Done; // indicate done as early as possible, while still after start
|
Indicate_Done; // indicate done as early as possible, while still after start
|
end
|
end
|
`ifdef NORMAL_PCI_CHECKS
|
`ifdef NORMAL_PCI_CHECKS
|
if (~pci_reset_comb & (ii == TEST_MASTER_SPINLOOP_MAX))
|
if (~pci_reset_comb & (ii == TEST_MASTER_SPINLOOP_MAX))
|
begin
|
begin
|
$display ("*** test %h - PCI Gnt never arrived, at %t",
|
$display ("*** test %h - PCI Gnt never arrived, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
`endif // NORMAL_PCI_CHECKS
|
`endif // NORMAL_PCI_CHECKS
|
end
|
end
|
endtask
|
endtask
|
|
|
// While asserting FRAME, wait zero or more clocks as commanded by master
|
// While asserting FRAME, wait zero or more clocks as commanded by master
|
// tasks can't have local storage! have to be module global
|
// tasks can't have local storage! have to be module global
|
reg [3:0] cnt;
|
reg [3:0] cnt;
|
task Execute_Master_Waitstates_But_Quit_On_Target_Abort;
|
task Execute_Master_Waitstates_But_Quit_On_Target_Abort;
|
input drive_ad_bus;
|
input drive_ad_bus;
|
input [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
input [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
input [3:0] num_waitstates;
|
input [3:0] num_waitstates;
|
begin
|
begin
|
for (cnt = 4'h0; cnt < num_waitstates[3:0]; cnt = cnt + 4'h1)
|
for (cnt = 4'h0; cnt < num_waitstates[3:0]; cnt = cnt + 4'h1)
|
begin
|
begin
|
if (~devsel_now & stop_now)
|
if (~devsel_now & stop_now)
|
begin
|
begin
|
cnt = num_waitstates[3:0]; // immediate exit on Target Abort
|
cnt = num_waitstates[3:0]; // immediate exit on Target Abort
|
end
|
end
|
else
|
else
|
begin
|
begin
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_WAIT_STATE_VALUE;
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_WAIT_STATE_VALUE;
|
master_ad_oe <= drive_ad_bus;
|
master_ad_oe <= drive_ad_bus;
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= master_mask_l[PCI_BUS_CBE_RANGE:0];
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= master_mask_l[PCI_BUS_CBE_RANGE:0];
|
master_cbe_oe <= 1'b1;
|
master_cbe_oe <= 1'b1;
|
master_debug_force_bad_par <= 1'b0;
|
master_debug_force_bad_par <= 1'b0;
|
master_got_master_abort <= 1'b0;
|
master_got_master_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_perr_check_next <= ~drive_ad_bus;
|
master_perr_check_next <= ~drive_ad_bus;
|
Assert_FRAME; // frame, but no action
|
Assert_FRAME; // frame, but no action
|
Deassert_IRDY;
|
Deassert_IRDY;
|
Inc_Master_Abort_Counter;
|
Inc_Master_Abort_Counter;
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
end
|
end
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
task Check_Target_Abort;
|
task Check_Target_Abort;
|
input got_target_abort;
|
input got_target_abort;
|
input [9:0] words_transferred;
|
input [9:0] words_transferred;
|
input [9:0] words_expected;
|
input [9:0] words_expected;
|
begin
|
begin
|
if (~got_target_abort)
|
if (~got_target_abort)
|
begin
|
begin
|
$display ("*** test master %h - Target Abort not received when expected, at %t",
|
$display ("*** test master %h - Target Abort not received when expected, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
else if (words_transferred[9:0] != words_expected[9:0])
|
else if (words_transferred[9:0] != words_expected[9:0])
|
begin
|
begin
|
$display ("*** test master %h - Target Abort received, but Word Count %d not %d, at %t",
|
$display ("*** test master %h - Target Abort received, but Word Count %d not %d, at %t",
|
test_device_id[2:0], words_transferred, words_expected, $time);
|
test_device_id[2:0], words_transferred, words_expected, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
endtask
|
endtask
|
|
|
task Check_Target_Retry;
|
task Check_Target_Retry;
|
input got_target_retry;
|
input got_target_retry;
|
input [9:0] words_transferred;
|
input [9:0] words_transferred;
|
input [9:0] words_expected;
|
input [9:0] words_expected;
|
begin
|
begin
|
if (~got_target_retry)
|
if (~got_target_retry)
|
begin
|
begin
|
$display ("*** test master %h - Target Retry not received when expected, at %t",
|
$display ("*** test master %h - Target Retry not received when expected, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
else if (words_transferred[9:0] != words_expected[9:0])
|
else if (words_transferred[9:0] != words_expected[9:0])
|
begin
|
begin
|
$display ("*** test master %h - Target Retry received, but Word Count %d not %d, at %t",
|
$display ("*** test master %h - Target Retry received, but Word Count %d not %d, at %t",
|
test_device_id[2:0], words_transferred, words_expected, $time);
|
test_device_id[2:0], words_transferred, words_expected, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
endtask
|
endtask
|
|
|
task Check_Target_Stop;
|
task Check_Target_Stop;
|
input got_target_stop;
|
input got_target_stop;
|
input [9:0] words_transferred;
|
input [9:0] words_transferred;
|
input [9:0] words_expected;
|
input [9:0] words_expected;
|
begin
|
begin
|
if (~got_target_stop)
|
if (~got_target_stop)
|
begin
|
begin
|
$display ("*** test master %h - Target Stop not received when expected, at %t",
|
$display ("*** test master %h - Target Stop not received when expected, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
else if (words_transferred[9:0] != words_expected[9:0])
|
else if (words_transferred[9:0] != words_expected[9:0])
|
begin
|
begin
|
$display ("*** test master %h - Target Stop received, but Word Count %d not %d, at %t",
|
$display ("*** test master %h - Target Stop received, but Word Count %d not %d, at %t",
|
test_device_id[2:0], words_transferred, words_expected, $time);
|
test_device_id[2:0], words_transferred, words_expected, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
endtask
|
endtask
|
|
|
// The initiator asked for a certain termination scheme. Did it do that?
|
// The initiator asked for a certain termination scheme. Did it do that?
|
task Check_Master_Burst_Termination_Cause;
|
task Check_Master_Burst_Termination_Cause;
|
input got_master_abort, got_master_terminate;
|
input got_master_abort, got_master_terminate;
|
input got_target_retry, got_target_stop, got_target_abort;
|
input got_target_retry, got_target_stop, got_target_abort;
|
input [9:0] words_transferred;
|
input [9:0] words_transferred;
|
begin
|
begin
|
if (~pci_reset_comb)
|
if (~pci_reset_comb)
|
begin
|
begin
|
// Check for Master Abort status
|
// Check for Master Abort status
|
if (~hold_master_expect_master_abort & got_master_abort)
|
if (~hold_master_expect_master_abort & got_master_abort)
|
begin
|
begin
|
$display ("*** test master %h - Master Abort received when none was expected, at %t",
|
$display ("*** test master %h - Master Abort received when none was expected, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (hold_master_expect_master_abort & ~got_master_abort)
|
if (hold_master_expect_master_abort & ~got_master_abort)
|
begin
|
begin
|
$display ("*** test master %h - Master Abort not received when expected, at %t",
|
$display ("*** test master %h - Master Abort not received when expected, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
// Check for Target Abort status
|
// Check for Target Abort status
|
if (hold_master_target_termination[2:0] == `Test_Target_Abort_On)
|
if (hold_master_target_termination[2:0] == `Test_Target_Abort_On)
|
Check_Target_Abort (got_target_abort, words_transferred[9:0], hold_master_size - 1);
|
Check_Target_Abort (got_target_abort, words_transferred[9:0], hold_master_size - 1);
|
|
|
if (hold_master_target_termination[2:0] == `Test_Target_Abort_Before)
|
if (hold_master_target_termination[2:0] == `Test_Target_Abort_Before)
|
begin
|
begin
|
if (hold_master_size[9:0] >= 10'h2) // too small, don't get a chance to do 2
|
if (hold_master_size[9:0] >= 10'h2) // too small, don't get a chance to do 2
|
begin
|
begin
|
Check_Target_Abort (got_target_abort, words_transferred[9:0], hold_master_size - 2);
|
Check_Target_Abort (got_target_abort, words_transferred[9:0], hold_master_size - 2);
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Check_Target_Stop (got_master_terminate,
|
Check_Target_Stop (got_master_terminate,
|
words_transferred[9:0], hold_master_size[9:0]);
|
words_transferred[9:0], hold_master_size[9:0]);
|
end
|
end
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
// Check for Target Retry status
|
// Check for Target Retry status
|
if (hold_master_target_termination[2:0] == `Test_Target_Retry_On)
|
if (hold_master_target_termination[2:0] == `Test_Target_Retry_On)
|
begin
|
begin
|
Check_Target_Retry (got_target_retry, words_transferred[9:0], hold_master_size - 1);
|
Check_Target_Retry (got_target_retry, words_transferred[9:0], hold_master_size - 1);
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
|
|
if (hold_master_target_termination[2:0] == `Test_Target_Retry_Before)
|
if (hold_master_target_termination[2:0] == `Test_Target_Retry_Before)
|
begin
|
begin
|
if (hold_master_size[9:0] >= 10'h2) // too small, don't get a chance to do 2
|
if (hold_master_size[9:0] >= 10'h2) // too small, don't get a chance to do 2
|
begin
|
begin
|
Check_Target_Retry (got_target_retry, words_transferred[9:0], hold_master_size - 2);
|
Check_Target_Retry (got_target_retry, words_transferred[9:0], hold_master_size - 2);
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Check_Target_Stop (got_master_terminate,
|
Check_Target_Stop (got_master_terminate,
|
words_transferred[9:0], hold_master_size[9:0]);
|
words_transferred[9:0], hold_master_size[9:0]);
|
end
|
end
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
// Check for Target Disconnect status
|
// Check for Target Disconnect status
|
if (hold_master_target_termination[2:0] == `Test_Target_Disc_On)
|
if (hold_master_target_termination[2:0] == `Test_Target_Disc_On)
|
begin
|
begin
|
Check_Target_Stop (got_target_stop, words_transferred[9:0], hold_master_size);
|
Check_Target_Stop (got_target_stop, words_transferred[9:0], hold_master_size);
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
|
|
if (hold_master_target_termination[2:0] == `Test_Target_Disc_Before)
|
if (hold_master_target_termination[2:0] == `Test_Target_Disc_Before)
|
begin
|
begin
|
if (hold_master_size[9:0] >= 10'h2) // too small, don't get a chance to do 2
|
if (hold_master_size[9:0] >= 10'h2) // too small, don't get a chance to do 2
|
begin
|
begin
|
Check_Target_Stop (got_target_stop, words_transferred[9:0], hold_master_size - 1);
|
Check_Target_Stop (got_target_stop, words_transferred[9:0], hold_master_size - 1);
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Check_Target_Stop (got_master_terminate,
|
Check_Target_Stop (got_master_terminate,
|
words_transferred[9:0], hold_master_size[9:0]);
|
words_transferred[9:0], hold_master_size[9:0]);
|
end
|
end
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
// Check for retry due to starting a delayed read
|
// Check for retry due to starting a delayed read
|
if (hold_master_target_termination[2:0] == `Test_Target_Start_Delayed_Read)
|
if (hold_master_target_termination[2:0] == `Test_Target_Start_Delayed_Read)
|
begin
|
begin
|
Check_Target_Retry (got_target_retry, words_transferred[9:0], 10'h0);
|
Check_Target_Retry (got_target_retry, words_transferred[9:0], 10'h0);
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
|
|
// Check for normal completion caused by the Master
|
// Check for normal completion caused by the Master
|
if ( (hold_master_target_termination[2:0] == `Test_Target_Normal_Completion)
|
if ( (hold_master_target_termination[2:0] == `Test_Target_Normal_Completion)
|
& ~hold_master_expect_master_abort )
|
& ~hold_master_expect_master_abort )
|
begin
|
begin
|
if (got_target_abort)
|
if (got_target_abort)
|
begin
|
begin
|
$display ("*** test master %h - Target Abort received when doing normal transfer, at %t",
|
$display ("*** test master %h - Target Abort received when doing normal transfer, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (got_target_retry)
|
if (got_target_retry)
|
begin
|
begin
|
$display ("*** test master %h - Target Retry received when doing normal transfer, at %t",
|
$display ("*** test master %h - Target Retry received when doing normal transfer, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (words_transferred[9:0] != hold_master_size[9:0])
|
if (words_transferred[9:0] != hold_master_size[9:0])
|
begin
|
begin
|
$display ("*** test master %h - Normal Transfer, but Word Count %d not %d, at %t",
|
$display ("*** test master %h - Normal Transfer, but Word Count %d not %d, at %t",
|
test_device_id[2:0], words_transferred, hold_master_size, $time);
|
test_device_id[2:0], words_transferred, hold_master_size, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
// Linger until DEVSEL.
|
// Linger until DEVSEL.
|
// Tasks can't have local storage! have to be module global
|
// Tasks can't have local storage! have to be module global
|
integer iii;
|
integer iii;
|
task Linger_Until_DEVSEL_Or_Master_Abort_Or_Target_Abort;
|
task Linger_Until_DEVSEL_Or_Master_Abort_Or_Target_Abort;
|
input drive_ad_bus;
|
input drive_ad_bus;
|
input [PCI_BUS_DATA_RANGE:0] master_write_data;
|
input [PCI_BUS_DATA_RANGE:0] master_write_data;
|
input [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
input [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
input do_master_terminate;
|
input do_master_terminate;
|
output got_master_abort;
|
output got_master_abort;
|
begin
|
begin
|
`ifdef VERBOSE_TEST_DEVICE
|
`ifdef VERBOSE_TEST_DEVICE
|
$display (" test %h - Lingering waiting for DEVSEL, at %t",
|
$display (" test %h - Lingering waiting for DEVSEL, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
`endif // VERBOSE_TEST_DEVICE
|
`endif // VERBOSE_TEST_DEVICE
|
for (iii = 0; iii < TEST_MASTER_SPINLOOP_MAX; iii = iii + 1)
|
for (iii = 0; iii < TEST_MASTER_SPINLOOP_MAX; iii = iii + 1)
|
begin
|
begin
|
if (~devsel_now) // no master yet
|
if (~devsel_now) // no master yet
|
begin
|
begin
|
if (stop_now) // target abort!
|
if (stop_now) // target abort!
|
begin
|
begin
|
iii = TEST_MASTER_SPINLOOP_MAX + 1; // break
|
iii = TEST_MASTER_SPINLOOP_MAX + 1; // break
|
got_master_abort = 1'b0; // target abort handled before master abort
|
got_master_abort = 1'b0; // target abort handled before master abort
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Check_Master_Abort_Counter (got_master_abort);
|
Check_Master_Abort_Counter (got_master_abort);
|
if (got_master_abort) // immediate exit on master abort
|
if (got_master_abort) // immediate exit on master abort
|
begin
|
begin
|
iii = TEST_MASTER_SPINLOOP_MAX + 1; // break
|
iii = TEST_MASTER_SPINLOOP_MAX + 1; // break
|
end
|
end
|
else
|
else
|
begin
|
begin
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= master_write_data[PCI_BUS_DATA_RANGE:0];
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= master_write_data[PCI_BUS_DATA_RANGE:0];
|
master_ad_oe <= drive_ad_bus;
|
master_ad_oe <= drive_ad_bus;
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= master_mask_l[PCI_BUS_CBE_RANGE:0];
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= master_mask_l[PCI_BUS_CBE_RANGE:0];
|
master_cbe_oe <= 1'b1;
|
master_cbe_oe <= 1'b1;
|
master_debug_force_bad_par <= hold_master_data_par_err;
|
master_debug_force_bad_par <= hold_master_data_par_err;
|
master_got_master_abort <= 1'b0;
|
master_got_master_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_perr_check_next <= ~drive_ad_bus;
|
master_perr_check_next <= ~drive_ad_bus;
|
Assert_Master_Continue_Or_Terminate (do_master_terminate);
|
Assert_Master_Continue_Or_Terminate (do_master_terminate);
|
Inc_Master_Abort_Counter;
|
Inc_Master_Abort_Counter;
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
end
|
end
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
iii = TEST_MASTER_SPINLOOP_MAX + 1; // break
|
iii = TEST_MASTER_SPINLOOP_MAX + 1; // break
|
got_master_abort = 1'b0; // success
|
got_master_abort = 1'b0; // success
|
end
|
end
|
end
|
end
|
if (iii == TEST_MASTER_SPINLOOP_MAX)
|
if (iii == TEST_MASTER_SPINLOOP_MAX)
|
begin
|
begin
|
got_master_abort = 1'b1; // fail if fall off end
|
got_master_abort = 1'b1; // fail if fall off end
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
`ifdef NORMAL_PCI_CHECKS
|
`ifdef NORMAL_PCI_CHECKS
|
if (~pci_reset_comb & (iii == TEST_MASTER_SPINLOOP_MAX))
|
if (~pci_reset_comb & (iii == TEST_MASTER_SPINLOOP_MAX))
|
begin
|
begin
|
$display ("*** test master %h - Bus didn't get DEVSEL during Master ref, at %t",
|
$display ("*** test master %h - Bus didn't get DEVSEL during Master ref, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
`endif // NORMAL_PCI_CHECKS
|
`endif // NORMAL_PCI_CHECKS
|
end
|
end
|
endtask
|
endtask
|
|
|
// Linger until TRDY or STOP are asserted.
|
// Linger until TRDY or STOP are asserted.
|
// Tasks can't have local storage! have to be module global
|
// Tasks can't have local storage! have to be module global
|
integer iiii;
|
integer iiii;
|
task Linger_Until_Target_Waitstates_Done;
|
task Linger_Until_Target_Waitstates_Done;
|
input drive_ad_bus;
|
input drive_ad_bus;
|
input [PCI_BUS_DATA_RANGE:0] master_write_data;
|
input [PCI_BUS_DATA_RANGE:0] master_write_data;
|
input [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
input [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
input do_master_terminate;
|
input do_master_terminate;
|
begin
|
begin
|
for (iiii = 0; iiii < TEST_MASTER_SPINLOOP_MAX; iiii = iiii + 1)
|
for (iiii = 0; iiii < TEST_MASTER_SPINLOOP_MAX; iiii = iiii + 1)
|
begin
|
begin
|
if (~trdy_now & ~stop_now) // stick in master wait states
|
if (~trdy_now & ~stop_now) // stick in master wait states
|
begin
|
begin
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= master_write_data[PCI_BUS_DATA_RANGE:0];
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= master_write_data[PCI_BUS_DATA_RANGE:0];
|
master_ad_oe <= drive_ad_bus;
|
master_ad_oe <= drive_ad_bus;
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= master_mask_l[PCI_BUS_CBE_RANGE:0];
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= master_mask_l[PCI_BUS_CBE_RANGE:0];
|
master_cbe_oe <= 1'b1;
|
master_cbe_oe <= 1'b1;
|
master_debug_force_bad_par <= hold_master_data_par_err;
|
master_debug_force_bad_par <= hold_master_data_par_err;
|
master_got_master_abort <= 1'b0;
|
master_got_master_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_perr_check_next <= ~drive_ad_bus;
|
master_perr_check_next <= ~drive_ad_bus;
|
Assert_Master_Continue_Or_Terminate (do_master_terminate);
|
Assert_Master_Continue_Or_Terminate (do_master_terminate);
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
end
|
end
|
else
|
else
|
begin
|
begin
|
iiii = TEST_MASTER_SPINLOOP_MAX + 1; // break
|
iiii = TEST_MASTER_SPINLOOP_MAX + 1; // break
|
end
|
end
|
end
|
end
|
`ifdef NORMAL_PCI_CHECKS
|
`ifdef NORMAL_PCI_CHECKS
|
if (~pci_reset_comb & (iiii == TEST_MASTER_SPINLOOP_MAX))
|
if (~pci_reset_comb & (iiii == TEST_MASTER_SPINLOOP_MAX))
|
begin
|
begin
|
$display ("*** test master %h - Bus didn't get DEVSEL during Master ref, at %t",
|
$display ("*** test master %h - Bus didn't get DEVSEL during Master ref, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
`endif // NORMAL_PCI_CHECKS
|
`endif // NORMAL_PCI_CHECKS
|
end
|
end
|
endtask
|
endtask
|
|
|
// Transfer a word with or without target termination, and act on Master Termination
|
// Transfer a word with or without target termination, and act on Master Termination
|
// This task MIGHT be entered when DEVSEL is Deasserted and STOP is Asserted!
|
// This task MIGHT be entered when DEVSEL is Deasserted and STOP is Asserted!
|
// Handle this Target Abort if it occurs.
|
// Handle this Target Abort if it occurs.
|
task Execute_Master_Ref_Undrive_All_In_Any_Termination_Unless_Fast_B2B;
|
task Execute_Master_Ref_Undrive_All_In_Any_Termination_Unless_Fast_B2B;
|
input drive_ad_bus;
|
input drive_ad_bus;
|
input watching_for_master_abort;
|
input watching_for_master_abort;
|
input do_master_terminate;
|
input do_master_terminate;
|
input enable_fast_back_to_back;
|
input enable_fast_back_to_back;
|
input [PCI_BUS_DATA_RANGE:0] master_write_data;
|
input [PCI_BUS_DATA_RANGE:0] master_write_data;
|
input [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
input [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
output [PCI_BUS_DATA_RANGE:0] target_read_data;
|
output [PCI_BUS_DATA_RANGE:0] target_read_data;
|
output got_master_abort, got_target_retry, got_target_stop, got_target_abort;
|
output got_master_abort, got_target_retry, got_target_stop, got_target_abort;
|
output want_fast_back_to_back;
|
output want_fast_back_to_back;
|
begin
|
begin
|
if (~devsel_now & stop_now)
|
if (~devsel_now & stop_now)
|
begin // Target Abort.
|
begin // Target Abort.
|
got_master_abort = 1'b0;
|
got_master_abort = 1'b0;
|
got_target_retry = 1'b0; got_target_stop = 1'b0; got_target_abort = 1'b1;
|
got_target_retry = 1'b0; got_target_stop = 1'b0; got_target_abort = 1'b1;
|
do_master_terminate = 1'b0; // force clean termination activity as if master abort
|
do_master_terminate = 1'b0; // force clean termination activity as if master abort
|
end
|
end
|
else
|
else
|
begin
|
begin
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= master_write_data[PCI_BUS_DATA_RANGE:0];
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= master_write_data[PCI_BUS_DATA_RANGE:0];
|
master_ad_oe <= drive_ad_bus;
|
master_ad_oe <= drive_ad_bus;
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= master_mask_l[PCI_BUS_CBE_RANGE:0];
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= master_mask_l[PCI_BUS_CBE_RANGE:0];
|
master_cbe_oe <= 1'b1;
|
master_cbe_oe <= 1'b1;
|
master_debug_force_bad_par <= hold_master_data_par_err;
|
master_debug_force_bad_par <= hold_master_data_par_err;
|
master_got_master_abort <= 1'b0;
|
master_got_master_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_perr_check_next <= ~drive_ad_bus;
|
master_perr_check_next <= ~drive_ad_bus;
|
Assert_Master_Continue_Or_Terminate (do_master_terminate);
|
Assert_Master_Continue_Or_Terminate (do_master_terminate);
|
Inc_Master_Abort_Counter;
|
Inc_Master_Abort_Counter;
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
if (watching_for_master_abort)
|
if (watching_for_master_abort)
|
begin
|
begin
|
Linger_Until_DEVSEL_Or_Master_Abort_Or_Target_Abort (drive_ad_bus,
|
Linger_Until_DEVSEL_Or_Master_Abort_Or_Target_Abort (drive_ad_bus,
|
master_write_data[PCI_BUS_DATA_RANGE:0],
|
master_write_data[PCI_BUS_DATA_RANGE:0],
|
master_mask_l[PCI_BUS_CBE_RANGE:0],
|
master_mask_l[PCI_BUS_CBE_RANGE:0],
|
do_master_terminate, got_master_abort);
|
do_master_terminate, got_master_abort);
|
end
|
end
|
else
|
else
|
begin
|
begin
|
got_master_abort = 1'b0;
|
got_master_abort = 1'b0;
|
end
|
end
|
if (got_master_abort)
|
if (got_master_abort)
|
begin
|
begin
|
got_target_retry = 1'b0; got_target_stop = 1'b0; got_target_abort = 1'b0;
|
got_target_retry = 1'b0; got_target_stop = 1'b0; got_target_abort = 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Linger_Until_Target_Waitstates_Done (drive_ad_bus,
|
Linger_Until_Target_Waitstates_Done (drive_ad_bus,
|
master_write_data[PCI_BUS_DATA_RANGE:0],
|
master_write_data[PCI_BUS_DATA_RANGE:0],
|
master_mask_l[PCI_BUS_CBE_RANGE:0],
|
master_mask_l[PCI_BUS_CBE_RANGE:0],
|
do_master_terminate);
|
do_master_terminate);
|
target_read_data[PCI_BUS_DATA_RANGE:0] = ad_now[PCI_BUS_DATA_RANGE:0]; // unconditionally grab.
|
target_read_data[PCI_BUS_DATA_RANGE:0] = ad_now[PCI_BUS_DATA_RANGE:0]; // unconditionally grab.
|
if (~devsel_now & stop_now)
|
if (~devsel_now & stop_now)
|
begin
|
begin
|
got_target_retry = 1'b0; got_target_stop = 1'b0; got_target_abort = 1'b1;
|
got_target_retry = 1'b0; got_target_stop = 1'b0; got_target_abort = 1'b1;
|
end
|
end
|
else if (devsel_now & trdy_now & stop_now)
|
else if (devsel_now & trdy_now & stop_now)
|
begin
|
begin
|
got_target_retry = 1'b0; got_target_stop = 1'b1; got_target_abort = 1'b0;
|
got_target_retry = 1'b0; got_target_stop = 1'b1; got_target_abort = 1'b0;
|
end
|
end
|
else if (devsel_now & ~trdy_now & stop_now)
|
else if (devsel_now & ~trdy_now & stop_now)
|
begin
|
begin
|
got_target_retry = 1'b1; got_target_stop = 1'b0; got_target_abort = 1'b0;
|
got_target_retry = 1'b1; got_target_stop = 1'b0; got_target_abort = 1'b0;
|
end
|
end
|
else if (devsel_now & trdy_now & ~stop_now)
|
else if (devsel_now & trdy_now & ~stop_now)
|
begin
|
begin
|
got_target_retry = 1'b0; got_target_stop = 1'b0; got_target_abort = 1'b0;
|
got_target_retry = 1'b0; got_target_stop = 1'b0; got_target_abort = 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (~pci_reset_comb)
|
if (~pci_reset_comb)
|
begin
|
begin
|
$display ("*** test %h - Master got unexpected Target Handshake Signals, at %t",
|
$display ("*** test %h - Master got unexpected Target Handshake Signals, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
got_target_retry = 1'b0; got_target_stop = 1'b0; got_target_abort = 1'b1;
|
got_target_retry = 1'b0; got_target_stop = 1'b0; got_target_abort = 1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
if ((got_master_abort | got_target_retry | got_target_stop | got_target_abort)
|
if ((got_master_abort | got_target_retry | got_target_stop | got_target_abort)
|
& ~do_master_terminate) // If not do_master_terminate, FRAME still asserted
|
& ~do_master_terminate) // If not do_master_terminate, FRAME still asserted
|
begin // turn-around cycle on FRAME
|
begin // turn-around cycle on FRAME
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= master_write_data[PCI_BUS_DATA_RANGE:0];
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= master_write_data[PCI_BUS_DATA_RANGE:0];
|
master_ad_oe <= drive_ad_bus;
|
master_ad_oe <= drive_ad_bus;
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= master_mask_l[PCI_BUS_CBE_RANGE:0];
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= master_mask_l[PCI_BUS_CBE_RANGE:0];
|
master_cbe_oe <= 1'b1;
|
master_cbe_oe <= 1'b1;
|
master_debug_force_bad_par <= hold_master_data_par_err;
|
master_debug_force_bad_par <= hold_master_data_par_err;
|
master_got_master_abort <= 1'b0;
|
master_got_master_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_perr_check_next <= ~drive_ad_bus;
|
master_perr_check_next <= ~drive_ad_bus;
|
Deassert_FRAME; // do the work that master_terminate would have already done
|
Deassert_FRAME; // do the work that master_terminate would have already done
|
Assert_IRDY;
|
Assert_IRDY;
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
end
|
end
|
if (got_master_abort | got_target_retry | got_target_stop | got_target_abort
|
if (got_master_abort | got_target_retry | got_target_stop | got_target_abort
|
| do_master_terminate) // If do_master_terminate, FRAME already deasserted
|
| do_master_terminate) // If do_master_terminate, FRAME already deasserted
|
begin
|
begin
|
// If doing immediate Address phase due to fast back-to-back, don't drive bus here
|
// If doing immediate Address phase due to fast back-to-back, don't drive bus here
|
// Extremely subtle point.
|
// Extremely subtle point.
|
// Cannot do a fast back-to-back transfer if Address Lines are being stepped!
|
// Cannot do a fast back-to-back transfer if Address Lines are being stepped!
|
// Fast-Back-To-Back only works if the device is able to grab the bus the next cycle.
|
// Fast-Back-To-Back only works if the device is able to grab the bus the next cycle.
|
// It must do this because the PCI Arbiter thinks the bus is busy, and might grant
|
// It must do this because the PCI Arbiter thinks the bus is busy, and might grant
|
// mastership to another party without a wait state assuming that an idle state
|
// mastership to another party without a wait state assuming that an idle state
|
// must be inserted by the present device before it re-drives the bus.
|
// must be inserted by the present device before it re-drives the bus.
|
// The other party will drive the bus the next clock if it does NOT see FRAME
|
// The other party will drive the bus the next clock if it does NOT see FRAME
|
// asserted now. Frame will always be delayed by address-stepping devices.
|
// asserted now. Frame will always be delayed by address-stepping devices.
|
// See the PCI Local Bus Spec Revision 2.2 section 3.4.1 and 3.4.2.
|
// See the PCI Local Bus Spec Revision 2.2 section 3.4.1 and 3.4.2.
|
// no fast B2B if master or target abort, to give time to report error to Config Reg
|
// no fast B2B if master or target abort, to give time to report error to Config Reg
|
if (~got_master_abort & ~got_target_abort
|
if (~got_master_abort & ~got_target_abort
|
& master_gnt_now & enable_fast_back_to_back & master_fast_b2b_en
|
& master_gnt_now & enable_fast_back_to_back & master_fast_b2b_en
|
& This_Master_Drove_The_AD_Bus_The_Last_Clock
|
& This_Master_Drove_The_AD_Bus_The_Last_Clock
|
& test_start & (test_master_number[2:0] == test_device_id[2:0])
|
& test_start & (test_master_number[2:0] == test_device_id[2:0])
|
& ( (test_command[3:0] != PCI_COMMAND_CONFIG_READ)
|
& ( (test_command[3:0] != PCI_COMMAND_CONFIG_READ)
|
& (test_command[3:0] != PCI_COMMAND_CONFIG_WRITE) ) )
|
& (test_command[3:0] != PCI_COMMAND_CONFIG_WRITE) ) )
|
begin
|
begin
|
want_fast_back_to_back = 1'b1;
|
want_fast_back_to_back = 1'b1;
|
// No clock here to let the next command dispatch quickly. The dispatcher has a wait
|
// No clock here to let the next command dispatch quickly. The dispatcher has a wait
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// Otherwise enforce an idle state
|
// Otherwise enforce an idle state
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
|
master_ad_oe <= 1'b0;
|
master_ad_oe <= 1'b0;
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4; // easy to see
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4; // easy to see
|
master_cbe_oe <= 1'b0;
|
master_cbe_oe <= 1'b0;
|
master_debug_force_bad_par <= 1'b0;
|
master_debug_force_bad_par <= 1'b0;
|
master_got_master_abort <= got_master_abort;
|
master_got_master_abort <= got_master_abort;
|
master_got_target_abort <= got_target_abort;
|
master_got_target_abort <= got_target_abort;
|
master_got_target_retry <= got_target_retry;
|
master_got_target_retry <= got_target_retry;
|
master_perr_check_next <= 1'b0;
|
master_perr_check_next <= 1'b0;
|
Deassert_FRAME;
|
Deassert_FRAME;
|
Deassert_IRDY;
|
Deassert_IRDY;
|
want_fast_back_to_back = 1'b0;
|
want_fast_back_to_back = 1'b0;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
want_fast_back_to_back = 1'b0;
|
want_fast_back_to_back = 1'b0;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
parameter TEST_MASTER_DOING_CONFIG_READ = 3'b000;
|
parameter TEST_MASTER_DOING_CONFIG_READ = 3'b000;
|
parameter TEST_MASTER_DOING_CONFIG_WRITE = 3'b001;
|
parameter TEST_MASTER_DOING_CONFIG_WRITE = 3'b001;
|
parameter TEST_MASTER_DOING_MEM_READ = 3'b010;
|
parameter TEST_MASTER_DOING_MEM_READ = 3'b010;
|
parameter TEST_MASTER_DOING_MEM_WRITE = 3'b011;
|
parameter TEST_MASTER_DOING_MEM_WRITE = 3'b011;
|
parameter TEST_MASTER_DOING_MEM_READ_LN = 3'b100; // Added by Tadej M., 06.12.2001
|
parameter TEST_MASTER_DOING_MEM_READ_LN = 3'b100; // Added by Tadej M., 06.12.2001
|
parameter TEST_MASTER_DOING_MEM_READ_MUL = 3'b110; // Added by Tadej M., 06.12.2001
|
parameter TEST_MASTER_DOING_MEM_READ_MUL = 3'b110; // Added by Tadej M., 06.12.2001
|
|
|
task Report_On_Master_PCI_Ref_Start;
|
task Report_On_Master_PCI_Ref_Start;
|
input [2:0] reference_type;
|
input [2:0] reference_type;
|
begin
|
begin
|
case (reference_type[2:0])
|
case (reference_type[2:0])
|
TEST_MASTER_DOING_CONFIG_READ:
|
TEST_MASTER_DOING_CONFIG_READ:
|
$display (" test master %h - Starting Config Read, at %t",
|
$display (" test master %h - Starting Config Read, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
TEST_MASTER_DOING_CONFIG_WRITE:
|
TEST_MASTER_DOING_CONFIG_WRITE:
|
$display (" test master %h - Starting Config Write, at %t",
|
$display (" test master %h - Starting Config Write, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
TEST_MASTER_DOING_MEM_READ:
|
TEST_MASTER_DOING_MEM_READ:
|
$display (" test master %h - Starting Memory Read, at %t",
|
$display (" test master %h - Starting Memory Read, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
TEST_MASTER_DOING_MEM_WRITE:
|
TEST_MASTER_DOING_MEM_WRITE:
|
$display (" test master %h - Starting Memory Write, at %t",
|
$display (" test master %h - Starting Memory Write, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
TEST_MASTER_DOING_MEM_READ_LN:
|
TEST_MASTER_DOING_MEM_READ_LN:
|
$display (" test master %h - Starting Memory Read Line, at %t",
|
$display (" test master %h - Starting Memory Read Line, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
TEST_MASTER_DOING_MEM_READ_MUL:
|
TEST_MASTER_DOING_MEM_READ_MUL:
|
$display (" test master %h - Starting Memory Read Line Multiple, at %t",
|
$display (" test master %h - Starting Memory Read Line Multiple, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
default:
|
default:
|
$display (" test master %h - Doing Unknown Reference, at %t",
|
$display (" test master %h - Doing Unknown Reference, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
endcase
|
endcase
|
`ifdef VERBOSE_TEST_DEVICE
|
`ifdef VERBOSE_TEST_DEVICE
|
Report_Master_Reference_Paramaters;
|
Report_Master_Reference_Paramaters;
|
`endif // VERBOSE_TEST_DEVICE
|
`endif // VERBOSE_TEST_DEVICE
|
end
|
end
|
endtask
|
endtask
|
|
|
task Report_On_Master_PCI_Ref_Finish;
|
task Report_On_Master_PCI_Ref_Finish;
|
input got_master_abort;
|
input got_master_abort;
|
input got_target_abort;
|
input got_target_abort;
|
input got_target_retry;
|
input got_target_retry;
|
input got_target_stop;
|
input got_target_stop;
|
input [9:0] words_transferred;
|
input [9:0] words_transferred;
|
begin
|
begin
|
if (got_master_abort)
|
if (got_master_abort)
|
begin
|
begin
|
$display (" test master %h - Got Master Abort, at %t",
|
$display (" test master %h - Got Master Abort, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (got_target_abort)
|
if (got_target_abort)
|
begin
|
begin
|
$display (" test master %h - Got Target Abort, at %t",
|
$display (" test master %h - Got Target Abort, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (got_target_retry)
|
if (got_target_retry)
|
begin
|
begin
|
$display (" test master %h - Got Target Retry, at %t",
|
$display (" test master %h - Got Target Retry, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (got_target_stop)
|
if (got_target_stop)
|
begin
|
begin
|
$display (" test master %h - Got Target Stop, at %t",
|
$display (" test master %h - Got Target Stop, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (~got_master_abort & ~got_target_abort & ~got_target_retry & ~got_target_stop)
|
if (~got_master_abort & ~got_target_abort & ~got_target_retry & ~got_target_stop)
|
begin
|
begin
|
$display (" test master %h - Normal Success, at %t",
|
$display (" test master %h - Normal Success, at %t",
|
test_device_id[2:0], $time);
|
test_device_id[2:0], $time);
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (words_transferred != 10'h0)
|
if (words_transferred != 10'h0)
|
begin
|
begin
|
$display (" test master %h - Transferred %h words, at %t",
|
$display (" test master %h - Transferred %h words, at %t",
|
test_device_id[2:0], words_transferred[9:0], $time);
|
test_device_id[2:0], words_transferred[9:0], $time);
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
endtask
|
endtask
|
|
|
// Tasks can't have local storage! have to be module global
|
// Tasks can't have local storage! have to be module global
|
reg step_address;
|
reg step_address;
|
reg [3:0] wait_states_this_time;
|
reg [3:0] wait_states_this_time;
|
reg [9:0] words_transferred;
|
reg [9:0] words_transferred;
|
reg drive_ad_bus, watching_for_master_abort, do_master_terminate_this_time;
|
reg drive_ad_bus, watching_for_master_abort, do_master_terminate_this_time;
|
reg [PCI_BUS_DATA_RANGE:0] target_read_data;
|
reg [PCI_BUS_DATA_RANGE:0] target_read_data;
|
reg [PCI_BUS_DATA_RANGE:0] master_write_data;
|
reg [PCI_BUS_DATA_RANGE:0] master_write_data;
|
reg [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
reg [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
reg [PCI_BUS_DATA_RANGE:0] master_write_data_next;
|
reg [PCI_BUS_DATA_RANGE:0] master_write_data_next;
|
reg [PCI_BUS_CBE_RANGE:0] master_mask_l_next;
|
reg [PCI_BUS_CBE_RANGE:0] master_mask_l_next;
|
reg got_master_abort, got_target_retry, got_target_stop, got_target_abort;
|
reg got_master_abort, got_target_retry, got_target_stop, got_target_abort;
|
reg got_master_terminate;
|
reg got_master_terminate;
|
task Execute_Master_PCI_Ref;
|
task Execute_Master_PCI_Ref;
|
input [2:0] reference_type;
|
input [2:0] reference_type;
|
output want_fast_back_to_back;
|
output want_fast_back_to_back;
|
begin
|
begin
|
Master_Req_Bus;
|
Master_Req_Bus;
|
if ( (reference_type[2:0] == TEST_MASTER_DOING_CONFIG_READ)
|
if ( (reference_type[2:0] == TEST_MASTER_DOING_CONFIG_READ)
|
| (reference_type[2:0] == TEST_MASTER_DOING_CONFIG_WRITE) )
|
| (reference_type[2:0] == TEST_MASTER_DOING_CONFIG_WRITE) )
|
begin
|
begin
|
step_address = TEST_MASTER_STEP_ADDRESS;
|
step_address = TEST_MASTER_STEP_ADDRESS;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
step_address = TEST_MASTER_IMMEDIATE_ADDRESS;
|
step_address = TEST_MASTER_IMMEDIATE_ADDRESS;
|
end
|
end
|
Master_Assert_Address (modified_master_address[PCI_BUS_DATA_RANGE:0],
|
Master_Assert_Address (modified_master_address[PCI_BUS_DATA_RANGE:0],
|
hold_master_command[PCI_BUS_CBE_RANGE:0],
|
hold_master_command[PCI_BUS_CBE_RANGE:0],
|
step_address, hold_master_fast_b2b, hold_master_addr_par_err);
|
step_address, hold_master_fast_b2b, hold_master_addr_par_err);
|
Master_Unreq_Bus; // After FRAME is asserted!
|
Master_Unreq_Bus; // After FRAME is asserted!
|
`ifdef REPORT_TEST_DEVICE
|
`ifdef REPORT_TEST_DEVICE
|
// Do Report after Address to let the time of the report line up with the bus event.
|
// Do Report after Address to let the time of the report line up with the bus event.
|
Report_On_Master_PCI_Ref_Start (reference_type[2:0]);
|
Report_On_Master_PCI_Ref_Start (reference_type[2:0]);
|
`endif // REPORT_TEST_DEVICE
|
`endif // REPORT_TEST_DEVICE
|
drive_ad_bus = (reference_type[2:0] == TEST_MASTER_DOING_CONFIG_WRITE)
|
drive_ad_bus = (reference_type[2:0] == TEST_MASTER_DOING_CONFIG_WRITE)
|
| (reference_type[2:0] == TEST_MASTER_DOING_MEM_WRITE);
|
| (reference_type[2:0] == TEST_MASTER_DOING_MEM_WRITE);
|
words_transferred = 9'h0;
|
words_transferred = 9'h0;
|
wait_states_this_time = hold_master_initial_waitstates[3:0];
|
wait_states_this_time = hold_master_initial_waitstates[3:0];
|
do_master_terminate_this_time =
|
do_master_terminate_this_time =
|
((words_transferred[9:0] + 4'h1) == hold_master_size[9:0]);
|
((words_transferred[9:0] + 4'h1) == hold_master_size[9:0]);
|
watching_for_master_abort = 1'b1;
|
watching_for_master_abort = 1'b1;
|
master_write_data[PCI_BUS_DATA_RANGE:0] = hold_master_data[PCI_BUS_DATA_RANGE:0];
|
master_write_data[PCI_BUS_DATA_RANGE:0] = hold_master_data[PCI_BUS_DATA_RANGE:0];
|
master_mask_l[PCI_BUS_CBE_RANGE:0] = hold_master_byte_enables_l[PCI_BUS_CBE_RANGE:0];
|
master_mask_l[PCI_BUS_CBE_RANGE:0] = hold_master_byte_enables_l[PCI_BUS_CBE_RANGE:0];
|
got_master_abort = 1'b0;
|
got_master_abort = 1'b0;
|
got_target_retry = 1'b0;
|
got_target_retry = 1'b0;
|
got_target_stop = 1'b0;
|
got_target_stop = 1'b0;
|
got_target_abort = 1'b0;
|
got_target_abort = 1'b0;
|
got_master_terminate = 1'b0;
|
got_master_terminate = 1'b0;
|
while ( ~got_master_abort & ~got_target_retry & ~got_target_stop
|
while ( ~got_master_abort & ~got_target_retry & ~got_target_stop
|
& ~got_target_abort & ~got_master_terminate)
|
& ~got_target_abort & ~got_master_terminate)
|
begin
|
begin
|
Execute_Master_Waitstates_But_Quit_On_Target_Abort (drive_ad_bus,
|
Execute_Master_Waitstates_But_Quit_On_Target_Abort (drive_ad_bus,
|
master_mask_l[3:0], wait_states_this_time[3:0]);
|
master_mask_l[3:0], wait_states_this_time[3:0]);
|
Execute_Master_Ref_Undrive_All_In_Any_Termination_Unless_Fast_B2B (drive_ad_bus,
|
Execute_Master_Ref_Undrive_All_In_Any_Termination_Unless_Fast_B2B (drive_ad_bus,
|
watching_for_master_abort, do_master_terminate_this_time,
|
watching_for_master_abort, do_master_terminate_this_time,
|
hold_master_fast_b2b, master_write_data[PCI_BUS_DATA_RANGE:0],
|
hold_master_fast_b2b, master_write_data[PCI_BUS_DATA_RANGE:0],
|
master_mask_l[PCI_BUS_CBE_RANGE:0],
|
master_mask_l[PCI_BUS_CBE_RANGE:0],
|
target_read_data[PCI_BUS_DATA_RANGE:0],
|
target_read_data[PCI_BUS_DATA_RANGE:0],
|
got_master_abort, got_target_retry,
|
got_master_abort, got_target_retry,
|
got_target_stop, got_target_abort,
|
got_target_stop, got_target_abort,
|
want_fast_back_to_back);
|
want_fast_back_to_back);
|
got_master_terminate = do_master_terminate_this_time;
|
got_master_terminate = do_master_terminate_this_time;
|
if (~got_master_abort & ~got_target_retry & ~got_target_abort)
|
if (~got_master_abort & ~got_target_retry & ~got_target_abort)
|
begin
|
begin
|
if (~drive_ad_bus)
|
if (~drive_ad_bus)
|
begin
|
begin
|
if ( master_check_received_data )
|
if ( master_check_received_data )
|
Compare_Read_Data_With_Expected_Data (target_read_data[PCI_BUS_DATA_RANGE:0],
|
Compare_Read_Data_With_Expected_Data (target_read_data[PCI_BUS_DATA_RANGE:0],
|
master_write_data[PCI_BUS_DATA_RANGE:0],
|
master_write_data[PCI_BUS_DATA_RANGE:0],
|
master_mask_l[PCI_BUS_CBE_RANGE:0]);
|
master_mask_l[PCI_BUS_CBE_RANGE:0]);
|
|
|
master_received_data = target_read_data ;
|
master_received_data = target_read_data ;
|
master_received_data_valid <= ~master_received_data_valid ;
|
master_received_data_valid <= ~master_received_data_valid ;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
wait_states_this_time = hold_master_subsequent_waitstates[3:0];
|
wait_states_this_time = hold_master_subsequent_waitstates[3:0];
|
words_transferred = words_transferred + 10'b1;
|
words_transferred = words_transferred + 10'b1;
|
do_master_terminate_this_time =
|
do_master_terminate_this_time =
|
((words_transferred[9:0] + 4'h1) == hold_master_size[9:0]);
|
((words_transferred[9:0] + 4'h1) == hold_master_size[9:0]);
|
watching_for_master_abort = 1'b0;
|
watching_for_master_abort = 1'b0;
|
Update_Write_Data (master_write_data[PCI_BUS_DATA_RANGE:0],
|
Update_Write_Data (master_write_data[PCI_BUS_DATA_RANGE:0],
|
master_mask_l[PCI_BUS_CBE_RANGE:0],
|
master_mask_l[PCI_BUS_CBE_RANGE:0],
|
master_write_data_next[PCI_BUS_DATA_RANGE:0],
|
master_write_data_next[PCI_BUS_DATA_RANGE:0],
|
master_mask_l_next[PCI_BUS_CBE_RANGE:0]);
|
master_mask_l_next[PCI_BUS_CBE_RANGE:0]);
|
master_write_data[PCI_BUS_DATA_RANGE:0] = master_write_data_next[PCI_BUS_DATA_RANGE:0];
|
master_write_data[PCI_BUS_DATA_RANGE:0] = master_write_data_next[PCI_BUS_DATA_RANGE:0];
|
master_mask_l[PCI_BUS_CBE_RANGE:0] = master_mask_l_next[PCI_BUS_CBE_RANGE:0];
|
master_mask_l[PCI_BUS_CBE_RANGE:0] = master_mask_l_next[PCI_BUS_CBE_RANGE:0];
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
`ifdef NORMAL_PCI_CHECKS
|
`ifdef NORMAL_PCI_CHECKS
|
Check_Master_Burst_Termination_Cause (got_master_abort, got_master_terminate,
|
Check_Master_Burst_Termination_Cause (got_master_abort, got_master_terminate,
|
got_target_retry, got_target_stop, got_target_abort,
|
got_target_retry, got_target_stop, got_target_abort,
|
words_transferred[9:0]);
|
words_transferred[9:0]);
|
`endif // NORMAL_PCI_CHECKS
|
`endif // NORMAL_PCI_CHECKS
|
`ifdef VERBOSE_TEST_DEVICE
|
`ifdef VERBOSE_TEST_DEVICE
|
Report_On_Master_PCI_Ref_Finish (got_master_abort, got_target_abort,
|
Report_On_Master_PCI_Ref_Finish (got_master_abort, got_target_abort,
|
got_target_retry, got_target_stop,
|
got_target_retry, got_target_stop,
|
words_transferred[9:0]);
|
words_transferred[9:0]);
|
`endif // VERBOSE_TEST_DEVICE
|
`endif // VERBOSE_TEST_DEVICE
|
end
|
end
|
endtask
|
endtask
|
|
|
// Task to print debug info
|
// Task to print debug info
|
// NOTE This must change if bit allocation changes
|
// NOTE This must change if bit allocation changes
|
task Report_Master_Reference_Paramaters;
|
task Report_Master_Reference_Paramaters;
|
begin
|
begin
|
if (hold_master_address[23:9] != 15'h0000)
|
if (hold_master_address[23:9] != 15'h0000)
|
begin
|
begin
|
// hold_master_address, hold_master_command, hold_master_data,
|
// hold_master_address, hold_master_command, hold_master_data,
|
// hold_master_byte_enables_l, hold_master_size
|
// hold_master_byte_enables_l, hold_master_size
|
$display (" First Master Data Wait States %h, Subsequent Master Data Wait States %h",
|
$display (" First Master Data Wait States %h, Subsequent Master Data Wait States %h",
|
hold_master_initial_waitstates[3:0],
|
hold_master_initial_waitstates[3:0],
|
hold_master_subsequent_waitstates[3:0]);
|
hold_master_subsequent_waitstates[3:0]);
|
$display (" Master Fast B-to_B En %h, Expect Master Abort %h",
|
$display (" Master Fast B-to_B En %h, Expect Master Abort %h",
|
hold_master_fast_b2b, hold_master_expect_master_abort);
|
hold_master_fast_b2b, hold_master_expect_master_abort);
|
$display (" Target Devsel Speed %h, Target Termination %h,",
|
$display (" Target Devsel Speed %h, Target Termination %h,",
|
hold_master_target_devsel_speed[1:0],
|
hold_master_target_devsel_speed[1:0],
|
hold_master_target_termination[2:0]);
|
hold_master_target_termination[2:0]);
|
$display (" First Target Data Wait States %h, Subsequent Target Data Wait States %h",
|
$display (" First Target Data Wait States %h, Subsequent Target Data Wait States %h",
|
hold_master_target_initial_waitstates[3:0],
|
hold_master_target_initial_waitstates[3:0],
|
hold_master_target_subsequent_waitstates[3:0]);
|
hold_master_target_subsequent_waitstates[3:0]);
|
$display (" Addr Par Error %h, Data Par Error %h",
|
$display (" Addr Par Error %h, Data Par Error %h",
|
hold_master_addr_par_err, hold_master_data_par_err);
|
hold_master_addr_par_err, hold_master_data_par_err);
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
endtask
|
endtask
|
|
|
task Complain_That_Test_Not_Written;
|
task Complain_That_Test_Not_Written;
|
output want_fast_back_to_back;
|
output want_fast_back_to_back;
|
begin
|
begin
|
$display ("*** test master %h - Diag not written yet: 'h%x, at %t",
|
$display ("*** test master %h - Diag not written yet: 'h%x, at %t",
|
test_device_id[2:0], hold_master_command[3:0], $time);
|
test_device_id[2:0], hold_master_command[3:0], $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
|
master_ad_oe <= 1'b0;
|
master_ad_oe <= 1'b0;
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4; // easy to see
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4; // easy to see
|
master_cbe_oe <= 1'b0;
|
master_cbe_oe <= 1'b0;
|
master_debug_force_bad_par <= 1'b0;
|
master_debug_force_bad_par <= 1'b0;
|
master_got_master_abort <= 1'b0;
|
master_got_master_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_perr_check_next <= 1'b0;
|
master_perr_check_next <= 1'b0;
|
Deassert_FRAME;
|
Deassert_FRAME;
|
Deassert_IRDY;
|
Deassert_IRDY;
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
Indicate_Done; // indicate done as early as possible, while still after start
|
Indicate_Done; // indicate done as early as possible, while still after start
|
want_fast_back_to_back = 1'b0;
|
want_fast_back_to_back = 1'b0;
|
end
|
end
|
endtask
|
endtask
|
|
|
task Reset_Master_To_Idle;
|
task Reset_Master_To_Idle;
|
begin
|
begin
|
master_req_out <= 1'b0;
|
master_req_out <= 1'b0;
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `PCI_BUS_DATA_ZERO;
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `PCI_BUS_DATA_ZERO;
|
master_ad_oe <= 1'b0;
|
master_ad_oe <= 1'b0;
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= `PCI_BUS_CBE_ZERO;
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= `PCI_BUS_CBE_ZERO;
|
master_cbe_oe <= 1'b0;
|
master_cbe_oe <= 1'b0;
|
master_frame_out <= 1'b0; master_irdy_out <= 1'b0;
|
master_frame_out <= 1'b0; master_irdy_out <= 1'b0;
|
master_got_master_abort <= 1'b0;
|
master_got_master_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_abort <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_got_target_retry <= 1'b0;
|
master_perr_check_next <= 1'b0;
|
master_perr_check_next <= 1'b0;
|
test_accepted_next <= 1'b0;
|
test_accepted_next <= 1'b0;
|
end
|
end
|
endtask
|
endtask
|
|
|
// We want the Target to do certain behavior to let us test the interface.
|
// We want the Target to do certain behavior to let us test the interface.
|
// We will use Address Bits to encode Target Wait State, Target Completion,
|
// We will use Address Bits to encode Target Wait State, Target Completion,
|
// and Target Error info.
|
// and Target Error info.
|
//
|
//
|
// Our Test Chips will use an 8-Bit Base Address Register, which
|
// Our Test Chips will use an 8-Bit Base Address Register, which
|
// will result in a 16 MByte memory map for each BAR.
|
// will result in a 16 MByte memory map for each BAR.
|
// Our Targets only have 256 bytes of SRAM. That leaves 16 Address
|
// Our Targets only have 256 bytes of SRAM. That leaves 16 Address
|
// Bits to play with.
|
// Bits to play with.
|
// Allocate Address Bits to mean the following:
|
// Allocate Address Bits to mean the following:
|
// Bit [23] When 1, the Target acts upon the fancy encoded info below
|
// Bit [23] When 1, the Target acts upon the fancy encoded info below
|
// Bits [22:19] Target Wait States for First Data Item
|
// Bits [22:19] Target Wait States for First Data Item
|
// Bits [18:15] Target Wait States for Subsequent Data Items
|
// Bits [18:15] Target Wait States for Subsequent Data Items
|
// Bits [14:12] What sort of Target Termination to make
|
// Bits [14:12] What sort of Target Termination to make
|
// Bits [11:10] Devsel Speed
|
// Bits [11:10] Devsel Speed
|
// Bit [9] Whether to make or expect a Data Parity Error
|
// Bit [9] Whether to make or expect a Data Parity Error
|
// Bit [8] Whether to expect an Address Parity Error
|
// Bit [8] Whether to expect an Address Parity Error
|
|
|
// fire off Master tasks in response to top-level testbench
|
// fire off Master tasks in response to top-level testbench
|
reg want_fast_back_to_back;
|
reg want_fast_back_to_back;
|
always @(posedge pci_ext_clk or posedge pci_reset_comb)
|
always @(posedge pci_ext_clk or posedge pci_reset_comb)
|
begin
|
begin
|
if ( ~pci_reset_comb & test_start
|
if ( ~pci_reset_comb & test_start
|
& (test_master_number[2:0] == test_device_id[2:0]))
|
& (test_master_number[2:0] == test_device_id[2:0]))
|
begin
|
begin
|
want_fast_back_to_back = 1'b1;
|
want_fast_back_to_back = 1'b1;
|
while (want_fast_back_to_back)
|
while (want_fast_back_to_back)
|
begin
|
begin
|
Indicate_Start;
|
Indicate_Start;
|
// Grab address and data in case it takes a while to get bus mastership
|
// Grab address and data in case it takes a while to get bus mastership
|
// Intentionally use "=" assignment so these variables are available to tasks
|
// Intentionally use "=" assignment so these variables are available to tasks
|
hold_master_address[23:9] = test_address[23:9];
|
hold_master_address[23:9] = test_address[23:9];
|
hold_master_command[3:0] = test_command[3:0];
|
hold_master_command[3:0] = test_command[3:0];
|
hold_master_data[PCI_BUS_DATA_RANGE:0] = test_data[PCI_BUS_DATA_RANGE:0];
|
hold_master_data[PCI_BUS_DATA_RANGE:0] = test_data[PCI_BUS_DATA_RANGE:0];
|
hold_master_byte_enables_l[PCI_BUS_CBE_RANGE:0] =
|
hold_master_byte_enables_l[PCI_BUS_CBE_RANGE:0] =
|
test_byte_enables_l[PCI_BUS_CBE_RANGE:0];
|
test_byte_enables_l[PCI_BUS_CBE_RANGE:0];
|
hold_master_size[9:0] = test_size[9:0];
|
hold_master_size[9:0] = test_size[9:0];
|
hold_master_addr_par_err = test_make_addr_par_error;
|
hold_master_addr_par_err = test_make_addr_par_error;
|
hold_master_data_par_err = test_make_data_par_error;
|
hold_master_data_par_err = test_make_data_par_error;
|
hold_master_initial_waitstates[3:0] = test_master_initial_wait_states[3:0];
|
hold_master_initial_waitstates[3:0] = test_master_initial_wait_states[3:0];
|
hold_master_subsequent_waitstates[3:0] = test_master_subsequent_wait_states[3:0];
|
hold_master_subsequent_waitstates[3:0] = test_master_subsequent_wait_states[3:0];
|
hold_master_target_initial_waitstates[3:0] = test_target_initial_wait_states[3:0];
|
hold_master_target_initial_waitstates[3:0] = test_target_initial_wait_states[3:0];
|
hold_master_target_subsequent_waitstates[3:0] = test_target_subsequent_wait_states[3:0];
|
hold_master_target_subsequent_waitstates[3:0] = test_target_subsequent_wait_states[3:0];
|
hold_master_target_devsel_speed[1:0] = test_target_devsel_speed[1:0];
|
hold_master_target_devsel_speed[1:0] = test_target_devsel_speed[1:0];
|
hold_master_fast_b2b = test_fast_back_to_back;
|
hold_master_fast_b2b = test_fast_back_to_back;
|
hold_master_target_termination[2:0] = test_target_termination[2:0];
|
hold_master_target_termination[2:0] = test_target_termination[2:0];
|
hold_master_expect_master_abort = test_expect_master_abort;
|
hold_master_expect_master_abort = test_expect_master_abort;
|
if (hold_master_size[9:0] == 0) // This means read causing delayed read
|
if (hold_master_size[9:0] == 0) // This means read causing delayed read
|
begin
|
begin
|
hold_master_size = 1;
|
hold_master_size = 1;
|
hold_master_target_termination = `Test_Target_Retry_Before_First;
|
hold_master_target_termination = `Test_Target_Retry_Before_First;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
// changed by Miha D. - no need for encoded addresses
|
// changed by Miha D. - no need for encoded addresses
|
modified_master_address = test_address ;
|
modified_master_address = test_address ;
|
/*
|
/*
|
modified_master_address[31:24] = test_address[31:24];
|
modified_master_address[31:24] = test_address[31:24];
|
modified_master_address[`TARGET_ENCODED_PARAMATERS_ENABLE] = 1'b1;
|
modified_master_address[`TARGET_ENCODED_PARAMATERS_ENABLE] = 1'b1;
|
modified_master_address[`TARGET_ENCODED_INIT_WAITSTATES] =
|
modified_master_address[`TARGET_ENCODED_INIT_WAITSTATES] =
|
test_target_initial_wait_states[3:0];
|
test_target_initial_wait_states[3:0];
|
modified_master_address[`TARGET_ENCODED_SUBS_WAITSTATES] =
|
modified_master_address[`TARGET_ENCODED_SUBS_WAITSTATES] =
|
test_target_subsequent_wait_states[3:0];
|
test_target_subsequent_wait_states[3:0];
|
modified_master_address[`TARGET_ENCODED_TERMINATION] =
|
modified_master_address[`TARGET_ENCODED_TERMINATION] =
|
test_target_termination[2:0];
|
test_target_termination[2:0];
|
modified_master_address[`TARGET_ENCODED_DEVSEL_SPEED] =
|
modified_master_address[`TARGET_ENCODED_DEVSEL_SPEED] =
|
test_target_devsel_speed[1:0];
|
test_target_devsel_speed[1:0];
|
modified_master_address[`TARGET_ENCODED_DATA_PAR_ERR] =
|
modified_master_address[`TARGET_ENCODED_DATA_PAR_ERR] =
|
test_make_data_par_error;
|
test_make_data_par_error;
|
modified_master_address[`TARGET_ENCODED_ADDR_PAR_ERR] =
|
modified_master_address[`TARGET_ENCODED_ADDR_PAR_ERR] =
|
test_make_addr_par_error;
|
test_make_addr_par_error;
|
modified_master_address[7:0] = test_address[7:0];
|
modified_master_address[7:0] = test_address[7:0];
|
*/
|
*/
|
case (test_command[3:0])
|
case (test_command[3:0])
|
PCI_COMMAND_INTERRUPT_ACKNOWLEDGE:
|
PCI_COMMAND_INTERRUPT_ACKNOWLEDGE:
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
PCI_COMMAND_SPECIAL_CYCLE:
|
PCI_COMMAND_SPECIAL_CYCLE:
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
PCI_COMMAND_IO_READ:
|
PCI_COMMAND_IO_READ:
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_READ,
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_READ,
|
want_fast_back_to_back);
|
want_fast_back_to_back);
|
PCI_COMMAND_IO_WRITE:
|
PCI_COMMAND_IO_WRITE:
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_WRITE,
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_WRITE,
|
want_fast_back_to_back);
|
want_fast_back_to_back);
|
PCI_COMMAND_RESERVED_READ_4:
|
PCI_COMMAND_RESERVED_READ_4:
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
PCI_COMMAND_RESERVED_WRITE_5:
|
PCI_COMMAND_RESERVED_WRITE_5:
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
PCI_COMMAND_MEMORY_READ:
|
PCI_COMMAND_MEMORY_READ:
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_READ,
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_READ,
|
want_fast_back_to_back);
|
want_fast_back_to_back);
|
PCI_COMMAND_MEMORY_WRITE:
|
PCI_COMMAND_MEMORY_WRITE:
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_WRITE,
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_WRITE,
|
want_fast_back_to_back);
|
want_fast_back_to_back);
|
PCI_COMMAND_RESERVED_READ_8:
|
PCI_COMMAND_RESERVED_READ_8:
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
PCI_COMMAND_RESERVED_WRITE_9:
|
PCI_COMMAND_RESERVED_WRITE_9:
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
PCI_COMMAND_CONFIG_READ:
|
PCI_COMMAND_CONFIG_READ:
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_CONFIG_READ,
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_CONFIG_READ,
|
want_fast_back_to_back);
|
want_fast_back_to_back);
|
PCI_COMMAND_CONFIG_WRITE:
|
PCI_COMMAND_CONFIG_WRITE:
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_CONFIG_WRITE,
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_CONFIG_WRITE,
|
want_fast_back_to_back);
|
want_fast_back_to_back);
|
PCI_COMMAND_MEMORY_READ_MULTIPLE: // Added by Tadej M., 06.12.2001
|
PCI_COMMAND_MEMORY_READ_MULTIPLE: // Added by Tadej M., 06.12.2001
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_READ_MUL,
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_READ_MUL,
|
want_fast_back_to_back);
|
want_fast_back_to_back);
|
// Complain_That_Test_Not_Written (want_fast_back_to_back);
|
// Complain_That_Test_Not_Written (want_fast_back_to_back);
|
PCI_COMMAND_DUAL_ADDRESS_CYCLE:
|
PCI_COMMAND_DUAL_ADDRESS_CYCLE:
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
PCI_COMMAND_MEMORY_READ_LINE: // Added by Tadej M., 06.12.2001
|
PCI_COMMAND_MEMORY_READ_LINE: // Added by Tadej M., 06.12.2001
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_READ_LN,
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_READ_LN,
|
want_fast_back_to_back);
|
want_fast_back_to_back);
|
// Complain_That_Test_Not_Written (want_fast_back_to_back);
|
// Complain_That_Test_Not_Written (want_fast_back_to_back);
|
PCI_COMMAND_MEMORY_WRITE_INVALIDATE:
|
PCI_COMMAND_MEMORY_WRITE_INVALIDATE:
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
default:
|
default:
|
begin
|
begin
|
$display ("*** test master %h - Unknown External Device Activity 'h%x, at %t",
|
$display ("*** test master %h - Unknown External Device Activity 'h%x, at %t",
|
test_device_id[2:0], test_command, $time);
|
test_device_id[2:0], test_command, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
endcase
|
endcase
|
if (pci_reset_comb)
|
if (pci_reset_comb)
|
begin
|
begin
|
want_fast_back_to_back = 1'b0;
|
want_fast_back_to_back = 1'b0;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
end // while want_fast_back_to_back
|
end // while want_fast_back_to_back
|
else if (~frame_now & ~irdy_now & master_gnt_now)
|
else if (~frame_now & ~irdy_now & master_gnt_now)
|
begin // park bus
|
begin // park bus
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_PARK_VALUE;
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_PARK_VALUE;
|
master_ad_oe <= 1'b1;
|
master_ad_oe <= 1'b1;
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4;
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4;
|
master_cbe_oe <= 1'b1;
|
master_cbe_oe <= 1'b1;
|
end
|
end
|
else
|
else
|
begin // unpark if grant is removed
|
begin // unpark if grant is removed
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
|
master_ad_oe <= 1'b0;
|
master_ad_oe <= 1'b0;
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4;
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4;
|
master_cbe_oe <= 1'b0;
|
master_cbe_oe <= 1'b0;
|
end
|
end
|
// NOTE WORKING need to handle master_got_target_retry here
|
// NOTE WORKING need to handle master_got_target_retry here
|
|
|
// Because this is sequential code, have to reset all regs if the above falls
|
// Because this is sequential code, have to reset all regs if the above falls
|
// through due to a reset. This would not be needed in synthesizable code.
|
// through due to a reset. This would not be needed in synthesizable code.
|
if (pci_reset_comb)
|
if (pci_reset_comb)
|
begin
|
begin
|
Reset_Master_To_Idle;
|
Reset_Master_To_Idle;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
endmodule
|
endmodule
|
|
|
|
|