`include "bus_commands.v"
|
`include "bus_commands.v"
|
module pci_unsupported_commands_master
|
module pci_unsupported_commands_master
|
(
|
(
|
CLK,
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CLK,
|
AD,
|
AD,
|
CBE,
|
CBE,
|
RST,
|
RST,
|
REQ,
|
REQ,
|
GNT,
|
GNT,
|
FRAME,
|
FRAME,
|
IRDY,
|
IRDY,
|
DEVSEL,
|
DEVSEL,
|
TRDY,
|
TRDY,
|
STOP,
|
STOP,
|
PAR
|
PAR
|
);
|
);
|
|
|
parameter normal = 0 ;
|
parameter normal = 0 ;
|
parameter disconnect = 1 ;
|
parameter disconnect = 1 ;
|
parameter retry = 2 ;
|
parameter retry = 2 ;
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parameter target_abort = 3 ;
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parameter target_abort = 3 ;
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parameter master_abort = 4 ;
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parameter master_abort = 4 ;
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parameter error = 5 ;
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parameter error = 5 ;
|
|
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input CLK ;
|
input CLK ;
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inout [31:0] AD ;
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inout [31:0] AD ;
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inout [3:0] CBE ;
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inout [3:0] CBE ;
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input RST ;
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input RST ;
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output REQ ;
|
output REQ ;
|
input GNT ;
|
input GNT ;
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inout FRAME ;
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inout FRAME ;
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inout IRDY ;
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inout IRDY ;
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input DEVSEL ;
|
input DEVSEL ;
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input TRDY ;
|
input TRDY ;
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input STOP ;
|
input STOP ;
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inout PAR ;
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inout PAR ;
|
|
|
reg [31:0] AD_int ;
|
reg [31:0] AD_int ;
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reg AD_en ;
|
reg AD_en ;
|
|
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reg [3:0] CBE_int ;
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reg [3:0] CBE_int ;
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reg CBE_en ;
|
reg CBE_en ;
|
|
|
reg FRAME_int ;
|
reg FRAME_int ;
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reg FRAME_en ;
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reg FRAME_en ;
|
|
|
reg IRDY_int ;
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reg IRDY_int ;
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reg IRDY_en ;
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reg IRDY_en ;
|
|
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reg PAR_int ;
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reg PAR_int ;
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reg PAR_en ;
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reg PAR_en ;
|
|
|
assign AD = AD_en ? AD_int : 32'hzzzz_zzzz ;
|
assign AD = AD_en ? AD_int : 32'hzzzz_zzzz ;
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assign CBE = CBE_en ? CBE_int : 4'hz ;
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assign CBE = CBE_en ? CBE_int : 4'hz ;
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assign FRAME = FRAME_en ? FRAME_int : 1'bz ;
|
assign FRAME = FRAME_en ? FRAME_int : 1'bz ;
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assign IRDY = IRDY_en ? IRDY_int : 1'bz ;
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assign IRDY = IRDY_en ? IRDY_int : 1'bz ;
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assign PAR = PAR_en ? PAR_int : 1'bz ;
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assign PAR = PAR_en ? PAR_int : 1'bz ;
|
|
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reg REQ ;
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reg REQ ;
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|
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event e_finish_transaction ;
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event e_finish_transaction ;
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event e_transfers_done ;
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event e_transfers_done ;
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|
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reg write ;
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reg write ;
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reg make_parity_error_after_last_dataphase ;
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reg make_parity_error_after_last_dataphase ;
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|
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initial
|
initial
|
begin
|
begin
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REQ = 1'b1 ;
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REQ = 1'b1 ;
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AD_en = 1'b0 ;
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AD_en = 1'b0 ;
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CBE_en = 1'b0 ;
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CBE_en = 1'b0 ;
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FRAME_en = 1'b0 ;
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FRAME_en = 1'b0 ;
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IRDY_en = 1'b0 ;
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IRDY_en = 1'b0 ;
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PAR_en = 1'b0 ;
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PAR_en = 1'b0 ;
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write = 1'b0 ;
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write = 1'b0 ;
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make_parity_error_after_last_dataphase = 1'b0 ;
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make_parity_error_after_last_dataphase = 1'b0 ;
|
end
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end
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|
|
task unsupported_reference ;
|
task unsupported_reference ;
|
input [31:0] addr1 ;
|
input [31:0] addr1 ;
|
input [31:0] addr2 ;
|
input [31:0] addr2 ;
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input [3:0] bc1 ;
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input [3:0] bc1 ;
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input [3:0] bc2 ;
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input [3:0] bc2 ;
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input [3:0] be ;
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input [3:0] be ;
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input [31:0] data ;
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input [31:0] data ;
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input make_addr_perr1 ;
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input make_addr_perr1 ;
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input make_addr_perr2 ;
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input make_addr_perr2 ;
|
output ok ;
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output ok ;
|
integer i ;
|
integer i ;
|
reg dual_address ;
|
reg dual_address ;
|
reg [2:0] received_termination ;
|
reg [2:0] received_termination ;
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begin:main
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begin:main
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ok = 1 ;
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ok = 1 ;
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dual_address = (bc1 == `BC_DUAL_ADDR_CYC) ;
|
dual_address = (bc1 == `BC_DUAL_ADDR_CYC) ;
|
|
|
get_bus_ownership(ok) ;
|
get_bus_ownership(ok) ;
|
if (ok !== 1'b1)
|
if (ok !== 1'b1)
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disable main ;
|
disable main ;
|
|
|
addr_phase1(addr1, bc1) ;
|
addr_phase1(addr1, bc1) ;
|
|
|
if ( dual_address )
|
if ( dual_address )
|
begin
|
begin
|
write = bc2[0] ;
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write = bc2[0] ;
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addr_phase2(addr2, bc2, make_addr_perr1) ;
|
addr_phase2(addr2, bc2, make_addr_perr1) ;
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first_and_last_data_phase(bc2[0], data, be, make_addr_perr2, 1'b0, received_termination) ;
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first_and_last_data_phase(bc2[0], data, be, make_addr_perr2, 1'b0, received_termination) ;
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finish_transaction(bc2[0], 1'b0) ;
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finish_transaction(bc2[0], 1'b0) ;
|
end
|
end
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else
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else
|
begin
|
begin
|
write = bc1[0] ;
|
write = bc1[0] ;
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first_and_last_data_phase(bc1[0], data, be, make_addr_perr1, 1'b0, received_termination) ;
|
first_and_last_data_phase(bc1[0], data, be, make_addr_perr1, 1'b0, received_termination) ;
|
finish_transaction(bc1[0], 1'b0) ;
|
finish_transaction(bc1[0], 1'b0) ;
|
end
|
end
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|
|
if (received_termination !== master_abort)
|
if (received_termination !== master_abort)
|
begin
|
begin
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
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end
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end
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endtask // master_reference
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endtask // master_reference
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|
|
// task added for target overflow testing
|
// task added for target overflow testing
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// master writes the addresses to the coresponding locations
|
// master writes the addresses to the coresponding locations
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task normal_write_transfer ;
|
task normal_write_transfer ;
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input [31:0] start_address ;
|
input [31:0] start_address ;
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input [3:0] bus_command ;
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input [3:0] bus_command ;
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input [31:0] size ;
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input [31:0] size ;
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input [2:0] wait_cycles ;
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input [2:0] wait_cycles ;
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output [31:0] actual_transfer ;
|
output [31:0] actual_transfer ;
|
output [2:0] received_termination ;
|
output [2:0] received_termination ;
|
reg ok ;
|
reg ok ;
|
reg [31:0] current_address ;
|
reg [31:0] current_address ;
|
begin:main
|
begin:main
|
|
|
write = 1'b1 ;
|
write = 1'b1 ;
|
get_bus_ownership (ok) ;
|
get_bus_ownership (ok) ;
|
if (ok !== 1'b1)
|
if (ok !== 1'b1)
|
begin
|
begin
|
received_termination = error ;
|
received_termination = error ;
|
disable main ;
|
disable main ;
|
end
|
end
|
|
|
make_parity_error_after_last_dataphase = 1'b0 ;
|
make_parity_error_after_last_dataphase = 1'b0 ;
|
|
|
addr_phase1(start_address, bus_command) ;
|
addr_phase1(start_address, bus_command) ;
|
actual_transfer = 0 ;
|
actual_transfer = 0 ;
|
if (size == 1)
|
if (size == 1)
|
begin
|
begin
|
first_and_last_data_phase (1'b1, ~start_address, 4'hF, 1'b0, 1'b0, received_termination) ;
|
first_and_last_data_phase (1'b1, ~start_address, 4'hF, 1'b0, 1'b0, received_termination) ;
|
if ((received_termination == normal) || (received_termination == disconnect))
|
if ((received_termination == normal) || (received_termination == disconnect))
|
actual_transfer = 1 ;
|
actual_transfer = 1 ;
|
|
|
-> e_finish_transaction ;
|
-> e_finish_transaction ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
current_address = start_address ;
|
current_address = start_address ;
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first_data_phase (1'b1, ~start_address, 4'hF, 1'b0, 1'b0, received_termination) ;
|
first_data_phase (1'b1, ~start_address, 4'hF, 1'b0, 1'b0, received_termination) ;
|
if ((received_termination == normal) || (received_termination == disconnect))
|
if ((received_termination == normal) || (received_termination == disconnect))
|
actual_transfer = 1 ;
|
actual_transfer = 1 ;
|
|
|
if (received_termination == master_abort)
|
if (received_termination == master_abort)
|
begin
|
begin
|
-> e_transfers_done ;
|
-> e_transfers_done ;
|
end
|
end
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|
|
while ((actual_transfer < (size - 1)) && (received_termination == normal))
|
while ((actual_transfer < (size - 1)) && (received_termination == normal))
|
begin
|
begin
|
current_address = current_address + 4 ;
|
current_address = current_address + 4 ;
|
insert_waits(1'b1, wait_cycles, received_termination) ;
|
insert_waits(1'b1, wait_cycles, received_termination) ;
|
if (received_termination === normal)
|
if (received_termination === normal)
|
begin
|
begin
|
subsequent_data_phase(1'b1, ~current_address, 4'hF, 1'b0, received_termination) ;
|
subsequent_data_phase(1'b1, ~current_address, 4'hF, 1'b0, received_termination) ;
|
if ((received_termination == normal) || (received_termination == disconnect))
|
if ((received_termination == normal) || (received_termination == disconnect))
|
actual_transfer = actual_transfer + 1 ;
|
actual_transfer = actual_transfer + 1 ;
|
end
|
end
|
end
|
end
|
|
|
if (received_termination == normal)
|
if (received_termination == normal)
|
begin
|
begin
|
insert_waits(1'b1, wait_cycles, received_termination) ;
|
insert_waits(1'b1, wait_cycles, received_termination) ;
|
if (received_termination === normal)
|
if (received_termination === normal)
|
begin
|
begin
|
last_data_phase(1'b1, ~current_address, 4'hF, 1'b0, received_termination) ;
|
last_data_phase(1'b1, ~current_address, 4'hF, 1'b0, received_termination) ;
|
if ((received_termination == normal) || (received_termination == disconnect))
|
if ((received_termination == normal) || (received_termination == disconnect))
|
actual_transfer = actual_transfer + 1 ;
|
actual_transfer = actual_transfer + 1 ;
|
|
|
-> e_finish_transaction ;
|
-> e_finish_transaction ;
|
end
|
end
|
else
|
else
|
-> e_transfers_done ;
|
-> e_transfers_done ;
|
end
|
end
|
else
|
else
|
-> e_transfers_done ;
|
-> e_transfers_done ;
|
end
|
end
|
end
|
end
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endtask // normal_write_transfer
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endtask // normal_write_transfer
|
|
|
task get_bus_ownership ;
|
task get_bus_ownership ;
|
output ok ;
|
output ok ;
|
integer deadlock ;
|
integer deadlock ;
|
begin
|
begin
|
deadlock = 0 ;
|
deadlock = 0 ;
|
@(posedge CLK) ;
|
@(posedge CLK) ;
|
while( ((GNT !== 0) || (FRAME !== 1'b1) || (IRDY !== 1'b1)) && (deadlock < 5000) )
|
while( ((GNT !== 0) || (FRAME !== 1'b1) || (IRDY !== 1'b1)) && (deadlock < 5000) )
|
begin
|
begin
|
REQ <= #6 1'b0 ;
|
REQ <= #6 1'b0 ;
|
@(posedge CLK) ;
|
@(posedge CLK) ;
|
deadlock = deadlock + 1 ;
|
deadlock = deadlock + 1 ;
|
end
|
end
|
|
|
if (GNT !== 0)
|
if (GNT !== 0)
|
begin
|
begin
|
$display("*E, PCI Master could not get ownership of the bus in 5000 cycles") ;
|
$display("*E, PCI Master could not get ownership of the bus in 5000 cycles") ;
|
ok = 0 ;
|
ok = 0 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
ok = 1 ;
|
ok = 1 ;
|
end
|
end
|
|
|
REQ <= #6 1'b1 ;
|
REQ <= #6 1'b1 ;
|
end
|
end
|
endtask // get_bus_ownership
|
endtask // get_bus_ownership
|
|
|
task addr_phase1 ;
|
task addr_phase1 ;
|
input [31:0] address ;
|
input [31:0] address ;
|
input [3:0] bus_command ;
|
input [3:0] bus_command ;
|
begin
|
begin
|
FRAME_en <= #6 1'b1 ;
|
FRAME_en <= #6 1'b1 ;
|
FRAME_int <= #6 1'b0 ;
|
FRAME_int <= #6 1'b0 ;
|
|
|
AD_en <= #6 1'b1 ;
|
AD_en <= #6 1'b1 ;
|
AD_int <= #6 address ;
|
AD_int <= #6 address ;
|
|
|
CBE_en <= #6 1'b1 ;
|
CBE_en <= #6 1'b1 ;
|
CBE_int <= #6 bus_command ;
|
CBE_int <= #6 bus_command ;
|
@(posedge CLK) ;
|
@(posedge CLK) ;
|
end
|
end
|
endtask // addr_phase1
|
endtask // addr_phase1
|
|
|
task addr_phase2 ;
|
task addr_phase2 ;
|
input [31:0] address ;
|
input [31:0] address ;
|
input [3:0] bus_command ;
|
input [3:0] bus_command ;
|
input make_parity_error;
|
input make_parity_error;
|
begin
|
begin
|
PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
|
PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
|
PAR_en <= #6 1'b1 ;
|
PAR_en <= #6 1'b1 ;
|
AD_int <= #6 address ;
|
AD_int <= #6 address ;
|
CBE_int <= #6 bus_command ;
|
CBE_int <= #6 bus_command ;
|
@(posedge CLK) ;
|
@(posedge CLK) ;
|
end
|
end
|
endtask
|
endtask
|
|
|
task first_and_last_data_phase ;
|
task first_and_last_data_phase ;
|
input rw ;
|
input rw ;
|
input [31:0] data ;
|
input [31:0] data ;
|
input [3:0] be ;
|
input [3:0] be ;
|
input make_addr_parity_error ;
|
input make_addr_parity_error ;
|
input make_data_parity_error ;
|
input make_data_parity_error ;
|
output [2:0] received_termination ;
|
output [2:0] received_termination ;
|
integer i ;
|
integer i ;
|
begin
|
begin
|
FRAME_int <= #6 1'b1 ;
|
FRAME_int <= #6 1'b1 ;
|
first_data_phase (rw, data, be, make_addr_parity_error, make_data_parity_error, received_termination) ;
|
first_data_phase (rw, data, be, make_addr_parity_error, make_data_parity_error, received_termination) ;
|
end
|
end
|
endtask // first_and_last_data_phase
|
endtask // first_and_last_data_phase
|
|
|
task first_data_phase ;
|
task first_data_phase ;
|
input rw ;
|
input rw ;
|
input [31:0] data ;
|
input [31:0] data ;
|
input [3:0] be ;
|
input [3:0] be ;
|
input make_addr_parity_error ;
|
input make_addr_parity_error ;
|
input make_data_parity_error ;
|
input make_data_parity_error ;
|
output [2:0] received_termination ;
|
output [2:0] received_termination ;
|
integer i ;
|
integer i ;
|
begin
|
begin
|
PAR_int <= #6 ^{AD, CBE, make_addr_parity_error} ;
|
PAR_int <= #6 ^{AD, CBE, make_addr_parity_error} ;
|
PAR_en <= #6 1'b1 ;
|
PAR_en <= #6 1'b1 ;
|
IRDY_en <= #6 1'b1 ;
|
IRDY_en <= #6 1'b1 ;
|
IRDY_int <= #6 1'b0 ;
|
IRDY_int <= #6 1'b0 ;
|
CBE_int <= #6 be ;
|
CBE_int <= #6 be ;
|
if (rw)
|
if (rw)
|
AD_int <= #6 data ;
|
AD_int <= #6 data ;
|
else
|
else
|
AD_en <= #6 1'b0 ;
|
AD_en <= #6 1'b0 ;
|
|
|
@(posedge CLK) ;
|
@(posedge CLK) ;
|
if (!rw)
|
if (!rw)
|
PAR_en <= #6 1'b0 ;
|
PAR_en <= #6 1'b0 ;
|
else
|
else
|
PAR_int <= #6 ^{AD, CBE, make_data_parity_error} ;
|
PAR_int <= #6 ^{AD, CBE, make_data_parity_error} ;
|
|
|
i = 1 ;
|
i = 1 ;
|
while ( (i < 5) && (DEVSEL === 1'b1) )
|
while ( (i < 5) && (DEVSEL === 1'b1) )
|
begin
|
begin
|
@(posedge CLK) ;
|
@(posedge CLK) ;
|
i = i + 1 ;
|
i = i + 1 ;
|
end
|
end
|
|
|
if (DEVSEL === 1'b1)
|
if (DEVSEL === 1'b1)
|
begin
|
begin
|
received_termination = master_abort ;
|
received_termination = master_abort ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
get_termination(received_termination);
|
get_termination(received_termination);
|
end
|
end
|
end
|
end
|
endtask // first_data_phase
|
endtask // first_data_phase
|
|
|
task subsequent_data_phase ;
|
task subsequent_data_phase ;
|
input rw ;
|
input rw ;
|
input [31:0] data ;
|
input [31:0] data ;
|
input [3:0] be ;
|
input [3:0] be ;
|
input make_parity_error ;
|
input make_parity_error ;
|
output [2:0] received_termination ;
|
output [2:0] received_termination ;
|
begin
|
begin
|
if (rw)
|
if (rw)
|
begin
|
begin
|
PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
|
PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
|
AD_int <= #6 data ;
|
AD_int <= #6 data ;
|
end
|
end
|
|
|
IRDY_int <= #6 1'b0 ;
|
IRDY_int <= #6 1'b0 ;
|
CBE_int <= #6 be ;
|
CBE_int <= #6 be ;
|
@(posedge CLK);
|
@(posedge CLK);
|
get_termination(received_termination);
|
get_termination(received_termination);
|
end
|
end
|
endtask // subsequent_data_phase
|
endtask // subsequent_data_phase
|
|
|
task last_data_phase ;
|
task last_data_phase ;
|
input rw ;
|
input rw ;
|
input [31:0] data ;
|
input [31:0] data ;
|
input [3:0] be ;
|
input [3:0] be ;
|
input make_parity_error ;
|
input make_parity_error ;
|
output [2:0] received_termination ;
|
output [2:0] received_termination ;
|
begin
|
begin
|
FRAME_int <= #6 1'b1 ;
|
FRAME_int <= #6 1'b1 ;
|
IRDY_int <= #6 1'b0 ;
|
IRDY_int <= #6 1'b0 ;
|
if (rw)
|
if (rw)
|
begin
|
begin
|
PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
|
PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
|
AD_int <= #6 data ;
|
AD_int <= #6 data ;
|
end
|
end
|
|
|
CBE_int <= #6 be ;
|
CBE_int <= #6 be ;
|
|
|
@(posedge CLK);
|
@(posedge CLK);
|
get_termination(received_termination);
|
get_termination(received_termination);
|
end
|
end
|
endtask // subsequent_data_phase
|
endtask // subsequent_data_phase
|
|
|
task get_termination ;
|
task get_termination ;
|
output [2:0] received_termination ;
|
output [2:0] received_termination ;
|
begin
|
begin
|
while ((TRDY === 1'b1) && (STOP === 1'b1))
|
while ((TRDY === 1'b1) && (STOP === 1'b1))
|
@(posedge CLK) ;
|
@(posedge CLK) ;
|
|
|
if ( DEVSEL !== 1'b0 )
|
if ( DEVSEL !== 1'b0 )
|
received_termination = target_abort ;
|
received_termination = target_abort ;
|
else if (TRDY !== 1'b1)
|
else if (TRDY !== 1'b1)
|
begin
|
begin
|
if (STOP !== 1'b1)
|
if (STOP !== 1'b1)
|
received_termination = disconnect ;
|
received_termination = disconnect ;
|
else
|
else
|
received_termination = normal ;
|
received_termination = normal ;
|
end
|
end
|
else
|
else
|
received_termination = retry ;
|
received_termination = retry ;
|
end
|
end
|
endtask // get_termination
|
endtask // get_termination
|
|
|
task finish_transaction ;
|
task finish_transaction ;
|
input rw ;
|
input rw ;
|
input make_parity_error ;
|
input make_parity_error ;
|
begin
|
begin
|
if (rw)
|
if (rw)
|
PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
|
PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
|
|
|
IRDY_int <= #6 1'b1 ;
|
IRDY_int <= #6 1'b1 ;
|
FRAME_en <= #6 1'b0 ;
|
FRAME_en <= #6 1'b0 ;
|
AD_en <= #6 1'b0 ;
|
AD_en <= #6 1'b0 ;
|
CBE_en <= #6 1'b0 ;
|
CBE_en <= #6 1'b0 ;
|
|
|
@(posedge CLK) ;
|
@(posedge CLK) ;
|
PAR_en <= #6 1'b0 ;
|
PAR_en <= #6 1'b0 ;
|
IRDY_en <= #6 1'b0 ;
|
IRDY_en <= #6 1'b0 ;
|
end
|
end
|
endtask // finish_transaction
|
endtask // finish_transaction
|
|
|
always@(e_finish_transaction)
|
always@(e_finish_transaction)
|
begin
|
begin
|
finish_transaction (write, make_parity_error_after_last_dataphase) ;
|
finish_transaction (write, make_parity_error_after_last_dataphase) ;
|
end
|
end
|
|
|
always@(e_transfers_done)
|
always@(e_transfers_done)
|
begin
|
begin
|
|
|
if (FRAME !== 1'b1)
|
if (FRAME !== 1'b1)
|
begin
|
begin
|
FRAME_int <= #6 1'b1 ;
|
FRAME_int <= #6 1'b1 ;
|
IRDY_int <= #6 1'b0 ;
|
IRDY_int <= #6 1'b0 ;
|
if (write)
|
if (write)
|
PAR_int <= #6 ^{CBE, AD} ;
|
PAR_int <= #6 ^{CBE, AD} ;
|
|
|
@(posedge CLK) ;
|
@(posedge CLK) ;
|
end
|
end
|
|
|
-> e_finish_transaction ;
|
-> e_finish_transaction ;
|
end
|
end
|
|
|
task insert_waits ;
|
task insert_waits ;
|
input rw ;
|
input rw ;
|
input [2:0] wait_cycles ;
|
input [2:0] wait_cycles ;
|
output [2:0] termination ;
|
output [2:0] termination ;
|
reg [2:0] wait_cycles_left ;
|
reg [2:0] wait_cycles_left ;
|
reg stop_without_trdy_received ;
|
reg stop_without_trdy_received ;
|
begin
|
begin
|
stop_without_trdy_received = 1'b0 ;
|
stop_without_trdy_received = 1'b0 ;
|
wait_cycles_left = wait_cycles ;
|
wait_cycles_left = wait_cycles ;
|
|
|
termination = normal ;
|
termination = normal ;
|
|
|
PAR_int <= #6 ^{AD, CBE} ;
|
PAR_int <= #6 ^{AD, CBE} ;
|
|
|
for (wait_cycles_left = wait_cycles ; (wait_cycles_left > 0) && !stop_without_trdy_received ; wait_cycles_left = wait_cycles_left - 1'b1)
|
for (wait_cycles_left = wait_cycles ; (wait_cycles_left > 0) && !stop_without_trdy_received ; wait_cycles_left = wait_cycles_left - 1'b1)
|
begin
|
begin
|
IRDY_int <= #6 1'b1 ;
|
IRDY_int <= #6 1'b1 ;
|
@(posedge CLK) ;
|
@(posedge CLK) ;
|
|
|
PAR_int <= #6 ^{AD, CBE, 1'b1} ;
|
PAR_int <= #6 ^{AD, CBE, 1'b1} ;
|
|
|
if ((STOP !== 1'b1) && (TRDY !== 1'b0))
|
if ((STOP !== 1'b1) && (TRDY !== 1'b0))
|
begin
|
begin
|
stop_without_trdy_received = 1'b1 ;
|
stop_without_trdy_received = 1'b1 ;
|
if (DEVSEL !== 1'b0)
|
if (DEVSEL !== 1'b0)
|
termination = target_abort ;
|
termination = target_abort ;
|
else
|
else
|
termination = retry ;
|
termination = retry ;
|
end
|
end
|
end
|
end
|
end
|
end
|
endtask // insert_waits
|
endtask // insert_waits
|
endmodule
|
endmodule
|
|
|
|
|