//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// File name: wb_slave_behavioral.v ////
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//// File name: wb_slave_behavioral.v ////
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//// ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/02/01 13:39:43 mihad
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// Initial testbench import. Still under development
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//
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//
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//
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`include "pci_testbench_defines.v"
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`include "pci_testbench_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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`include "pci_constants.v"
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module WB_SLAVE_BEHAVIORAL
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module WB_SLAVE_BEHAVIORAL
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(
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(
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CLK_I,
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CLK_I,
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RST_I,
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RST_I,
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ACK_O,
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ACK_O,
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ADR_I,
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ADR_I,
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CYC_I,
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CYC_I,
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DAT_O,
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DAT_O,
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DAT_I,
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DAT_I,
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ERR_O,
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ERR_O,
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RTY_O,
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RTY_O,
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SEL_I,
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SEL_I,
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STB_I,
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STB_I,
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WE_I,
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WE_I,
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CAB_I
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CAB_I
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);
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);
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/*----------------------------------------------------------------------------------------------------------------------
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/*----------------------------------------------------------------------------------------------------------------------
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WISHBONE signals
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WISHBONE signals
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----------------------------------------------------------------------------------------------------------------------*/
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----------------------------------------------------------------------------------------------------------------------*/
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input CLK_I ;
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input CLK_I ;
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input RST_I ;
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input RST_I ;
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output ACK_O ;
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output ACK_O ;
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input `WB_ADDR_TYPE ADR_I ;
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input `WB_ADDR_TYPE ADR_I ;
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input CYC_I ;
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input CYC_I ;
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output `WB_DATA_TYPE DAT_O ;
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output `WB_DATA_TYPE DAT_O ;
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input `WB_DATA_TYPE DAT_I ;
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input `WB_DATA_TYPE DAT_I ;
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output ERR_O ;
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output ERR_O ;
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output RTY_O ;
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output RTY_O ;
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input `WB_SEL_TYPE SEL_I ;
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input `WB_SEL_TYPE SEL_I ;
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input STB_I ;
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input STB_I ;
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input WE_I ;
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input WE_I ;
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input CAB_I ;
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input CAB_I ;
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|
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//reg ACK_O ;
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//reg ACK_O ;
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//reg ERR_O ;
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//reg ERR_O ;
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//reg RTY_O ;
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//reg RTY_O ;
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reg [31:0] DAT_O ;
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reg [31:0] DAT_O ;
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/*----------------------------------------------------------------------------------------------------------------------
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/*----------------------------------------------------------------------------------------------------------------------
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Asynchronous dual-port RAM signals for storing and fetching the data
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Asynchronous dual-port RAM signals for storing and fetching the data
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----------------------------------------------------------------------------------------------------------------------*/
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----------------------------------------------------------------------------------------------------------------------*/
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reg [31:0] wb_memory [0:1023] ; // data for WB memory - 16 LSB addresses are connected
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reg [31:0] wb_memory [0:1023] ; // data for WB memory - 16 LSB addresses are connected
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reg [31:0] mem_wr_data_out ;
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reg [31:0] mem_wr_data_out ;
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reg [31:0] mem_rd_data_in ;
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reg [31:0] mem_rd_data_in ;
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|
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/*----------------------------------------------------------------------------------------------------------------------
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/*----------------------------------------------------------------------------------------------------------------------
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Maximum values for WAIT and RETRY counters and which response !!!
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Maximum values for WAIT and RETRY counters and which response !!!
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----------------------------------------------------------------------------------------------------------------------*/
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----------------------------------------------------------------------------------------------------------------------*/
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reg [2:0] a_e_r_resp ; // tells with which cycle_termination_signal must wb_slave respond !
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reg [2:0] a_e_r_resp ; // tells with which cycle_termination_signal must wb_slave respond !
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reg wait_cyc ;
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reg wait_cyc ;
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reg [7:0] max_retry ;
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reg [7:0] max_retry ;
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// assign registers to default state while in reset
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// assign registers to default state while in reset
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always@(RST_I)
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always@(RST_I)
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begin
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begin
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if (RST_I)
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if (RST_I)
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begin
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begin
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a_e_r_resp <= 3'b000 ; // do not respond
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a_e_r_resp <= 3'b000 ; // do not respond
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wait_cyc <= 1'b0 ; // no wait cycles
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wait_cyc <= 1'b0 ; // no wait cycles
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max_retry <= 8'h0 ; // no retries
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max_retry <= 8'h0 ; // no retries
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end
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end
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end //reset
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end //reset
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task cycle_response ;
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task cycle_response ;
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input [2:0] ack_err_rty_resp ; // acknowledge, error or retry response input flags
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input [2:0] ack_err_rty_resp ; // acknowledge, error or retry response input flags
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input wait_cycles ; // if wait cycles before each data termination cycle (ack, err or rty)
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input wait_cycles ; // if wait cycles before each data termination cycle (ack, err or rty)
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input [7:0] retry_cycles ; // noumber of retry cycles before acknowledge cycle
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input [7:0] retry_cycles ; // noumber of retry cycles before acknowledge cycle
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begin
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begin
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// assign values
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// assign values
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a_e_r_resp <= #1 ack_err_rty_resp ;
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a_e_r_resp <= #1 ack_err_rty_resp ;
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wait_cyc <= #1 wait_cycles ;
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wait_cyc <= #1 wait_cycles ;
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max_retry <= #1 retry_cycles ;
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max_retry <= #1 retry_cycles ;
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end
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end
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endtask // cycle_response
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endtask // cycle_response
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/*----------------------------------------------------------------------------------------------------------------------
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/*----------------------------------------------------------------------------------------------------------------------
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Internal signals and logic
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Internal signals and logic
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----------------------------------------------------------------------------------------------------------------------*/
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----------------------------------------------------------------------------------------------------------------------*/
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reg calc_ack ;
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reg calc_ack ;
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reg calc_err ;
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reg calc_err ;
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reg calc_rty ;
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reg calc_rty ;
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reg [7:0] retry_cnt ;
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reg [7:0] retry_cnt ;
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reg [7:0] retry_num ;
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reg [7:0] retry_num ;
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reg retry_expired ;
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reg retry_expired ;
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reg retry_rst ;
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reg retry_rst ;
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// RESET retry counter
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// RESET retry counter
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always@(posedge RST_I or posedge CLK_I)
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always@(posedge RST_I or posedge CLK_I)
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begin
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begin
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if (RST_I)
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if (RST_I)
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retry_rst <= 1'b1 ;
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retry_rst <= 1'b1 ;
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else
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else
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retry_rst <= calc_ack || calc_err ;
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retry_rst <= calc_ack || calc_err ;
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end
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end
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// Retry counter
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// Retry counter
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always@(posedge retry_rst or negedge calc_rty)
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always@(posedge retry_rst or negedge calc_rty)
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begin
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begin
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if (retry_rst)
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if (retry_rst)
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retry_cnt <= #`FF_DELAY 8'h00 ;
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retry_cnt <= #`FF_DELAY 8'h00 ;
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else
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else
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retry_cnt <= #`FF_DELAY retry_num ;
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retry_cnt <= #`FF_DELAY retry_num ;
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end
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end
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always@(retry_cnt or max_retry)
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always@(retry_cnt or max_retry)
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begin
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begin
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if (retry_cnt < max_retry)
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if (retry_cnt < max_retry)
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begin
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begin
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retry_num = retry_cnt + 1'b1 ;
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retry_num = retry_cnt + 1'b1 ;
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retry_expired = #10 1'b0 ;
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retry_expired = #10 1'b0 ;
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end
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end
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else
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else
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begin
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begin
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retry_num = retry_cnt ;
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retry_num = retry_cnt ;
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retry_expired = #10 1'b1 ;
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retry_expired = #10 1'b1 ;
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end
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end
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end
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end
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reg [1:0] wait_cnt ;
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reg [1:0] wait_cnt ;
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reg [1:0] wait_num ;
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reg [1:0] wait_num ;
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reg wait_expired ;
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reg wait_expired ;
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reg reset_wait ;
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reg reset_wait ;
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always@(posedge RST_I or posedge CLK_I)
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always@(posedge RST_I or posedge CLK_I)
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begin
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begin
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if (RST_I)
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if (RST_I)
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reset_wait <= #`FF_DELAY 1'b1 ;
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reset_wait <= #`FF_DELAY 1'b1 ;
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else
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else
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reset_wait <= #`FF_DELAY (wait_expired || ~STB_I) ;
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reset_wait <= #`FF_DELAY (wait_expired || ~STB_I) ;
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end
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end
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// Wait counter
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// Wait counter
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always@(posedge reset_wait or posedge CLK_I)
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always@(posedge reset_wait or posedge CLK_I)
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begin
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begin
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if (reset_wait)
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if (reset_wait)
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wait_cnt <= #`FF_DELAY 4'h0 ;
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wait_cnt <= #`FF_DELAY 4'h0 ;
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else
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else
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wait_cnt <= #`FF_DELAY wait_num ;
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wait_cnt <= #`FF_DELAY wait_num ;
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end
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end
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always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired)
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always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired)
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begin
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begin
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if ((wait_cyc) && (STB_I))
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if ((wait_cyc) && (STB_I))
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begin
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begin
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if (wait_cnt < 2'h2)
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if (wait_cnt < 2'h2)
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begin
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begin
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wait_num = wait_cnt + 1'b1 ;
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wait_num = wait_cnt + 1'b1 ;
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wait_expired = 1'b0 ;
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wait_expired = 1'b0 ;
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calc_ack = 1'b0 ;
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calc_ack = 1'b0 ;
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calc_err = 1'b0 ;
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calc_err = 1'b0 ;
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calc_rty = 1'b0 ;
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calc_rty = 1'b0 ;
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end
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end
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else
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else
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begin
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begin
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wait_num = wait_cnt ;
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wait_num = wait_cnt ;
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wait_expired = 1'b1 ;
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wait_expired = 1'b1 ;
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if (a_e_r_resp == 3'b100)
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if (a_e_r_resp == 3'b100)
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begin
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begin
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calc_ack = 1'b1 ;
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calc_ack = 1'b1 ;
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calc_err = 1'b0 ;
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calc_err = 1'b0 ;
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calc_rty = 1'b0 ;
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calc_rty = 1'b0 ;
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end
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end
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else
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else
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if (a_e_r_resp == 3'b010)
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if (a_e_r_resp == 3'b010)
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begin
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begin
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calc_ack = 1'b0 ;
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calc_ack = 1'b0 ;
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calc_err = 1'b1 ;
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calc_err = 1'b1 ;
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calc_rty = 1'b0 ;
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calc_rty = 1'b0 ;
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end
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end
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else
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else
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if (a_e_r_resp == 3'b001)
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if (a_e_r_resp == 3'b001)
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begin
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begin
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calc_err = 1'b0 ;
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calc_err = 1'b0 ;
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if (retry_expired)
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if (retry_expired)
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begin
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begin
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calc_ack = 1'b1 ;
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calc_ack = 1'b1 ;
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calc_rty = 1'b0 ;
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calc_rty = 1'b0 ;
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end
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end
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else
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else
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begin
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begin
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calc_ack = 1'b0 ;
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calc_ack = 1'b0 ;
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calc_rty = 1'b1 ;
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calc_rty = 1'b1 ;
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end
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end
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end
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end
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else
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else
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begin
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begin
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calc_ack = 1'b0 ;
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calc_ack = 1'b0 ;
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calc_err = 1'b0 ;
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calc_err = 1'b0 ;
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calc_rty = 1'b0 ;
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calc_rty = 1'b0 ;
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end
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end
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end
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end
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end
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end
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else
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else
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if ((~wait_cyc) && (STB_I))
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if ((~wait_cyc) && (STB_I))
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begin
|
begin
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wait_num = 2'h0 ;
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wait_num = 2'h0 ;
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wait_expired = 1'b1 ;
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wait_expired = 1'b1 ;
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if (a_e_r_resp == 3'b100)
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if (a_e_r_resp == 3'b100)
|
begin
|
begin
|
calc_ack = 1'b1 ;
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calc_ack = 1'b1 ;
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calc_err = 1'b0 ;
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calc_err = 1'b0 ;
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calc_rty = 1'b0 ;
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calc_rty = 1'b0 ;
|
end
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end
|
else
|
else
|
if (a_e_r_resp == 3'b010)
|
if (a_e_r_resp == 3'b010)
|
begin
|
begin
|
calc_ack = 1'b0 ;
|
calc_ack = 1'b0 ;
|
calc_err = 1'b1 ;
|
calc_err = 1'b1 ;
|
calc_rty = 1'b0 ;
|
calc_rty = 1'b0 ;
|
end
|
end
|
else
|
else
|
if (a_e_r_resp == 3'b001)
|
if (a_e_r_resp == 3'b001)
|
begin
|
begin
|
calc_err = 1'b0 ;
|
calc_err = 1'b0 ;
|
if (retry_expired)
|
if (retry_expired)
|
begin
|
begin
|
calc_ack = 1'b1 ;
|
calc_ack = 1'b1 ;
|
calc_rty = 1'b0 ;
|
calc_rty = 1'b0 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
calc_ack = 1'b0 ;
|
calc_ack = 1'b0 ;
|
calc_rty = 1'b1 ;
|
calc_rty = 1'b1 ;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
calc_ack = 1'b0 ;
|
calc_ack = 1'b0 ;
|
calc_err = 1'b0 ;
|
calc_err = 1'b0 ;
|
calc_rty = 1'b0 ;
|
calc_rty = 1'b0 ;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
wait_num = 2'h0 ;
|
wait_num = 2'h0 ;
|
wait_expired = 1'b0 ;
|
wait_expired = 1'b0 ;
|
calc_ack = 1'b0 ;
|
calc_ack = 1'b0 ;
|
calc_err = 1'b0 ;
|
calc_err = 1'b0 ;
|
calc_rty = 1'b0 ;
|
calc_rty = 1'b0 ;
|
end
|
end
|
end
|
end
|
|
|
wire rd_sel = (CYC_I && STB_I && ~WE_I) ;
|
wire rd_sel = (CYC_I && STB_I && ~WE_I) ;
|
wire wr_sel = (CYC_I && STB_I && WE_I) ;
|
wire wr_sel = (CYC_I && STB_I && WE_I) ;
|
|
|
// Generate cycle termination signals
|
// Generate cycle termination signals
|
assign ACK_O = calc_ack && STB_I ;
|
assign ACK_O = calc_ack && STB_I ;
|
assign ERR_O = calc_err && STB_I ;
|
assign ERR_O = calc_err && STB_I ;
|
assign RTY_O = calc_rty && STB_I ;
|
assign RTY_O = calc_rty && STB_I ;
|
|
|
// Assign address to asynchronous memory
|
// Assign address to asynchronous memory
|
always@(ADR_I or RST_I)
|
always@(ADR_I or RST_I)
|
begin
|
begin
|
if (RST_I) // this is added because at start of test bench we need address change in order to get data!
|
if (RST_I) // this is added because at start of test bench we need address change in order to get data!
|
mem_rd_data_in = 32'hxxxx_xxxx ;
|
mem_rd_data_in = 32'hxxxx_xxxx ;
|
else
|
else
|
mem_rd_data_in = wb_memory[ADR_I[11:2]] ;
|
mem_rd_data_in = wb_memory[ADR_I[11:2]] ;
|
end
|
end
|
|
|
// assign outputs to unknown state while in reset
|
// assign outputs to unknown state while in reset
|
always@(RST_I)
|
always@(RST_I)
|
begin
|
begin
|
if (RST_I)
|
if (RST_I)
|
begin
|
begin
|
DAT_O <= 32'hxxxx_xxxx ;
|
DAT_O <= 32'hxxxx_xxxx ;
|
end
|
end
|
end //reset
|
end //reset
|
|
|
// Data input/output interface
|
// Data input/output interface
|
always@(rd_sel or wr_sel or mem_rd_data_in or DAT_I or SEL_I or mem_wr_data_out)
|
always@(rd_sel or wr_sel or mem_rd_data_in or DAT_I or SEL_I or mem_wr_data_out)
|
begin
|
begin
|
if (rd_sel)
|
if (rd_sel)
|
begin
|
begin
|
DAT_O = mem_rd_data_in ;
|
DAT_O = mem_rd_data_in ;
|
end
|
end
|
end
|
end
|
always@(posedge CLK_I)
|
always@(posedge CLK_I)
|
begin
|
begin
|
if (wr_sel)
|
if (wr_sel)
|
begin
|
begin
|
mem_wr_data_out = wb_memory[ADR_I[11:2]] ;
|
mem_wr_data_out = wb_memory[ADR_I[11:2]] ;
|
|
|
if ( SEL_I[3] )
|
if ( SEL_I[3] )
|
mem_wr_data_out[31:24] = DAT_I[31:24] ;
|
mem_wr_data_out[31:24] = DAT_I[31:24] ;
|
|
|
if ( SEL_I[2] )
|
if ( SEL_I[2] )
|
mem_wr_data_out[23:16] = DAT_I[23:16] ;
|
mem_wr_data_out[23:16] = DAT_I[23:16] ;
|
|
|
if ( SEL_I[1] )
|
if ( SEL_I[1] )
|
mem_wr_data_out[15: 8] = DAT_I[15: 8] ;
|
mem_wr_data_out[15: 8] = DAT_I[15: 8] ;
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|
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if ( SEL_I[0] )
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if ( SEL_I[0] )
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mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0] ;
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mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0] ;
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|
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wb_memory[ADR_I[11:2]] <= mem_wr_data_out ;
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wb_memory[ADR_I[11:2]] <= mem_wr_data_out ;
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end
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end
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end
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end
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|
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endmodule
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endmodule
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|
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