//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// File name "wb_addr_mux.v" ////
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//// File name "wb_addr_mux.v" ////
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//// ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README ////
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//// All additional information is avaliable in the README ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////
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//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/08/19 16:54:25 mihad
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// Revision 1.4 2002/08/19 16:54:25 mihad
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// Got rid of undef directives
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// Got rid of undef directives
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//
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//
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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// module provides instantiation of address decoders and address multiplexer for various number of implemented wishbone images
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// module provides instantiation of address decoders and address multiplexer for various number of implemented wishbone images
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`include "pci_constants.v"
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`include "pci_constants.v"
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module pci_wb_addr_mux
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module pci_wb_addr_mux
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(
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(
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`ifdef REGISTER_WBS_OUTPUTS
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`ifdef REGISTER_WBS_OUTPUTS
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clk_in,
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clk_in,
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reset_in,
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reset_in,
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sample_address_in,
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sample_address_in,
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`endif
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`endif
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address_in,
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address_in,
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bar0_in,
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bar0_in,
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bar1_in,
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bar1_in,
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bar2_in,
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bar2_in,
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bar3_in,
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bar3_in,
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bar4_in,
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bar4_in,
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bar5_in,
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bar5_in,
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am0_in,
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am0_in,
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am1_in,
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am1_in,
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am2_in,
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am2_in,
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am3_in,
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am3_in,
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am4_in,
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am4_in,
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am5_in,
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am5_in,
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ta0_in,
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ta0_in,
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ta1_in,
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ta1_in,
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ta2_in,
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ta2_in,
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ta3_in,
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ta3_in,
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ta4_in,
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ta4_in,
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ta5_in,
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ta5_in,
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at_en_in,
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at_en_in,
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hit_out,
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hit_out,
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address_out
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address_out
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);
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);
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input [31:0] address_in ;
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input [31:0] address_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar0_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar0_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar1_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar1_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar2_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar2_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar3_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar3_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar4_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar4_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar5_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar5_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am0_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am0_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am1_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am1_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am2_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am2_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am3_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am3_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am4_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am4_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am5_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am5_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta0_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta0_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta1_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta1_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta2_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta2_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta3_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta3_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta4_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta4_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta5_in ;
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input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta5_in ;
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input [5:0] at_en_in ;
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input [5:0] at_en_in ;
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output [5:0] hit_out ;
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output [5:0] hit_out ;
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output [31:0] address_out ;
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output [31:0] address_out ;
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reg [31:0] address_out ;
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reg [31:0] address_out ;
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wire [31:0] addr0 ;
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wire [31:0] addr0 ;
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wire [31:0] addr1 ;
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wire [31:0] addr1 ;
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wire [31:0] addr2 ;
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wire [31:0] addr2 ;
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wire [31:0] addr3 ;
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wire [31:0] addr3 ;
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wire [31:0] addr4 ;
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wire [31:0] addr4 ;
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wire [31:0] addr5 ;
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wire [31:0] addr5 ;
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wire [5:0] hit ;
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wire [5:0] hit ;
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assign hit_out = hit ;
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assign hit_out = hit ;
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`ifdef REGISTER_WBS_OUTPUTS
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`ifdef REGISTER_WBS_OUTPUTS
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input clk_in, reset_in, sample_address_in ;
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input clk_in, reset_in, sample_address_in ;
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|
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reg [31:0] address ;
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reg [31:0] address ;
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always@(posedge clk_in or posedge reset_in)
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always@(posedge clk_in or posedge reset_in)
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begin
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begin
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if ( reset_in )
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if ( reset_in )
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address <= #`FF_DELAY 0 ;
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address <= #`FF_DELAY 0 ;
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else
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else
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if ( sample_address_in )
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if ( sample_address_in )
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address <= #`FF_DELAY address_in ;
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address <= #`FF_DELAY address_in ;
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end
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end
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`else
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`else
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wire [31:0] address = address_in ;
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wire [31:0] address = address_in ;
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`endif
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`endif
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`ifdef GUEST
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`ifdef GUEST
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`ifdef NO_CNF_IMAGE
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`ifdef NO_CNF_IMAGE
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`else
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`else
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`define PCI_WB_ADDR_MUX_DEC0_INCLUDE
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`define PCI_WB_ADDR_MUX_DEC0_INCLUDE
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`endif
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`endif
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`else
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`else
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`ifdef HOST
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`ifdef HOST
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`define PCI_WB_ADDR_MUX_DEC0_INCLUDE
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`define PCI_WB_ADDR_MUX_DEC0_INCLUDE
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`endif
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`endif
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`endif
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`endif
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`ifdef PCI_WB_ADDR_MUX_DEC0_INCLUDE
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`ifdef PCI_WB_ADDR_MUX_DEC0_INCLUDE
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pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec0
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pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec0
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(
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(
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.hit (hit[0]),
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.hit (hit[0]),
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.addr_out (addr0),
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.addr_out (addr0),
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.addr_in (address),
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.addr_in (address),
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.base_addr (bar0_in),
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.base_addr (bar0_in),
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.mask_addr (am0_in),
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.mask_addr (am0_in),
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.tran_addr (ta0_in),
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.tran_addr (ta0_in),
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.at_en (1'b0)
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.at_en (1'b0)
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) ;
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) ;
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`else
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`else
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// configuration image not implemented
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// configuration image not implemented
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assign hit[0] = 1'b0 ;
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assign hit[0] = 1'b0 ;
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assign addr0 = 32'h0000_0000 ;
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assign addr0 = 32'h0000_0000 ;
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`endif
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`endif
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// one image is always implemented
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// one image is always implemented
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pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec1
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pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec1
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(
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(
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.hit (hit[1]),
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.hit (hit[1]),
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.addr_out (addr1),
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.addr_out (addr1),
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.addr_in (address),
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.addr_in (address),
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.base_addr (bar1_in),
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.base_addr (bar1_in),
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.mask_addr (am1_in),
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.mask_addr (am1_in),
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.tran_addr (ta1_in),
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.tran_addr (ta1_in),
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.at_en (at_en_in[1])
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.at_en (at_en_in[1])
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) ;
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) ;
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`ifdef WB_IMAGE2
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`ifdef WB_IMAGE2
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pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec2
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pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec2
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(
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(
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.hit (hit[2]),
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.hit (hit[2]),
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.addr_out (addr2),
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.addr_out (addr2),
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.addr_in (address),
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.addr_in (address),
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.base_addr (bar2_in),
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.base_addr (bar2_in),
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.mask_addr (am2_in),
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.mask_addr (am2_in),
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.tran_addr (ta2_in),
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.tran_addr (ta2_in),
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.at_en (at_en_in[2])
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.at_en (at_en_in[2])
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) ;
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) ;
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`else
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`else
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assign hit[2] = 1'b0 ;
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assign hit[2] = 1'b0 ;
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assign addr2 = 0 ;
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assign addr2 = 0 ;
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`endif
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`endif
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`ifdef WB_IMAGE3
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`ifdef WB_IMAGE3
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pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec3
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pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec3
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(
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(
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.hit (hit[3]),
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.hit (hit[3]),
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.addr_out (addr3),
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.addr_out (addr3),
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.addr_in (address),
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.addr_in (address),
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.base_addr (bar3_in),
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.base_addr (bar3_in),
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.mask_addr (am3_in),
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.mask_addr (am3_in),
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.tran_addr (ta3_in),
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.tran_addr (ta3_in),
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.at_en (at_en_in[3])
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.at_en (at_en_in[3])
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) ;
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) ;
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`else
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`else
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assign hit[3] = 1'b0 ;
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assign hit[3] = 1'b0 ;
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assign addr3 = 0 ;
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assign addr3 = 0 ;
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`endif
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`endif
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`ifdef WB_IMAGE4
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`ifdef WB_IMAGE4
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pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec4
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pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec4
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(
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(
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.hit (hit[4]),
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.hit (hit[4]),
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.addr_out (addr4),
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.addr_out (addr4),
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.addr_in (address),
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.addr_in (address),
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.base_addr (bar4_in),
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.base_addr (bar4_in),
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.mask_addr (am4_in),
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.mask_addr (am4_in),
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.tran_addr (ta4_in),
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.tran_addr (ta4_in),
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.at_en (at_en_in[4])
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.at_en (at_en_in[4])
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) ;
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) ;
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`else
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`else
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assign hit[4] = 1'b0 ;
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assign hit[4] = 1'b0 ;
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assign addr4 = 0 ;
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assign addr4 = 0 ;
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`endif
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`endif
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`ifdef WB_IMAGE5
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`ifdef WB_IMAGE5
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pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec5
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pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec5
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(
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(
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.hit (hit[5]),
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.hit (hit[5]),
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.addr_out (addr5),
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.addr_out (addr5),
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.addr_in (address),
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.addr_in (address),
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.base_addr (bar5_in),
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.base_addr (bar5_in),
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.mask_addr (am5_in),
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.mask_addr (am5_in),
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.tran_addr (ta5_in),
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.tran_addr (ta5_in),
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.at_en (at_en_in[5])
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.at_en (at_en_in[5])
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) ;
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) ;
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`else
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`else
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assign hit[5] = 1'b0 ;
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assign hit[5] = 1'b0 ;
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assign addr5 = 0 ;
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assign addr5 = 0 ;
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`endif
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`endif
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// address multiplexer
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// address multiplexer
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always@
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always@
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(
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(
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hit or
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hit or
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addr0 or
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addr0 or
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addr1 or
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addr1 or
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addr2 or
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addr2 or
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addr3 or
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addr3 or
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addr4 or
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addr4 or
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addr5
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addr5
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)
|
)
|
begin
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begin
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case ( {hit[5:2], hit[0]} )
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case ( {hit[5:2], hit[0]} )
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5'b0_0_0_0_1: address_out = addr0 ;
|
5'b0_0_0_0_1: address_out = addr0 ;
|
5'b0_0_0_1_0: address_out = addr2 ;
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5'b0_0_0_1_0: address_out = addr2 ;
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5'b0_0_1_0_0: address_out = addr3 ;
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5'b0_0_1_0_0: address_out = addr3 ;
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5'b0_1_0_0_0: address_out = addr4 ;
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5'b0_1_0_0_0: address_out = addr4 ;
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5'b1_0_0_0_0: address_out = addr5 ;
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5'b1_0_0_0_0: address_out = addr5 ;
|
|
|
// default address is address from decoder 1 - it is always implemented - in case of stripped down core to only one image
|
// default address is address from decoder 1 - it is always implemented - in case of stripped down core to only one image
|
// this multiplexer can be completely removed during synthesys
|
// this multiplexer can be completely removed during synthesys
|
default: address_out = addr1 ;
|
default: address_out = addr1 ;
|
endcase
|
endcase
|
end
|
end
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|
|
endmodule
|
endmodule
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