/* Constraints */
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/* Constraints */
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CLK_UNCERTAINTY = 0.1 /* 100 ps */
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CLK_UNCERTAINTY = 0.1 /* 100 ps */
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DFFPQ2_CKQ = 0.2 /* Clk to Q in technology time units */
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DFFPQ2_CKQ = 0.2 /* Clk to Q in technology time units */
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DFFPQ2_SETUP = 0.1 /* Setup time in technology time units */
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DFFPQ2_SETUP = 0.1 /* Setup time in technology time units */
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|
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/* Clocks constraints */
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/* Clocks constraints */
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set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY
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set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY
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set_dont_touch_network all_clocks()
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set_dont_touch_network all_clocks()
|
|
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/* Reset constraints */
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/* Reset constraints */
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set_driving_cell -none RST
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set_driving_cell -none RST
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set_drive 0 RST
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set_drive 0 RST
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set_dont_touch_network RST
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set_dont_touch_network RST
|
|
|
/* All inputs except reset and clock */
|
/* All inputs except reset and clock */
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all_inputs_wo_rst_clk = all_inputs() - PCI_CLK - WB_CLK - RST
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all_inputs_wo_rst_clk = all_inputs() - PCI_CLK - WB_CLK - RST
|
|
|
/* Set output delays and load for output signals
|
/* Set output delays and load for output signals
|
*
|
*
|
* All outputs are assumed to go directly into
|
* All outputs are assumed to go directly into
|
* external flip-flops for the purpose of this
|
* external flip-flops for the purpose of this
|
* synthesis
|
* synthesis
|
*/
|
*/
|
set_load load_of(umcl18u250t2_typ/DFFPQ2/D) * 4 all_outputs()
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set_load load_of(umcl18u250t2_typ/DFFPQ2/D) * 4 all_outputs()
|
|
|
/* Input delay and driving cell of all inputs
|
/* Input delay and driving cell of all inputs
|
*
|
*
|
* All these signals are assumed to come directly from
|
* All these signals are assumed to come directly from
|
* flip-flops for the purpose of this synthesis
|
* flip-flops for the purpose of this synthesis
|
*
|
*
|
*/
|
*/
|
set_driving_cell -cell DFFPQ2 -pin Q all_inputs_wo_rst_clk
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set_driving_cell -cell DFFPQ2 -pin Q all_inputs_wo_rst_clk
|
|
|
/* Set design fanout */
|
/* Set design fanout */
|
/*
|
/*
|
set_max_fanout 10 TOPLEVEL
|
set_max_fanout 10 TOPLEVEL
|
*/
|
*/
|
|
|
/* Set area constraint */
|
/* Set area constraint */
|
set_max_area MAX_AREA
|
set_max_area MAX_AREA
|
|
|
set_operating_conditions -max WORST -max_library umcl18u250t2_wc
|
set_operating_conditions -max WORST -max_library umcl18u250t2_wc
|
|
|