#-- Synplicity, Inc.
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#-- Synplicity, Inc.
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#-- Version 7.2
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#-- Version 7.2
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#-- Project file /shared/projects/pci/mihad/pci/apps/crt/syn/synplify/pci_crt.prj
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#-- Project file /shared/projects/pci/mihad/pci/apps/crt/syn/synplify/pci_crt.prj
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#-- Written on Mon Mar 10 13:16:14 2003
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#-- Written on Mon Mar 10 13:16:14 2003
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#add_file options
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#add_file options
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add_file -verilog "$LIB/xilinx/virtex.v"
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add_file -verilog "$LIB/xilinx/virtex.v"
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add_file -verilog "../../../../rtl/verilog/meta_flop.v"
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add_file -verilog "../../../../rtl/verilog/meta_flop.v"
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add_file -verilog "../../../../rtl/verilog/pci_async_reset_flop.v"
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add_file -verilog "../../../../rtl/verilog/pci_async_reset_flop.v"
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add_file -verilog "../../../../rtl/verilog/pci_bridge32.v"
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add_file -verilog "../../../../rtl/verilog/pci_bridge32.v"
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add_file -verilog "../../../../rtl/verilog/pci_cbe_en_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_cbe_en_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_conf_cyc_addr_dec.v"
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add_file -verilog "../../../../rtl/verilog/pci_conf_cyc_addr_dec.v"
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add_file -verilog "../../../../rtl/verilog/pci_conf_space.v"
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add_file -verilog "../../../../rtl/verilog/pci_conf_space.v"
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add_file -verilog "../../../../rtl/verilog/pci_cur_out_reg.v"
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add_file -verilog "../../../../rtl/verilog/pci_cur_out_reg.v"
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add_file -verilog "../../../../rtl/verilog/pci_delayed_sync.v"
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add_file -verilog "../../../../rtl/verilog/pci_delayed_sync.v"
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add_file -verilog "../../../../rtl/verilog/pci_delayed_write_reg.v"
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add_file -verilog "../../../../rtl/verilog/pci_delayed_write_reg.v"
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add_file -verilog "../../../../rtl/verilog/pci_frame_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_frame_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_frame_en_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_frame_en_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_frame_load_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_frame_load_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_in_reg.v"
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add_file -verilog "../../../../rtl/verilog/pci_in_reg.v"
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add_file -verilog "../../../../rtl/verilog/pci_io_mux_ad_en_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_io_mux_ad_en_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_io_mux_ad_load_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_io_mux_ad_load_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_io_mux.v"
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add_file -verilog "../../../../rtl/verilog/pci_io_mux.v"
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add_file -verilog "../../../../rtl/verilog/pci_irdy_out_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_irdy_out_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_mas_ad_en_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_mas_ad_en_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_mas_ad_load_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_mas_ad_load_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_mas_ch_state_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_mas_ch_state_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_master32_sm_if.v"
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add_file -verilog "../../../../rtl/verilog/pci_master32_sm_if.v"
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add_file -verilog "../../../../rtl/verilog/pci_master32_sm.v"
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add_file -verilog "../../../../rtl/verilog/pci_master32_sm.v"
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add_file -verilog "../../../../rtl/verilog/pci_out_reg.v"
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add_file -verilog "../../../../rtl/verilog/pci_out_reg.v"
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add_file -verilog "../../../../rtl/verilog/pci_par_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_par_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_parity_check.v"
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add_file -verilog "../../../../rtl/verilog/pci_parity_check.v"
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add_file -verilog "../../../../rtl/verilog/pci_pci_decoder.v"
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add_file -verilog "../../../../rtl/verilog/pci_pci_decoder.v"
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add_file -verilog "../../../../rtl/verilog/pci_pcir_fifo_control.v"
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add_file -verilog "../../../../rtl/verilog/pci_pcir_fifo_control.v"
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add_file -verilog "../../../../rtl/verilog/pci_pci_tpram.v"
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add_file -verilog "../../../../rtl/verilog/pci_pci_tpram.v"
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add_file -verilog "../../../../rtl/verilog/pci_pciw_fifo_control.v"
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add_file -verilog "../../../../rtl/verilog/pci_pciw_fifo_control.v"
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add_file -verilog "../../../../rtl/verilog/pci_pciw_pcir_fifos.v"
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add_file -verilog "../../../../rtl/verilog/pci_pciw_pcir_fifos.v"
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add_file -verilog "../../../../rtl/verilog/pci_perr_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_perr_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_perr_en_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_perr_en_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_ram_16x40d.v"
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add_file -verilog "../../../../rtl/verilog/pci_ram_16x40d.v"
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add_file -verilog "../../../../rtl/verilog/pci_rst_int.v"
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add_file -verilog "../../../../rtl/verilog/pci_rst_int.v"
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add_file -verilog "../../../../rtl/verilog/pci_serr_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_serr_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_serr_en_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_serr_en_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_sync_module.v"
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add_file -verilog "../../../../rtl/verilog/pci_sync_module.v"
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add_file -verilog "../../../../rtl/verilog/pci_target32_clk_en.v"
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add_file -verilog "../../../../rtl/verilog/pci_target32_clk_en.v"
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add_file -verilog "../../../../rtl/verilog/pci_target32_devs_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_target32_devs_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_target32_interface.v"
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add_file -verilog "../../../../rtl/verilog/pci_target32_interface.v"
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add_file -verilog "../../../../rtl/verilog/pci_target32_sm.v"
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add_file -verilog "../../../../rtl/verilog/pci_target32_sm.v"
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add_file -verilog "../../../../rtl/verilog/pci_target32_stop_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_target32_stop_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_target32_trdy_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_target32_trdy_crit.v"
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add_file -verilog "../../../../rtl/verilog/pci_target_unit.v"
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add_file -verilog "../../../../rtl/verilog/pci_target_unit.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_addr_mux.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_addr_mux.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_decoder.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_decoder.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_master.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_master.v"
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add_file -verilog "../../../../rtl/verilog/pci_wbr_fifo_control.v"
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add_file -verilog "../../../../rtl/verilog/pci_wbr_fifo_control.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_slave_unit.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_slave_unit.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_slave.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_slave.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_tpram.v"
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add_file -verilog "../../../../rtl/verilog/pci_wb_tpram.v"
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add_file -verilog "../../../../rtl/verilog/pci_wbw_fifo_control.v"
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add_file -verilog "../../../../rtl/verilog/pci_wbw_fifo_control.v"
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add_file -verilog "../../../../rtl/verilog/pci_wbw_wbr_fifos.v"
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add_file -verilog "../../../../rtl/verilog/pci_wbw_wbr_fifos.v"
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add_file -verilog "../../../../rtl/verilog/synchronizer_flop.v"
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add_file -verilog "../../../../rtl/verilog/synchronizer_flop.v"
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add_file -verilog "../../rtl/verilog/crtc_iob.v"
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add_file -verilog "../../rtl/verilog/crtc_iob.v"
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add_file -verilog "../../rtl/verilog/ssvga_crtc.v"
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add_file -verilog "../../rtl/verilog/ssvga_crtc.v"
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add_file -verilog "../../rtl/verilog/ssvga_fifo.v"
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add_file -verilog "../../rtl/verilog/ssvga_fifo.v"
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add_file -verilog "../../rtl/verilog/ssvga_top.v"
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add_file -verilog "../../rtl/verilog/ssvga_top.v"
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add_file -verilog "../../rtl/verilog/ssvga_wbm_if.v"
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add_file -verilog "../../rtl/verilog/ssvga_wbm_if.v"
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add_file -verilog "../../rtl/verilog/ssvga_wbs_if.v"
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add_file -verilog "../../rtl/verilog/ssvga_wbs_if.v"
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add_file -constraint "pci_crt.sdc"
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add_file -constraint "pci_crt.sdc"
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add_file -verilog "../../rtl/verilog/top.v"
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add_file -verilog "../../rtl/verilog/top.v"
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#implementation: "rev_1"
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#implementation: "rev_1"
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impl -add rev_1
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impl -add rev_1
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#device options
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#device options
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set_option -technology SPARTAN2
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set_option -technology SPARTAN2
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set_option -part XC2S150
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set_option -part XC2S150
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set_option -package PQ208
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set_option -package PQ208
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set_option -speed_grade -5
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set_option -speed_grade -5
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#compilation/mapping options
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#compilation/mapping options
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set_option -default_enum_encoding default
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set_option -default_enum_encoding default
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set_option -symbolic_fsm_compiler 1
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set_option -symbolic_fsm_compiler 1
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set_option -resource_sharing 0
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set_option -resource_sharing 0
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set_option -use_fsm_explorer 0
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set_option -use_fsm_explorer 0
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#map options
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#map options
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set_option -frequency 50.000
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set_option -frequency 50.000
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set_option -fanout_limit 50
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set_option -fanout_limit 50
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set_option -disable_io_insertion 0
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set_option -disable_io_insertion 0
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set_option -pipe 1
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set_option -pipe 1
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set_option -retiming 1
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set_option -retiming 1
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set_option -modular 0
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set_option -modular 0
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set_option -update_models_cp 0
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set_option -update_models_cp 0
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set_option -verification_mode 0
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set_option -verification_mode 0
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#simulation options
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#simulation options
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set_option -write_verilog 0
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set_option -write_verilog 0
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set_option -write_vhdl 0
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set_option -write_vhdl 0
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#automatic place and route (vendor) options
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 1
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set_option -write_apr_constraint 1
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#set result format/file last
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#set result format/file last
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project -result_file "rev_1/top.edf"
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project -result_file "rev_1/top.edf"
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#implementation attributes
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#implementation attributes
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set_option -compiler_compatible 0
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set_option -compiler_compatible 0
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set_option -random_floorplan 0
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set_option -random_floorplan 0
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set_option -popfeed 1
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set_option -popfeed 1
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set_option -constprop 1
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set_option -constprop 1
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set_option -createhierarchy 0
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set_option -createhierarchy 0
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set_option -floorplan ""
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set_option -floorplan ""
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set_option -nfilter_user_path ""
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set_option -nfilter_user_path ""
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set_option -pin_assignment ""
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set_option -pin_assignment ""
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set_option -include_path "../../rtl/verilog/;../../../../rtl/verilog/"
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set_option -include_path "../../rtl/verilog/;../../../../rtl/verilog/"
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impl -active "rev_1"
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impl -active "rev_1"
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