// definition of maximum test application command length
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// definition of maximum test application command length
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#define MAX_COMMAND_LEN 100
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#define MAX_COMMAND_LEN 100
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#define MAX_DESCRIPTION_LEN 1000
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#define MAX_DESCRIPTION_LEN 1000
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#define NUM_OF_COMMANDS 15
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#define NUM_OF_COMMANDS 15
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char GSA_COMMANDS [NUM_OF_COMMANDS][MAX_COMMAND_LEN] = {
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char GSA_COMMANDS [NUM_OF_COMMANDS][MAX_COMMAND_LEN] = {
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"help",
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"help",
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"quit",
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"quit",
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"set_pci_region",
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"set_pci_region",
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"write",
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"write",
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"read",
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"read",
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"target_write",
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"target_write",
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"dump",
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"dump",
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"master_read",
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"master_read",
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"master_buf_fill",
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"master_buf_fill",
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"master_write",
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"master_write",
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"master_chk_write",
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"master_chk_write",
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"target_chk_write",
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"target_chk_write",
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"target_programmed_tests",
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"target_programmed_tests",
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"set_wb_region",
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"set_wb_region",
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"master_programmed_tests"
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"master_programmed_tests"
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} ;
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} ;
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char GSA_COMMAND_DESCRIPTIONS [NUM_OF_COMMANDS][MAX_DESCRIPTION_LEN] = {
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char GSA_COMMAND_DESCRIPTIONS [NUM_OF_COMMANDS][MAX_DESCRIPTION_LEN] = {
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"Displays basic command and parameter reference.",
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"Displays basic command and parameter reference.",
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"Exits the program.",
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"Exits the program.",
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"Selects one of 6 bridge pci address regions <region> for subsequent accesses.",
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"Selects one of 6 bridge pci address regions <region> for subsequent accesses.",
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"Writes 32 bit word <value> to specified offset <offset> and performs read-back.",
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"Writes 32 bit word <value> to specified offset <offset> and performs read-back.",
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"Reads data from the specified offset <offset>.",
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"Reads data from the specified offset <offset>.",
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"Initiates <number of transactions> write transactions with <transaction size> size. It starts from specified offset<offset>. <pattern> selects the pattern to write to on-board buffer.",
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"Initiates <number of transactions> write transactions with <transaction size> size. It starts from specified offset<offset>. <pattern> selects the pattern to write to on-board buffer.",
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"Reads 32 words from specified offset<offset>.",
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"Reads 32 words from specified offset<offset>.",
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"Configures master to read data from the system memory buffer. Reads start at specified offset <offset>, using <number of transactions> read operations of size <transaction size>.",
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"Configures master to read data from the system memory buffer. Reads start at specified offset <offset>, using <number of transactions> read operations of size <transaction size>.",
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"Fills system buffer with the specified pattern <pattern>.",
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"Fills system buffer with the specified pattern <pattern>.",
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"Writes contents of device's RAM on specified offset to system memory. Writes start at specified offset <offset>, using <number of transactions> write operations of size <transaction size>.",
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"Writes contents of device's RAM on specified offset to system memory. Writes start at specified offset <offset>, using <number of transactions> write operations of size <transaction size>.",
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"Checks <size> words of data in system memory from offset <offset> against a specified pattern <pattern>.",
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"Checks <size> words of data in system memory from offset <offset> against a specified pattern <pattern>.",
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"Checks data in onboard buffer from offset <offset> against a specified pattern. Buffer is read with <number of transactions> transactions of size <transaction size>.",
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"Checks data in onboard buffer from offset <offset> against a specified pattern. Buffer is read with <number of transactions> transactions of size <transaction size>.",
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"Performs arround 2M read/write transactions through target. Writes write pseudo random data, reads check the data.",
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"Performs arround 2M read/write transactions through target. Writes write pseudo random data, reads check the data.",
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"Enables WISHBONE image <image[1:5]> for subsequent PCI Master accesses. The command doesn't check for implemented WB images!",
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"Enables WISHBONE image <image[1:5]> for subsequent PCI Master accesses. The command doesn't check for implemented WB images!",
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"Executes the master test program code written in the function in the pci_bridge32_test.c file!"
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"Executes the master test program code written in the function in the pci_bridge32_test.c file!"
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} ;
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} ;
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char GSA_PARAMETERS [NUM_OF_COMMANDS][MAX_COMMAND_LEN] = {
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char GSA_PARAMETERS [NUM_OF_COMMANDS][MAX_COMMAND_LEN] = {
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"",
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"",
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"",
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"",
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"<region[0:5]>",
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"<region[0:5]>",
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"<offset> <value>",
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"<offset> <value>",
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"<offset>",
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"<offset>",
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"<starting offset> <number of transactions> <transaction size> <pattern>",
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"<starting offset> <number of transactions> <transaction size> <pattern>",
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"<offset>",
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"<offset>",
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"<offset> <number of transactions> <transaction size>",
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"<offset> <number of transactions> <transaction size>",
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"<pattern>",
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"<pattern>",
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"<offset> <number of transactions> <transaction size>",
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"<offset> <number of transactions> <transaction size>",
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"<offset> <size> <pattern>",
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"<offset> <size> <pattern>",
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"<offset> <number of transactions> <transaction size> <pattern>",
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"<offset> <number of transactions> <transaction size> <pattern>",
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"",
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"",
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"<image[1:5]>",
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"<image[1:5]>",
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""
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""
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} ;
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} ;
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#define GET_CMD(i) (GSA_COMMANDS[i])
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#define GET_CMD(i) (GSA_COMMANDS[i])
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#define GET_CMD_DES(i) (GSA_COMMAND_DESCRIPTIONS[i])
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#define GET_CMD_DES(i) (GSA_COMMAND_DESCRIPTIONS[i])
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#define GET_CMD_PARMS(i) (GSA_PARAMETERS[i])
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#define GET_CMD_PARMS(i) (GSA_PARAMETERS[i])
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#define SYS_BUFFER_SIZE (4096)
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#define SYS_BUFFER_SIZE (4096)
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#define SPARTAN_BOARD_BUFFER_SIZE (1024)
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#define SPARTAN_BOARD_BUFFER_SIZE (1024)
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#define TARGET_BUFFER_SIZE (1024)
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#define TARGET_BUFFER_SIZE (1024)
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#define MASTER_TRANS_SIZE_OFFSET (0x1000)
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#define MASTER_TRANS_SIZE_OFFSET (0x1000)
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#define MASTER_TRANS_COUNT_OFFSET (0x1004)
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#define MASTER_TRANS_COUNT_OFFSET (0x1004)
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#define MASTER_OP_CODE_OFFSET (0x1008)
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#define MASTER_OP_CODE_OFFSET (0x1008)
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#define MASTER_ADDR_REG_OFFSET (0x100c)
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#define MASTER_ADDR_REG_OFFSET (0x100c)
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#define TARGET_BURST_TRANS_CNT_OFFSET (0x1010)
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#define TARGET_BURST_TRANS_CNT_OFFSET (0x1010)
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#define TARGET_TEST_SIZE_OFFSET (0x1014)
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#define TARGET_TEST_SIZE_OFFSET (0x1014)
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#define TARGET_TEST_START_ADR_OFFSET (0x1018)
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#define TARGET_TEST_START_ADR_OFFSET (0x1018)
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#define TARGET_TEST_START_DATA_OFFSET (0x101C)
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#define TARGET_TEST_START_DATA_OFFSET (0x101C)
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#define TARGET_TEST_ERR_REP_OFFSET (0x1020)
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#define TARGET_TEST_ERR_REP_OFFSET (0x1020)
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#define MASTER_NUM_OF_WB_OFFSET (0x1024)
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#define MASTER_NUM_OF_WB_OFFSET (0x1024)
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#define MASTER_NUM_OF_PCI_OFFSET (0x1028)
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#define MASTER_NUM_OF_PCI_OFFSET (0x1028)
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#define MASTER_TEST_SIZE_OFFSET (0x102C)
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#define MASTER_TEST_SIZE_OFFSET (0x102C)
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#define MASTER_TEST_START_DATA_OFFSET (0x1030)
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#define MASTER_TEST_START_DATA_OFFSET (0x1030)
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#define MASTER_TEST_DATA_ERROR_OFFSET (0x1034)
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#define MASTER_TEST_DATA_ERROR_OFFSET (0x1034)
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