/* PCI input delay constraints definition*/
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/* PCI input delay constraints definition*/
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if ( PCI_CLK_PERIOD == 15 ){
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if ( PCI_CLK_PERIOD == 15 ){
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/* 3ns setup time constraint */
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/* 3ns setup time constraint */
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set_input_delay -max 12 -clock PCI_CLK {AD}
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set_input_delay -max 12 -clock PCI_CLK {AD}
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set_input_delay -max 12 -clock PCI_CLK {CBE}
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set_input_delay -max 12 -clock PCI_CLK {CBE}
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set_input_delay -max 12 -clock PCI_CLK {FRAME}
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set_input_delay -max 12 -clock PCI_CLK {FRAME}
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set_input_delay -max 12 -clock PCI_CLK {IRDY}
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set_input_delay -max 12 -clock PCI_CLK {IRDY}
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set_input_delay -max 12 -clock PCI_CLK {IDSEL}
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set_input_delay -max 12 -clock PCI_CLK {IDSEL}
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set_input_delay -max 12 -clock PCI_CLK {DEVSEL}
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set_input_delay -max 12 -clock PCI_CLK {DEVSEL}
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set_input_delay -max 12 -clock PCI_CLK {TRDY}
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set_input_delay -max 12 -clock PCI_CLK {TRDY}
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set_input_delay -max 12 -clock PCI_CLK {STOP}
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set_input_delay -max 12 -clock PCI_CLK {STOP}
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set_input_delay -max 12 -clock PCI_CLK {PAR}
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set_input_delay -max 12 -clock PCI_CLK {PAR}
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set_input_delay -max 12 -clock PCI_CLK {PERR}
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set_input_delay -max 12 -clock PCI_CLK {PERR}
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/* 0ns hold time constraints */
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/* 0ns hold time constraints */
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set_input_delay -min 0 -clock PCI_CLK {AD}
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set_input_delay -min 0 -clock PCI_CLK {AD}
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set_input_delay -min 0 -clock PCI_CLK {CBE}
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set_input_delay -min 0 -clock PCI_CLK {CBE}
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set_input_delay -min 0 -clock PCI_CLK {FRAME}
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set_input_delay -min 0 -clock PCI_CLK {FRAME}
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set_input_delay -min 0 -clock PCI_CLK {IRDY}
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set_input_delay -min 0 -clock PCI_CLK {IRDY}
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set_input_delay -min 0 -clock PCI_CLK {IDSEL}
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set_input_delay -min 0 -clock PCI_CLK {IDSEL}
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set_input_delay -min 0 -clock PCI_CLK {DEVSEL}
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set_input_delay -min 0 -clock PCI_CLK {DEVSEL}
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set_input_delay -min 0 -clock PCI_CLK {TRDY}
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set_input_delay -min 0 -clock PCI_CLK {TRDY}
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set_input_delay -min 0 -clock PCI_CLK {STOP}
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set_input_delay -min 0 -clock PCI_CLK {STOP}
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set_input_delay -min 0 -clock PCI_CLK {PAR}
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set_input_delay -min 0 -clock PCI_CLK {PAR}
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set_input_delay -min 0 -clock PCI_CLK {PERR}
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set_input_delay -min 0 -clock PCI_CLK {PERR}
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/* GNT has 5ns constraint */
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/* GNT has 5ns constraint */
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set_input_delay -max 10 -clock PCI_CLK {GNT}
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set_input_delay -max 10 -clock PCI_CLK {GNT}
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set_input_delay -min 0 -clock PCI_CLK {GNT}
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set_input_delay -min 0 -clock PCI_CLK {GNT}
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/* 6ns output delay constraints */
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/* 6ns output delay constraints */
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set_output_delay -max 9 -clock PCI_CLK {AD}
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set_output_delay -max 9 -clock PCI_CLK {AD}
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set_output_delay -max 9 -clock PCI_CLK {CBE}
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set_output_delay -max 9 -clock PCI_CLK {CBE}
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set_output_delay -max 9 -clock PCI_CLK {FRAME}
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set_output_delay -max 9 -clock PCI_CLK {FRAME}
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set_output_delay -max 9 -clock PCI_CLK {IRDY}
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set_output_delay -max 9 -clock PCI_CLK {IRDY}
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set_output_delay -max 9 -clock PCI_CLK {DEVSEL}
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set_output_delay -max 9 -clock PCI_CLK {DEVSEL}
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set_output_delay -max 9 -clock PCI_CLK {TRDY}
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set_output_delay -max 9 -clock PCI_CLK {TRDY}
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set_output_delay -max 9 -clock PCI_CLK {STOP}
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set_output_delay -max 9 -clock PCI_CLK {STOP}
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set_output_delay -max 9 -clock PCI_CLK {PAR}
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set_output_delay -max 9 -clock PCI_CLK {PAR}
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set_output_delay -max 9 -clock PCI_CLK {PERR}
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set_output_delay -max 9 -clock PCI_CLK {PERR}
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set_output_delay -max 9 -clock PCI_CLK {SERR}
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set_output_delay -max 9 -clock PCI_CLK {SERR}
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set_output_delay -max 9 -clock PCI_CLK {REQ}
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set_output_delay -max 9 -clock PCI_CLK {REQ}
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}else if ( PCI_CLK_PERIOD == 30 ){
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}else if ( PCI_CLK_PERIOD == 30 ){
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/* 7ns setup time constraint */
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/* 7ns setup time constraint */
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set_input_delay -max 23 -clock PCI_CLK {AD}
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set_input_delay -max 23 -clock PCI_CLK {AD}
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set_input_delay -max 23 -clock PCI_CLK {CBE}
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set_input_delay -max 23 -clock PCI_CLK {CBE}
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set_input_delay -max 23 -clock PCI_CLK {FRAME}
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set_input_delay -max 23 -clock PCI_CLK {FRAME}
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set_input_delay -max 23 -clock PCI_CLK {IRDY}
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set_input_delay -max 23 -clock PCI_CLK {IRDY}
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set_input_delay -max 23 -clock PCI_CLK {IDSEL}
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set_input_delay -max 23 -clock PCI_CLK {IDSEL}
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set_input_delay -max 23 -clock PCI_CLK {DEVSEL}
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set_input_delay -max 23 -clock PCI_CLK {DEVSEL}
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set_input_delay -max 23 -clock PCI_CLK {TRDY}
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set_input_delay -max 23 -clock PCI_CLK {TRDY}
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set_input_delay -max 23 -clock PCI_CLK {STOP}
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set_input_delay -max 23 -clock PCI_CLK {STOP}
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set_input_delay -max 23 -clock PCI_CLK {PAR}
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set_input_delay -max 23 -clock PCI_CLK {PAR}
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set_input_delay -max 23 -clock PCI_CLK {PERR}
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set_input_delay -max 23 -clock PCI_CLK {PERR}
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/* 0ns hold time constraints */
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/* 0ns hold time constraints */
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set_input_delay -min 0 -clock PCI_CLK {AD}
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set_input_delay -min 0 -clock PCI_CLK {AD}
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set_input_delay -min 0 -clock PCI_CLK {CBE}
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set_input_delay -min 0 -clock PCI_CLK {CBE}
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set_input_delay -min 0 -clock PCI_CLK {FRAME}
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set_input_delay -min 0 -clock PCI_CLK {FRAME}
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set_input_delay -min 0 -clock PCI_CLK {IRDY}
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set_input_delay -min 0 -clock PCI_CLK {IRDY}
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set_input_delay -min 0 -clock PCI_CLK {IDSEL}
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set_input_delay -min 0 -clock PCI_CLK {IDSEL}
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set_input_delay -min 0 -clock PCI_CLK {DEVSEL}
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set_input_delay -min 0 -clock PCI_CLK {DEVSEL}
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set_input_delay -min 0 -clock PCI_CLK {TRDY}
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set_input_delay -min 0 -clock PCI_CLK {TRDY}
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set_input_delay -min 0 -clock PCI_CLK {STOP}
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set_input_delay -min 0 -clock PCI_CLK {STOP}
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set_input_delay -min 0 -clock PCI_CLK {PAR}
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set_input_delay -min 0 -clock PCI_CLK {PAR}
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set_input_delay -min 0 -clock PCI_CLK {PERR}
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set_input_delay -min 0 -clock PCI_CLK {PERR}
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/* GNT has 10ns constraint */
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/* GNT has 10ns constraint */
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set_input_delay -max 20 -clock PCI_CLK {GNT}
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set_input_delay -max 20 -clock PCI_CLK {GNT}
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set_input_delay -min 0 -clock PCI_CLK {GNT}
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set_input_delay -min 0 -clock PCI_CLK {GNT}
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/* 11ns output delay constraints */
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/* 11ns output delay constraints */
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set_output_delay -max 19 -clock PCI_CLK {AD}
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set_output_delay -max 19 -clock PCI_CLK {AD}
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set_output_delay -max 19 -clock PCI_CLK {CBE}
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set_output_delay -max 19 -clock PCI_CLK {CBE}
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set_output_delay -max 19 -clock PCI_CLK {FRAME}
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set_output_delay -max 19 -clock PCI_CLK {FRAME}
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set_output_delay -max 19 -clock PCI_CLK {IRDY}
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set_output_delay -max 19 -clock PCI_CLK {IRDY}
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set_output_delay -max 19 -clock PCI_CLK {DEVSEL}
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set_output_delay -max 19 -clock PCI_CLK {DEVSEL}
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set_output_delay -max 19 -clock PCI_CLK {TRDY}
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set_output_delay -max 19 -clock PCI_CLK {TRDY}
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set_output_delay -max 19 -clock PCI_CLK {STOP}
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set_output_delay -max 19 -clock PCI_CLK {STOP}
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set_output_delay -max 19 -clock PCI_CLK {PAR}
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set_output_delay -max 19 -clock PCI_CLK {PAR}
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set_output_delay -max 19 -clock PCI_CLK {PERR}
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set_output_delay -max 19 -clock PCI_CLK {PERR}
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set_output_delay -max 19 -clock PCI_CLK {SERR}
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set_output_delay -max 19 -clock PCI_CLK {SERR}
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/* REQ has 12ns output delay constraint */
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/* REQ has 12ns output delay constraint */
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set_output_delay -max 12 -clock PCI_CLK {REQ}
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set_output_delay -max 12 -clock PCI_CLK {REQ}
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}else{
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}else{
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echo "Error: Unsupported PCI clock period specified!"
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echo "Error: Unsupported PCI clock period specified!"
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exit
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exit
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}
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}
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set_false_path -from PCI_CLK -to WB_CLK
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set_false_path -from PCI_CLK -to WB_CLK
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set_false_path -from WB_CLK -to PCI_CLK
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set_false_path -from WB_CLK -to PCI_CLK
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set_false_path -from {bridge/configuration/*} -to {SDAT_O}
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set_false_path -from {bridge/configuration/*} -to {SDAT_O}
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