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PCI Bridge IP Core
Introduction
Today, the PCI bus is the number-one device connectivity standard on the market to integrate modern embedded applications into bigger systems. The PCI Bridge IP Core is built according to PCI specification Rev. 2.2 (or lower) and provides a backend connection that is WISHBONE open-standard compatible. Since standardized backend is rarely seen in common IP cores, the architecture-independent interface, which can be used in a wide variety of applications, is the PCI Bride IP Cores major benefit.
Features
Figure 1: Core Architecture Overview
PCI Interface
PCI 2.2 compliant 32- bit, 33 or 66- MHz Initiator and Target interface
Zero wait state burst operation
Parameterized number of synthesizable, fully programmable images (default one, maximum 6 images) with address translation capability and 4KB to 1GB image size for access from PCI bus to address space on WISHBONE bus
Programmable image address space mapping (I/O or memory space)
In-core realization of PCI transaction ordering requirements; use of posted writes and delayed reads in either direction
Single delayed transaction support in either direction
Supported initiator functions:
Memory Read, Memory Read Line, Memory Read Multiple, Memory Write commands
IO Read and Write commands
Configuration Read and Write commands
Interrupt Acknowledge command
Support of linear burst ordering
Bus Parking
Supported Target functions:
Memory Read, Memory Read Line, Memory Read Multiple, Memory Write, Memory Write, and Invalidate commands
IO Read and Write commands
Configuration Read and Write commands
Support of linear burst ordering
Fast Back-to-Back Capable Target response
Software configurable support for memory access optimizing commands
Fully transparent WISHBONE interface operation, controllable on image by image basis with proper software settings of configuration registers
WISHBONE Interface
WISHBONE clock independent of PCI clock
WISHBONE SoC bus revision B.1 compliant with separate Master and Slave interfaces
Zero wait state burst operation
Parameterized number of synthesizable, fully programmable images (default one, maximum 5 images) with address translation capability and 4KB to 1GB image size provided for access from WISHBONE bus to address space on PCI bus
Fully transparent PCI bus command usage, controllable on image by image basis with proper settings of configuration registers
Core Internals
Provision of two possible parameterized implementations HOST (used for host bridging with WISHBONE SoC bus as host bus) and GUEST (used for expansion bus bridging with WISHBONE SoC bus as expansion bus)
Four synthesizable, dual port FIFOs with parameterized depth
Extended configuration space, implemented for additional software programmable features of the core
General Description
The PCI Bridge IP Core is PCI specification Rev. 2.2 compliant but can also be used in systems designed according to lower versions, since the PCI is backwards compatible. A set of pre-synthesis parameters is defined in a separate file and offers a wide variety of implementations from high performance to low cost (in terms of resource utilization). The Core is targeting FPGA as well as ASIC SoC implementations.
Utilization
The following table lists the cores intended applications.
TechnologyFPGA SizeSilicon AreaSpeedPower ConsumptionXILINX Spartan FPGA1300 slices + 6 Block Select+ RAMTBD33 MHz on 5 speed gradeTBDASICTBDTBDTBDTBD
(footnote continued)
PAGE
PAGE 2
PCI Bridge IP Core
PCI Bridge IP Core
Authors reserve the right to make changes in specifications at any time and without notice. The information in this publication is believed to be accurate and reliable. No responsibility, however, is assumed by the Authors for its use, nor for any infringements of patents or other rights of third parties resulting from its use.
DATA SHEET
EMBED Word.Picture.8
EMBED Visio.Drawing.6
( K Y m n o t z | } ~ x n
|
? + ' ' @ Times New Roman
UwUw 0
PCI Bridge IP Core
Introduction
Today, the PCI bus is the number-one device connectivity standard on the market to integrate modern embedded applications into bigger systems. The PCI Bridge IP Core is built according to PCI specification Rev. 2.2 (or lower) and provides a backend connection that is WISHBONE open-standard compatible. Since standardized backend is rarely seen in common IP cores, the architecture-independent interface, which can be used in a wide variety of applications, is the PCI Bride IP Cores major benefit.
Features
Figure 1: Core Architecture Overview
PCI Interface
PCI 2.2 compliant 32- bit, 33 or 66- MHz Initiator and Target interface
Zero wait state burst operation
Parameterized number of synthesizable, fully programmable images (default one, maximum 6 images) with address translation capability and 4KB to 1GB image size for access from PCI bus to address space on WISHBONE bus
Programmable image address space mapping (I/O or memory space)
In-core realization of PCI transaction ordering requirements; use of posted writes and delayed reads in either direction
Single delayed transaction support in either direction
Supported initiator functions:
Memory Read, Memory Read Line, Memory Read Multiple, Memory Write commands
IO Read and Write commands
Configuration Read and Write commands
Interrupt Acknowledge command
Support of linear burst ordering
Bus Parking
Supported Target functions:
Memory Read, Memory Read Line, Memory Read Multiple, Memory Write, Memory Write, and Invalidate commands
IO Read and Write commands
Configuration Read and Write commands
Support of linear burst ordering
Fast Back-to-Back Capable Target response
Software configurable support for memory access optimizing commands
Fully transparent WISHBONE interface operation, controllable on image by image basis with proper software settings of configuration registers
WISHBONE Interface
WISHBONE clock independent of PCI clock
WISHBONE SoC bus revision B.1 compliant with separate Master and Slave interfaces
Zero wait state burst operation
Parameterized number of synthesizable, fully programmable images (default one, maximum 5 images) with address translation capability and 4KB to 1GB image size provided for access from WISHBONE bus to address space on PCI bus
Fully transparent PCI bus command usage, controllable on image by image basis with proper settings of configuration registers
Core Internals
Provision of two possible parameterized implementations HOST (used for host bridging with WISHBONE SoC bus as host bus) and GUEST (used for expansion bus bridging with WISHBONE SoC bus as expansion bus)
Four synthesizable, dual port FIFOs with parameterized depth
Extended configuration space, implemented for additional software programmable features of the core
General Description
The PCI Bridge IP Core is PCI specification Rev. 2.2 compliant but can also be used in systems designed according to lower versions, since the PCI is backwards compatible. A set of pre-synthesis parameters is defined in a separate file and offers a wide variety of implementations from high performance to low cost (in terms of resource utilization). The Core is targeting FPGA as well as ASIC SoC implementations.
Utilization
The following table lists the cores intended applications.
TechnologyFPGA SizeSilicon AreaSpeedPower ConsumptionXILINX Spartan FPGA1300 slices + 6 Block Select+ RAMTBD33 MHz on 5 speed gradeTBDASICTBDTBDTBDTBD
(footnote continued)
PAGE
PAGE 2
PCI Bridge IP Core
PCI Bridge IP Core
Authors reserve the right to make changes in specifications at any time and without notice. The information in this publication is believed to be accurate and reliable. No responsibility, however, is assumed by the Authors for its use, nor for any infringements of patents or other rights of third parties resulting from its use.
DATA SHEET
EMBED Word.Picture.8
EMBED Visio.Drawing.6
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2
|
, ! B
2
|
, ! B
2
|
, c T - 2
|
, c T - 2
|
,
|
,
|
IO Read an < 7 % % * % ) % 2
|
IO Read an < 7 % % * % ) % 2
|
, 2
d Write commands e* O % % * ? ? % ) *
2
|
, 2
d Write commands e* O % % * ? ? % ) *
2
|
, % ' -
2
|
, % ' -
2
|
! B
2
|
! B
2
|
c T - 7 2
|
c T - 7 2
|
Configuration Read and Write 7 * ) ) ) % * ) 7 % % * % ) * O % ' 2
|
Configuration Read and Write 7 * ) ) ) % * ) 7 % % * % ) * O % ' 2
|
commands n% * ? ? % ) *
2
|
commands n% * ? ? % ) *
2
|
1
% ' -
2
|
1
% ' -
2
|
K
! B
2
|
K
! B
2
|
K
c T - 7 2
|
K
c T - 7 2
|
K
Interrupt Acknowledge command ) % ) * ; % ) ) * : % * ) % % * ? ? % ) *
2
|
K
Interrupt Acknowledge command ) % ) * ; % ) ) * : % * ) % % * ? ? % ) *
2
|
K
% ' -
2
|
K
% ' -
2
|
! B
2
|
! B
2
|
c T - ; 2
|
c T - ; 2
|
Support of linear burst ordering. ) * * * * ) % % * ) * * % ) )
2
|
Support of linear burst ordering. ) * * * * ) % % * ) * * % ) )
2
|
% ' -
2
|
% ' -
2
|
! B
2
|
! B
2
|
c T - 2
|
c T - 2
|
Bus Parkings8 ) / % ) ) )
2
|
Bus Parkings8 ) / % ) ) )
2
|
O
% ' -
|
O
% ' -
|
2
|
2
|
h
|
h
|
&
2
|
&
2
|
h
|
h
|
p - 4 2
|
p - 4 2
|
q" Supported Target functions:n. ) * * * % * 4 % ) % ) ) % * )
2
|
q" Supported Target functions:n. ) * * * % * 4 % ) % ) ) % * )
2
|
q % ' -
2
|
q % ' -
2
|
! B
2
|
! B
2
|
c T - : 2
|
c T - : 2
|
Memory Read, Memory Read Line, gJ % ? * ( > 7 % % * > J % ? * ( > 7 % % * > 2 ) % ' A 2
|
Memory Read, Memory Read Line, gJ % ? * ( > 7 % % * > J % ? * ( > 7 % % * > 2 ) % ' A 2
|
1 $ Memory Read Multiple, Memory Write, J % ? * ( 7 % % * J ) * % J % ? * ( O % ' 2
|
1 $ Memory Read Multiple, Memory Write, J % ? * ( 7 % % * J ) * % J % ? * ( O % ' 2
|
Memory WriteJ % ? * ( O % # 2
|
Memory WriteJ % ? * ( O % # 2
|
and Invalidate % ) * ) ) % * % % ' 2
|
and Invalidate % ) * ) ) % * % % ' 2
|
commands n% * ? ? % ) *
2
|
commands n% * ? ? % ) *
2
|
1
% ' -
2
|
1
% ' -
2
|
P! B
2
|
P! B
2
|
Pc T - 4 2
|
Pc T - 4 2
|
P IO Read and Write commands n < 7 % % * % ) * O % % * ? ? % ) *
2
|
P IO Read and Write commands n < 7 % % * % ) * O % % * ? ? % ) *
2
|
P % ' -
2
|
P % ' -
2
|
! B
2
|
! B
2
|
c T - 7 2
|
c T - 7 2
|
Configuration Read and Write 7 * ) ) ) % * ) 7 % % * % ) * O % ' 2
|
Configuration Read and Write 7 * ) ) ) % * ) 7 % % * % ) * O % ' 2
|
commands n% * ? ? % ) *
2
|
commands n% * ? ? % ) *
2
|
1
% ' -
2
|
1
% ' -
2
|
o! B
2
|
o! B
2
|
oc T - ; 2
|
oc T - ; 2
|
o Support of linear burst ordering. ) * * * * ) % % * ) * * % ) )
2
|
o Support of linear burst ordering. ) * * * * ) % % * ) * * % ) )
2
|
o % ' -
2
|
o % ' -
2
|
! B
2
|
! B
2
|
c T - 2
|
c T - 2
|
Fast Backn. % W 8 % % )
2
|
Fast Backn. % W 8 % % )
2
|
C
- 2
|
C
- 2
|
^
to *
2
|
^
to *
2
|
-o ) 2
|
-o ) 2
|
Back Capable Target 8 % % ) W 7 % * % * % W 4 % ) % ' 2
|
Back Capable Target 8 % % ) W 7 % * % * % W 4 % ) % ' 2
|
/ response % * * ) %
2
|
/ response % * * ) %
2
|
/ o% ' -
|
/ o% ' -
|
2
|
2
|
|
|
o&
2
|
o&
2
|
|
|
op - I 2
|
op - I 2
|
" ) Software configurable support for memory . * : % % ) % * ) ) ) % * % ) ) * * * ) * ( ? % ? * ( ' 2 2
|
" ) Software configurable support for memory . * : % % ) % * ) ) ) % * % ) ) * * * ) * ( ? % ? * ( ' 2 2
|
" access optimizing commands% % % % * * ? % ) ) % * ? ? % ) *
2
|
" access optimizing commands% % % % * * ? % ) ) % * ? ? % ) *
2
|
o% ' -
|
o% ' -
|
2
|
2
|
R
|
R
|
o&
2
|
o&
2
|
R
|
R
|
op - A 2
|
op - A 2
|
[" $ Fully transparent WISHBONE interface. ) ( L % ) * % % ) L O . < 8 < < 3 L ) % % % %
2
|
[" $ Fully transparent WISHBONE interface. ) ( L % ) * % % ) L O . < 8 < < 3 L ) % % % %
2
|
[ o ' J 2
|
[ o ' J 2
|
" * operation, controllable on image by image * * % % * ) ( % * ) * % * % ( * ) ( ? % ) % ( * ( ' ? % ) % ' F 2
|
" * operation, controllable on image by image * * % % * ) ( % * ) * % * % ( * ) ( ? % ) % ( * ( ' ? % ) % ' F 2
|
" ' basis with proper software settings of * % I : ) I * * * % I * : % % I % ) ) I * ' . 2
|
" ' basis with proper software settings of * % I : ) I * * * % I * : % % I % ) ) I * ' . 2
|
z" configuration registers % * ) ) ) % * ) % ) %
2
|
z" configuration registers % * ) ) ) % * ) % ) %
2
|
z o% '
2
|
z o% '
2
|
|
|
o% - ( 2
|
o% - ( 2
|
7
|
7
|
WISHBONE Interface W = B B H B = 8 3 $ 3 3 3 @ "Arial w@
|
WISHBONE Interface W = B B H B = 8 3 $ 3 3 3 @ "Arial w@
|
UwUw 0 -
2
|
UwUw 0 -
2
|
:9 / -
|
:9 / -
|
2
|
2
|
|
|
&
2
|
&
2
|
|
|
p - > 2
|
p - > 2
|
" " WISHBONE clock independent of PCI O . < 8 < < 3 E % * % ) E ) * % * % ) * % ) E * D / 7 ' 2
|
" " WISHBONE clock independent of PCI O . < 8 < < 3 E % * % ) E ) * % * % ) * % ) E * D / 7 ' 2
|
"" clock % * % )
2
|
"" clock % * % )
2
|
" % ' -
- -
! , -
-
-
*J
2
|
" % ' -
- -
! , -
-
-
*J
2
|
K J* % @ Times New Roman
UwUw 0 -
2
|
K J* % @ Times New Roman
UwUw 0 -
2
|
J* - 2
|
J* - 2
|
|
|
J*DATA SHEETH E = E C H C C =
2
|
J*DATA SHEETH E = E C H C C =
2
|
J* 8 ' &
.
|
J* 8 ' &
.
|
- - /D 1 _ _ - - Arial w@ f
|
- - /D 1 _ _ - - Arial w@ f
|
UwUw 0 - "System w@
|
UwUw 0 - "System w@
|
v
UwUw 0 -
|
v
UwUw 0 -
|
- - 1 $ N f f O N O N f - - - - $ 2GG22G - - Arial w@ f
|
- - 1 $ N f f O N O N f - - - - $ 2GG22G - - Arial w@ f
|
UwUw 0 - Arial w@
|
UwUw 0 - Arial w@
|
>
UwUw 0 - "System w@
|
>
UwUw 0 - "System w@
|
U
UwUw 0 - . - 2
|
U
UwUw 0 - . - 2
|
<
|
<
|
PCI MasterC H S 8 2 8 ! 2
|
PCI MasterC H S 8 2 8 ! 2
|
ModuleS 8 8 8 8 - - - $ 2 22 - - - Arial w@ 8
|
ModuleS 8 8 8 8 - - - $ 2 22 - - - Arial w@ 8
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
t <
|
t <
|
PCI TargetC H = 8 ! 8 8 2
|
PCI TargetC H = 8 ! 8 8 2
|
& ModuleS 8 8 8 8 - - - $ 2 3
3
2 2 3 - - - Arial w@
|
& ModuleS 8 8 8 8 - - - $ 2 3
3
2 2 3 - - - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
n; WISHBONE^ C H C N H C 2
|
n; WISHBONE^ C H C N H C 2
|
Slave ModuleC 8 2 8 S 8 8 8 8 - - - $ 2
2 2 - - - Arial w@ j
|
Slave ModuleC 8 2 8 S 8 8 8 8 - - - $ 2
2 2 - - - Arial w@ j
|
UwUw 0 - - - . - 2
|
UwUw 0 - - - . - 2
|
WISHBONE^ C H C N H C 2
|
WISHBONE^ C H C N H C 2
|
w MasterS 8 2 8 ! 2
|
w MasterS 8 2 8 ! 2
|
& ModuleS 8 8 8 8 - - - $ 233G2G23 - - Arial w@ f
|
& ModuleS 8 8 8 8 - - - $ 233G2G23 - - Arial w@ f
|
UwUw 0 - Arial w@
|
UwUw 0 - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
PCI Config.e7 < < . . . 2
|
PCI Config.e7 < < . . . 2
|
CYCLE< 6 < . 7 - - - $ 2 2 2 - - Arial w@
|
CYCLE< 6 < . 7 - - - $ 2 2 2 - - Arial w@
|
@
UwUw 0 - Arial w@
|
@
UwUw 0 - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
f Interrupt ack. . . . . . * + 2
|
f Interrupt ack. . . . . . * + 2
|
W CYCLE < 6 < . 7 - - - $ 222 - - Arial w@ 8
|
W CYCLE < 6 < . 7 - - - $ 222 - - Arial w@ 8
|
UwUw 0 - Arial w@
|
UwUw 0 - Arial w@
|
]
UwUw 0 - - . - 2
|
]
UwUw 0 - - . - 2
|
U PCI Config.e7 < < . . . 2
|
U PCI Config.e7 < < . . . 2
|
CYCLE< 6 < . 7 - - - $ >
|
CYCLE< 6 < . 7 - - - $ >
|
|
|
>> - - Arial w@ j
|
>> - - Arial w@ j
|
UwUw 0 - Arial w@
|
UwUw 0 - Arial w@
|
UwUw 0 - Arial w@ x
|
UwUw 0 - Arial w@ x
|
c
UwUw 0 - - - . - 2
|
c
UwUw 0 - - - . - 2
|
A WBR_FIFOO < < . 3 3 A - 2
|
A WBR_FIFOO < < . 3 3 A - 2
|
o WB from PCIeS 7 . G 7 < - - - $ 2n
|
o WB from PCIeS 7 . G 7 < - - - $ 2n
|
n
|
n
|
22n - - - Arial w@ f
|
22n - - - Arial w@ f
|
UwUw 0 - Arial w@
|
UwUw 0 - Arial w@
|
UwUw 0 - - - . - 2
|
UwUw 0 - - - . - 2
|
v WBW_FIFOO < O . 3 3 A - 2
|
v WBW_FIFOO < O . 3 3 A - 2
|
C WB to PCItS 7 . 7 < - - - $ 2
|
C WB to PCItS 7 . 7 < - - - $ 2
|
|
|
|
|
2
|
2
|
2 - - - Arial w@
|
2 - - - Arial w@
|
B
UwUw 0 - Arial w@
|
B
UwUw 0 - Arial w@
|
UwUw 0 - - - . - 2
|
UwUw 0 - - - . - 2
|
t
|
t
|
PCIR_FIFOt7 < < . 3 3 A - 2
|
PCIR_FIFOt7 < < . 3 3 A - 2
|
|
|
d PCI from WBe7 < . G S 7 - - - $ 2
|
d PCI from WBe7 < . G S 7 - - - $ 2
|
|
|
2 22 2 - - - Arial w@ 8
|
2 22 2 - - - Arial w@ 8
|
UwUw 0 - Arial w@
|
UwUw 0 - Arial w@
|
^
UwUw 0 - - . - 2
|
^
UwUw 0 - - . - 2
|
w PCIW_FIFOt7 < O . 3 3 A - 2
|
w PCIW_FIFOt7 < O . 3 3 A - 2
|
PCI to WBt7 < . S 7 - - - $ >n n >>n - - Arial w@
|
PCI to WBt7 < . S 7 - - - $ >n n >>n - - Arial w@
|
UwUw 0 - Arial w@ x
|
UwUw 0 - Arial w@ x
|
e
UwUw 0 - - . - 2
|
e
UwUw 0 - - . - 2
|
u
Configuration H 8 8 7 8 ! 8 8 8 2
|
u
Configuration H 8 8 7 8 ! 8 8 8 2
|
R Space C 8 8 2 8 - - - $ 2 2 2 - - Arial w@
|
R Space C 8 8 2 8 - - - $ 2 2 2 - - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
_ RESET U.< 7 7 7 4 < - - - $ 2Z2Z2 - - Arial w@
|
_ RESET U.< 7 7 7 4 < - - - $ 2Z2Z2 - - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
Error U.7 . < - - - $ 2 22 - - Arial w@
|
Error U.7 . < - - - $ 2 22 - - Arial w@
|
C
UwUw 0 - - . - 2
|
C
UwUw 0 - - . - 2
|
Interrupt U. . . . . < - - - $ F
|
Interrupt U. . . . . < - - - $ F
|
FF
|
FF
|
FF
|
FF
|
- - Arial w@ 8
|
- - Arial w@ 8
|
UwUw 0 - Arial w@ j
|
UwUw 0 - Arial w@ j
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
wA PCIC H 2
|
wA PCIC H 2
|
R I/O N - - - $ > nn>nng g > - - Arial w@
|
R I/O N - - - $ > nn>nng g > - - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
RL System- ! " % 9 - - - $ Z 2 n2 nZ n n Z - - Arial w@
|
RL System- ! " % 9 - - - $ Z 2 n2 nZ n n Z - - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
n $ Arbitration.- % % % % - - - $ FZZ2F - - - - $ F B q q B 2 F - - - - $ 2n'VFVF2n - - - - $ F22vF - -
|
n $ Arbitration.- % % % % - - - $ FZZ2F - - - - $ F B q q B 2 F - - - - $ 2n'VFVF2n - - - - $ F22vF - -
|
- % u - - - - , $ 2}zv2 - - - - , $ Fvz}~}}}}}}~F - -
|
- % u - - - - , $ 2}zv2 - - - - , $ Fvz}~}}}}}}~F - -
|
- % RuR - - - - , $ 2Rqnjgc_\XTPMIEA>:732R - - - - , $ FR37:>A~E}I}M}P}T}X}\~_cgjnqFR - -
|
- % RuR - - - - , $ 2Rqnjgc_\XTPMIEA>:732R - - - - , $ FR37:>A~E}I}M}P}T}X}\~_cgjnqFR - -
|
- % u - - - - , $ 22 - - - - , $ F~}}}}}}~F - - - - $ '>'n??n' - - - - $ 2
|
- % u - - - - , $ 22 - - - - , $ F~}}}}}}~F - - - - $ '>'n??n' - - - - $ 2
|
+
|
+
|
|
|
|
|
F
|
F
|
2 - - Arial w@
|
2 - - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
D PCI Read Address- 0 0 % % % - % % % " " - - - $ 2 b 2 - - - - " $ r ; ; - nQ - - - z p ` V F < , " v l \ R B 8 ( # * 5 < G N Y ` k r b X H > ; ; ; ; ; ; ; # ; 3 ; = ; M ; W ; g ; q ; ; ; ; ; ; ; ; ; ; ; ;
; ; ' ; 7 ; A ; Q ; [ ; k ; u ; ; ; ; ; ; ; - # y n y n u { o h \ U Q \ f v - - - Arial w@
|
D PCI Read Address- 0 0 % % % - % % % " " - - - $ 2 b 2 - - - - " $ r ; ; - nQ - - - z p ` V F < , " v l \ R B 8 ( # * 5 < G N Y ` k r b X H > ; ; ; ; ; ; ; # ; 3 ; = ; M ; W ; g ; q ; ; ; ; ; ; ; ; ; ; ; ;
; ; ' ; 7 ; A ; Q ; [ ; k ; u ; ; ; ; ; ; ; - # y n y n u { o h \ U Q \ f v - - - Arial w@
|
D
UwUw 0 - - . - 2
|
D
UwUw 0 - - . - 2
|
% PCI HOSTC H H N C > - - - $ Z nnZnGn G - - Arial w@ x
|
% PCI HOSTC H H N C > - - - $ Z nnZnGn G - - Arial w@ x
|
f
UwUw 0 - - . - 2
|
f
UwUw 0 - - . - 2
|
& Addr/Datat- % % 0 % % - - - $ v nnvnbn b - - Arial w@ 8
|
& Addr/Datat- % % 0 % % - - - $ v nnvnbn b - - Arial w@ 8
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
Q ControlT0 % % % - - - $ nnn~n0 0 ~ - - Arial w@
|
Q ControlT0 % % % - - - $ nnn~n0 0 ~ - - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
@ Interruptt % % % % - - - $ # nn#nnK K # - - Arial w@
|
@ Interruptt % % % % - - - $ # nn#nnK K # - - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
7r Error - % - - - $ #2#2 a a#h#hnnnn# - - - - $ 6 #j<6 <6 e e M 6 - - - - $ ?22 - - - - $ >ZBBss>Z - - - - $
|
7r Error - % - - - $ #2#2 a a#h#hnnnn# - - - - $ 6 #j<6 <6 e e M 6 - - - - $ ?22 - - - - $ >ZBBss>Z - - - - $
|
|
|
?
|
?
|
2 2
|
2 2
|
|
|
|
|
- - - - $ 2 Z
|
- - - - $ 2 Z
|
|
|
B
|
B
|
B
|
B
|
s
|
s
|
s
|
s
|
2 Z - - - - $ ;k2 k2 ; - - Arial w@ j
|
2 Z - - - - $ ;k2 k2 ; - - Arial w@ j
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
OD WB Read AddressB - 0 % % % - % % % " " - - - $ b$2 $2 - - Arial w@
|
OD WB Read AddressB - 0 % % % - % % % " " - - - $ b$2 $2 - - Arial w@
|
F
UwUw 0 - - . - - - - $
Z
2Y2YZYY
Z - - Arial w@ x
|
F
UwUw 0 - - . - - - - $
Z
2Y2YZYY
Z - - Arial w@ x
|
g
UwUw 0 - - . -
2
|
g
UwUw 0 - - . -
2
|
na Data0 % % - - - $
G
YYGY3Y
3
- - Arial w@ 8
|
na Data0 % % - - - $
G
YYGY3Y
3
- - Arial w@ 8
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
< ControlT0 % % % - - - $
n
- - Arial w@
|
< ControlT0 % % % - - - $
n
- - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
, AddressT- % % % " " - - - $
|
, AddressT- % % % " " - - - $
|
|
|
|
|
2
|
2
|
2u
|
2u
|
u
|
u
|
F
|
F
|
|
|
- - - - $ 2
|
- - - - $ 2
|
b
|
b
|
|
|
|
|
|
|
|
|
2 - - - - $
|
2 - - - - $
|
|
|
|
|
|
|
|
|
|
|
2
|
2
|
2 u
|
2 u
|
|
|
u
|
u
|
|
|
F
|
F
|
|
|
|
|
- - - - $ \ | 3 \ \ a a a Va \ - - - - $ Z YY2
2
Y Y Z - - Arial w@
|
- - - - $ \ | 3 \ \ a a a Va \ - - - - $ Z YY2
2
Y Y Z - - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
n , AddressT- % % % " " - - - $
|
n , AddressT- % % % " " - - - $
|
|
|
Y
|
Y
|
YY
|
YY
|
Y
|
Y
|
|
|
Y
|
Y
|
Y
|
Y
|
|
|
|
|
|
|
- - Arial w@ j
|
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7 @CJ< OJ QJ kH: : F o o t e r F i r s t 8 X&d 5 8 8 F o o t e r E v e n 9 X&d 5 6 6
|
F o o t e r O d d : X&d 5 , , H e a d e r F i r s t ; * * H e a d e r E v e n < ( (
|
F o o t e r O d d : X&d 5 , , H e a d e r F i r s t ; * * H e a d e r E v e n < ( (
|
H e a d e r O d d = J J
C h a p t e r L a b e l
|
H e a d e r O d d = J J
C h a p t e r L a b e l
|
> @CJ< OJ QJ kHX X
C h a p t e r T i t l e ? pd ]p @CJ< OJ QJ kHJ J C h a p t e r S u b t i t l e @ d 6@CJ" < C < B o d y T e x t I n d e n t
|
> @CJ< OJ QJ kHX X
C h a p t e r T i t l e ? pd ]p @CJ< OJ QJ kHJ J C h a p t e r S u b t i t l e @ d 6@CJ" < C < B o d y T e x t I n d e n t
|
A ^ > J@1> S u b t i t l e B d 6@CJ" H >@ "H T i t l e C pd ]p @CJ< OJ QJ kH6 = B6
L i s t N u m b e r 5
|
A ^ > J@1> S u b t i t l e B d 6@CJ" H >@ "H T i t l e C pd ]p @CJ< OJ QJ kH6 = B6
L i s t N u m b e r 5
|
D ^ 6 < R6
L i s t N u m b e r 4
|
D ^ 6 < R6
L i s t N u m b e r 4
|
E @ ^@ 6 ; b6
L i s t N u m b e r 3
|
E @ ^@ 6 ; b6
L i s t N u m b e r 3
|
F ^ 6 9 r6
L i s t B u l l e t 5
|
F ^ 6 9 r6
L i s t B u l l e t 5
|
G ^ 6 8 6
L i s t B u l l e t 4
|
G ^ 6 8 6
L i s t B u l l e t 4
|
H @ ^@ 6 7 6
L i s t B u l l e t 3
|
H @ ^@ 6 7 6
L i s t B u l l e t 3
|
I ^ 6 6 6
L i s t B u l l e t 2
|
I ^ 6 6 6
L i s t B u l l e t 2
|
J p^p ( 5 ( L i s t 5
|
J p^p ( 5 ( L i s t 5
|
K @ ^@ ( 4 ( L i s t 4
|
K @ ^@ ( 4 ( L i s t 4
|
L ^ ( 3 ( L i s t 3
|
L ^ ( 3 ( L i s t 3
|
M p^p ( 2 ( L i s t 2
|
M p^p ( 2 ( L i s t 2
|
N ^ 4 X@4 E m p h a s i s 5@OJ QJ kH 6 '@6 C o m m e n t R e f e r e n c e CJ , , C o m m e n t T e x t Q 6 : "6
L i s t N u m b e r 2
|
N ^ 4 X@4 E m p h a s i s 5@OJ QJ kH 6 '@6 C o m m e n t R e f e r e n c e CJ , , C o m m e n t T e x t Q 6 : "6
L i s t N u m b e r 2
|
R p^p D 2
L i s t C o n t i n u e p S
|
R p^p D 2
L i s t C o n t i n u e p S
|
& F >T . ^` : E 1B: L i s t C o n t i n u e 2
|
& F >T . ^` : E 1B: L i s t C o n t i n u e 2
|
T p^p : F 1R: L i s t C o n t i n u e 3
|
T p^p : F 1R: L i s t C o n t i n u e 3
|
U ^ : G 1b: L i s t C o n t i n u e 4
|
U ^ : G 1b: L i s t C o n t i n u e 4
|
V @ ^@ : H 1r: L i s t C o n t i n u e 5
|
V @ ^@ : H 1r: L i s t C o n t i n u e 5
|
W ^ : :
N o r m a l I n d e n t
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W ^ : :
N o r m a l I n d e n t
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X ^ 0J
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X ^ 0J
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^ ^ R e t u r n A d d r e s s , Y $ d $p&#$+D0$^ CJ ( O ( S l o g a n 6@CJ 0 Oa0 C o m p a n y N a m e [ D D
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^ ^ R e t u r n A d d r e s s , Y $ d $p&#$+D0$^ CJ ( O ( S l o g a n 6@CJ 0 Oa0 C o m p a n y N a m e [ D D
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P a r t L a b e l
|
P a r t L a b e l
|
\ @CJ< OJ QJ kH
|
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i 0 @ 0 N o r m a l _HmH sH tH T @ T H e a d i n g 1 hd -D @& `h 5@CJ EH * @ * H e a d i n g 2 5 & & H e a d i n g 3 6 6 H e a d i n g 4
|
i 0 @ 0 N o r m a l _HmH sH tH T @ T H e a d i n g 1 hd -D @& `h 5@CJ EH * @ * H e a d i n g 2 5 & & H e a d i n g 3 6 6 H e a d i n g 4
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F o o t n o t e B a s e $d CJ Z "Z B l o c k Q u o t a t i o n % $< %d$&d0]^ 6 4 O24 B o d y T e x t K e e p $ > "@Q> C a p t i o n $d < a$ 6CJ & O B& P i c t u r e $ H O H D o c u m e n t L a b e l @CJ< OJ QJ kH8 *@ 8 E n d n o t e R e f e r e n c e 5H*, + , E n d n o t e T e x t : @: F o o t e r
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& F ] 1 L i s t N u m b e r p *
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& F>T 8 h . ]^ 4 - 4
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M a c r o T e x t + OJ QJ kH: )@ : P a g e N u m b e r 5CJ OJ QJ kH \ \ S u b t i t l e C o v e r - d ] 56@CJ( OJ QJ kH@ @ T i t l e C o v e r . d 5@CJH , O, S u p e r s c r i p t 5H*J J T O C B a s e 0
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M a c r o T e x t + OJ QJ kH: )@ : P a g e N u m b e r 5CJ OJ QJ kH \ \ S u b t i t l e C o v e r - d ] 56@CJ( OJ QJ kH@ @ T i t l e C o v e r . d 5@CJH , O, S u p e r s c r i p t 5H*J J T O C B a s e 0
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d ^ OJ QJ kHL # L T a b l e o f F i g u r e s 1 ] ^` @ "@ T O C 1 2
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d ^ OJ QJ kHL # L T a b l e o f F i g u r e s 1 ] ^` @ "@ T O C 1 2
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] ^ 5@ 8 28 T O C 2 3
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7 @CJ< OJ QJ kH: : F o o t e r F i r s t 8 X&d 5 8 8 F o o t e r E v e n 9 X&d 5 6 6
|
7 @CJ< OJ QJ kH: : F o o t e r F i r s t 8 X&d 5 8 8 F o o t e r E v e n 9 X&d 5 6 6
|
F o o t e r O d d : X&d 5 , , H e a d e r F i r s t ; * * H e a d e r E v e n < ( (
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F o o t e r O d d : X&d 5 , , H e a d e r F i r s t ; * * H e a d e r E v e n < ( (
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H e a d e r O d d = J J
C h a p t e r L a b e l
|
H e a d e r O d d = J J
C h a p t e r L a b e l
|
> @CJ< OJ QJ kHX X
C h a p t e r T i t l e ? pd ]p @CJ< OJ QJ kHJ J C h a p t e r S u b t i t l e @ d 6@CJ" < C < B o d y T e x t I n d e n t
|
> @CJ< OJ QJ kHX X
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|
A ^ > J@1> S u b t i t l e B d 6@CJ" H >@ "H T i t l e C pd ]p @CJ< OJ QJ kH6 = B6
L i s t N u m b e r 5
|
A ^ > J@1> S u b t i t l e B d 6@CJ" H >@ "H T i t l e C pd ]p @CJ< OJ QJ kH6 = B6
L i s t N u m b e r 5
|
D ^ 6 < R6
L i s t N u m b e r 4
|
D ^ 6 < R6
L i s t N u m b e r 4
|
E @ ^@ 6 ; b6
L i s t N u m b e r 3
|
E @ ^@ 6 ; b6
L i s t N u m b e r 3
|
F ^ 6 9 r6
L i s t B u l l e t 5
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F ^ 6 9 r6
L i s t B u l l e t 5
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G ^ 6 8 6
L i s t B u l l e t 4
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G ^ 6 8 6
L i s t B u l l e t 4
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H @ ^@ 6 7 6
L i s t B u l l e t 3
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H @ ^@ 6 7 6
L i s t B u l l e t 3
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I ^ 6 6 6
L i s t B u l l e t 2
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L i s t B u l l e t 2
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J p^p ( 5 ( L i s t 5
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J p^p ( 5 ( L i s t 5
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K @ ^@ ( 4 ( L i s t 4
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K @ ^@ ( 4 ( L i s t 4
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L ^ ( 3 ( L i s t 3
|
L ^ ( 3 ( L i s t 3
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M p^p ( 2 ( L i s t 2
|
M p^p ( 2 ( L i s t 2
|
N ^ 4 X@4 E m p h a s i s 5@OJ QJ kH 6 '@6 C o m m e n t R e f e r e n c e CJ , , C o m m e n t T e x t Q 6 : "6
L i s t N u m b e r 2
|
N ^ 4 X@4 E m p h a s i s 5@OJ QJ kH 6 '@6 C o m m e n t R e f e r e n c e CJ , , C o m m e n t T e x t Q 6 : "6
L i s t N u m b e r 2
|
R p^p D 2
L i s t C o n t i n u e p S
|
R p^p D 2
L i s t C o n t i n u e p S
|
& F >T . ^` : E 1B: L i s t C o n t i n u e 2
|
& F >T . ^` : E 1B: L i s t C o n t i n u e 2
|
T p^p : F 1R: L i s t C o n t i n u e 3
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T p^p : F 1R: L i s t C o n t i n u e 3
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U ^ : G 1b: L i s t C o n t i n u e 4
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U ^ : G 1b: L i s t C o n t i n u e 4
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V @ ^@ : H 1r: L i s t C o n t i n u e 5
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V @ ^@ : H 1r: L i s t C o n t i n u e 5
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^ ^ R e t u r n A d d r e s s , Y $ d $p&#$+D0$^ CJ ( O ( S l o g a n 6@CJ 0 Oa0 C o m p a n y N a m e [ D D
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|
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k ^ L@ D a t e l ` $ ` E n v e l o p e A d d r e s s ! m @ &+D/ ^@ CJ OJ QJ : % : E n v e l o p e R e t u r n n OJ QJ 2 2
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k ^ L@ D a t e l ` $ ` E n v e l o p e A d d r e s s ! m @ &+D/ ^@ CJ OJ QJ : % : E n v e l o p e R e t u r n n OJ QJ 2 2
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2
|
n&
2
|
|
|
np - O 2
|
np - O 2
|
" - Single delayed transaction support in either . ) ) % ! * % % ( % * ! % ) % % * ) ! ) * * * ! ) % ) % ' 2
|
" - Single delayed transaction support in either . ) ) % ! * % % ( % * ! % ) % % * ) ! ) * * * ! ) % ) % ' 2
|
G
|
G
|
" direction * % % * )
2
|
" direction * % % * )
2
|
G
|
G
|
J n% ' -
|
J n% ' -
|
2
|
2
|
|
|
|
|
n&
2
|
n&
2
|
|
|
|
|
np - 8 2
|
np - 8 2
|
|
|
" Supported initiator functions:. ) * * * % * ) % * ) ) % * )
2
|
" Supported initiator functions:. ) * * * % * ) % * ) ) % * )
2
|
|
|
n% ' @ Wingdings
|
n% ' @ Wingdings
|
=
UwUw 0 -
2
|
=
UwUw 0 -
2
|
! B
2
|
! B
2
|
c T - : 2
|
c T - : 2
|
Memory Read, Memory Read Line, J % ? * ( > 7 % % * > J % ? * ( > 7 % % * > 2 ) % ' @ 2
|
Memory Read, Memory Read Line, J % ? * ( > 7 % % * > J % ? * ( > 7 % % * > 2 ) % ' @ 2
|
l # Memory Read Multiple, Memory Write oJ % ? * ( 7 % % * J ) * % J % ? * ( O % ' 2
|
l # Memory Read Multiple, Memory Write oJ % ? * ( 7 % % * J ) * % J % ? * ( O % ' 2
|
commands % * ? ? % ) *
2
|
commands % * ? ? % ) *
2
|
1
% ' -
2
|
1
% ' -
2
|
, ! B
2
|
, ! B
2
|
, c T - 2
|
, c T - 2
|
,
|
,
|
IO Read an < 7 % % * % ) % 2
|
IO Read an < 7 % % * % ) % 2
|
, 2
d Write commands e* O % % * ? ? % ) *
2
|
, 2
d Write commands e* O % % * ? ? % ) *
2
|
, % ' -
2
|
, % ' -
2
|
! B
2
|
! B
2
|
c T - 7 2
|
c T - 7 2
|
Configuration Read and Write 7 * ) ) ) % * ) 7 % % * % ) * O % ' 2
|
Configuration Read and Write 7 * ) ) ) % * ) 7 % % * % ) * O % ' 2
|
commands n% * ? ? % ) *
2
|
commands n% * ? ? % ) *
2
|
1
% ' -
2
|
1
% ' -
2
|
K
! B
2
|
K
! B
2
|
K
c T - 7 2
|
K
c T - 7 2
|
K
Interrupt Acknowledge command ) % ) * ; % ) ) * : % * ) % % * ? ? % ) *
2
|
K
Interrupt Acknowledge command ) % ) * ; % ) ) * : % * ) % % * ? ? % ) *
2
|
K
% ' -
2
|
K
% ' -
2
|
! B
2
|
! B
2
|
c T - ; 2
|
c T - ; 2
|
Support of linear burst ordering. ) * * * * ) % % * ) * * % ) )
2
|
Support of linear burst ordering. ) * * * * ) % % * ) * * % ) )
2
|
% ' -
2
|
% ' -
2
|
! B
2
|
! B
2
|
c T - 2
|
c T - 2
|
Bus Parkings8 ) / % ) ) )
2
|
Bus Parkings8 ) / % ) ) )
2
|
O
% ' -
|
O
% ' -
|
2
|
2
|
h
|
h
|
&
2
|
&
2
|
h
|
h
|
p - 4 2
|
p - 4 2
|
q" Supported Target functions:n. ) * * * % * 4 % ) % ) ) % * )
2
|
q" Supported Target functions:n. ) * * * % * 4 % ) % ) ) % * )
2
|
q % ' -
2
|
q % ' -
2
|
! B
2
|
! B
2
|
c T - : 2
|
c T - : 2
|
Memory Read, Memory Read Line, gJ % ? * ( > 7 % % * > J % ? * ( > 7 % % * > 2 ) % ' A 2
|
Memory Read, Memory Read Line, gJ % ? * ( > 7 % % * > J % ? * ( > 7 % % * > 2 ) % ' A 2
|
1 $ Memory Read Multiple, Memory Write, J % ? * ( 7 % % * J ) * % J % ? * ( O % ' 2
|
1 $ Memory Read Multiple, Memory Write, J % ? * ( 7 % % * J ) * % J % ? * ( O % ' 2
|
Memory WriteJ % ? * ( O % # 2
|
Memory WriteJ % ? * ( O % # 2
|
and Invalidate % ) * ) ) % * % % ' 2
|
and Invalidate % ) * ) ) % * % % ' 2
|
commands n% * ? ? % ) *
2
|
commands n% * ? ? % ) *
2
|
1
% ' -
2
|
1
% ' -
2
|
P! B
2
|
P! B
2
|
Pc T - 4 2
|
Pc T - 4 2
|
P IO Read and Write commands n < 7 % % * % ) * O % % * ? ? % ) *
2
|
P IO Read and Write commands n < 7 % % * % ) * O % % * ? ? % ) *
2
|
P % ' -
2
|
P % ' -
2
|
! B
2
|
! B
2
|
c T - 7 2
|
c T - 7 2
|
Configuration Read and Write 7 * ) ) ) % * ) 7 % % * % ) * O % ' 2
|
Configuration Read and Write 7 * ) ) ) % * ) 7 % % * % ) * O % ' 2
|
commands n% * ? ? % ) *
2
|
commands n% * ? ? % ) *
2
|
1
% ' -
2
|
1
% ' -
2
|
o! B
2
|
o! B
2
|
oc T - ; 2
|
oc T - ; 2
|
o Support of linear burst ordering. ) * * * * ) % % * ) * * % ) )
2
|
o Support of linear burst ordering. ) * * * * ) % % * ) * * % ) )
2
|
o % ' -
2
|
o % ' -
2
|
! B
2
|
! B
2
|
c T - 2
|
c T - 2
|
Fast Backn. % W 8 % % )
2
|
Fast Backn. % W 8 % % )
2
|
C
- 2
|
C
- 2
|
^
to *
2
|
^
to *
2
|
-o ) 2
|
-o ) 2
|
Back Capable Target 8 % % ) W 7 % * % * % W 4 % ) % ' 2
|
Back Capable Target 8 % % ) W 7 % * % * % W 4 % ) % ' 2
|
/ response % * * ) %
2
|
/ response % * * ) %
2
|
/ o% ' -
|
/ o% ' -
|
2
|
2
|
|
|
o&
2
|
o&
2
|
|
|
op - I 2
|
op - I 2
|
" ) Software configurable support for memory . * : % % ) % * ) ) ) % * % ) ) * * * ) * ( ? % ? * ( ' 2 2
|
" ) Software configurable support for memory . * : % % ) % * ) ) ) % * % ) ) * * * ) * ( ? % ? * ( ' 2 2
|
" access optimizing commands% % % % * * ? % ) ) % * ? ? % ) *
2
|
" access optimizing commands% % % % * * ? % ) ) % * ? ? % ) *
2
|
o% ' -
|
o% ' -
|
2
|
2
|
R
|
R
|
o&
2
|
o&
2
|
R
|
R
|
op - A 2
|
op - A 2
|
[" $ Fully transparent WISHBONE interface. ) ( L % ) * % % ) L O . < 8 < < 3 L ) % % % %
2
|
[" $ Fully transparent WISHBONE interface. ) ( L % ) * % % ) L O . < 8 < < 3 L ) % % % %
2
|
[ o ' J 2
|
[ o ' J 2
|
" * operation, controllable on image by image * * % % * ) ( % * ) * % * % ( * ) ( ? % ) % ( * ( ' ? % ) % ' F 2
|
" * operation, controllable on image by image * * % % * ) ( % * ) * % * % ( * ) ( ? % ) % ( * ( ' ? % ) % ' F 2
|
" ' basis with proper software settings of * % I : ) I * * * % I * : % % I % ) ) I * ' . 2
|
" ' basis with proper software settings of * % I : ) I * * * % I * : % % I % ) ) I * ' . 2
|
z" configuration registers % * ) ) ) % * ) % ) %
2
|
z" configuration registers % * ) ) ) % * ) % ) %
2
|
z o% '
2
|
z o% '
2
|
|
|
o% - ( 2
|
o% - ( 2
|
7
|
7
|
WISHBONE Interface W = B B H B = 8 3 $ 3 3 3 @ "Arial w@ s
|
WISHBONE Interface W = B B H B = 8 3 $ 3 3 3 @ "Arial w@ s
|
UwUw 0 -
2
|
UwUw 0 -
2
|
:9 / -
|
:9 / -
|
2
|
2
|
|
|
&
2
|
&
2
|
|
|
p - > 2
|
p - > 2
|
" " WISHBONE clock independent of PCI O . < 8 < < 3 E % * % ) E ) * % * % ) * % ) E * D / 7 ' 2
|
" " WISHBONE clock independent of PCI O . < 8 < < 3 E % * % ) E ) * % * % ) * % ) E * D / 7 ' 2
|
"" clock % * % )
2
|
"" clock % * % )
2
|
" % ' -
- -
! , -
-
-
*J
2
|
" % ' -
- -
! , -
-
-
*J
2
|
K J* % @ Times New Roman
UwUw 0 -
2
|
K J* % @ Times New Roman
UwUw 0 -
2
|
J* - 2
|
J* - 2
|
|
|
J*DATA SHEETH E = E C H C C =
2
|
J*DATA SHEETH E = E C H C C =
2
|
J* 8 ' &
.
|
J* 8 ' &
.
|
- - /D 1 _ _ - - Arial w@
|
- - /D 1 _ _ - - Arial w@
|
UwUw 0 - "System w@ (
|
UwUw 0 - "System w@ (
|
1
UwUw 0 -
|
1
UwUw 0 -
|
- - 1 $ N f f O N O N f - - - - $ 2GG22G - - Arial w@
|
- - 1 $ N f f O N O N f - - - - $ 2GG22G - - Arial w@
|
UwUw 0 - Arial w@
|
UwUw 0 - Arial w@
|
UwUw 0 - "System w@
|
UwUw 0 - "System w@
|
UwUw 0 - . - 2
|
UwUw 0 - . - 2
|
<
|
<
|
PCI MasterC H S 8 2 8 ! 2
|
PCI MasterC H S 8 2 8 ! 2
|
ModuleS 8 8 8 8 - - - $ 2 22 - - - Arial w@
|
ModuleS 8 8 8 8 - - - $ 2 22 - - - Arial w@
|
j
UwUw 0 - - . - 2
|
j
UwUw 0 - - . - 2
|
t <
|
t <
|
PCI TargetC H = 8 ! 8 8 2
|
PCI TargetC H = 8 ! 8 8 2
|
& ModuleS 8 8 8 8 - - - $ 2 3
3
2 2 3 - - - Arial w@
|
& ModuleS 8 8 8 8 - - - $ 2 3
3
2 2 3 - - - Arial w@
|
q
UwUw 0 - - . - 2
|
q
UwUw 0 - - . - 2
|
n; WISHBONE^ C H C N H C 2
|
n; WISHBONE^ C H C N H C 2
|
Slave ModuleC 8 2 8 S 8 8 8 8 - - - $ 2
2 2 - - - Arial w@
|
Slave ModuleC 8 2 8 S 8 8 8 8 - - - $ 2
2 2 - - - Arial w@
|
j
UwUw 0 - - - . - 2
|
j
UwUw 0 - - - . - 2
|
WISHBONE^ C H C N H C 2
|
WISHBONE^ C H C N H C 2
|
w MasterS 8 2 8 ! 2
|
w MasterS 8 2 8 ! 2
|
& ModuleS 8 8 8 8 - - - $ 233G2G23 - - Arial w@
|
& ModuleS 8 8 8 8 - - - $ 233G2G23 - - Arial w@
|
UwUw 0 - Arial w@ r
|
UwUw 0 - Arial w@ r
|
N
UwUw 0 - - . - 2
|
N
UwUw 0 - - . - 2
|
PCI Config.e7 < < . . . 2
|
PCI Config.e7 < < . . . 2
|
CYCLE< 6 < . 7 - - - $ 2 2 2 - - Arial w@
|
CYCLE< 6 < . 7 - - - $ 2 2 2 - - Arial w@
|
UwUw 0 - Arial w@
|
UwUw 0 - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
f Interrupt ack. . . . . . * + 2
|
f Interrupt ack. . . . . . * + 2
|
W CYCLE < 6 < . 7 - - - $ 222 - - Arial w@
|
W CYCLE < 6 < . 7 - - - $ 222 - - Arial w@
|
l
UwUw 0 - Arial w@
|
l
UwUw 0 - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
U PCI Config.e7 < < . . . 2
|
U PCI Config.e7 < < . . . 2
|
CYCLE< 6 < . 7 - - - $ >
|
CYCLE< 6 < . 7 - - - $ >
|
|
|
>> - - Arial w@
|
>> - - Arial w@
|
k
UwUw 0 - Arial w@
|
k
UwUw 0 - Arial w@
|
s
UwUw 0 - Arial w@
|
s
UwUw 0 - Arial w@
|
UwUw 0 - - - . - 2
|
UwUw 0 - - - . - 2
|
A WBR_FIFOO < < . 3 3 A - 2
|
A WBR_FIFOO < < . 3 3 A - 2
|
o WB from PCIeS 7 . G 7 < - - - $ 2n
|
o WB from PCIeS 7 . G 7 < - - - $ 2n
|
n
|
n
|
22n - - - Arial w@
|
22n - - - Arial w@
|
UwUw 0 - Arial w@ r
|
UwUw 0 - Arial w@ r
|
O
UwUw 0 - - - . - 2
|
O
UwUw 0 - - - . - 2
|
v WBW_FIFOO < O . 3 3 A - 2
|
v WBW_FIFOO < O . 3 3 A - 2
|
C WB to PCItS 7 . 7 < - - - $ 2
|
C WB to PCItS 7 . 7 < - - - $ 2
|
|
|
|
|
2
|
2
|
2 - - - Arial w@
|
2 - - - Arial w@
|
UwUw 0 - Arial w@
|
UwUw 0 - Arial w@
|
UwUw 0 - - - . - 2
|
UwUw 0 - - - . - 2
|
t
|
t
|
PCIR_FIFOt7 < < . 3 3 A - 2
|
PCIR_FIFOt7 < < . 3 3 A - 2
|
|
|
d PCI from WBe7 < . G S 7 - - - $ 2
|
d PCI from WBe7 < . G S 7 - - - $ 2
|
|
|
2 22 2 - - - Arial w@
|
2 22 2 - - - Arial w@
|
n
UwUw 0 - Arial w@
|
n
UwUw 0 - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
w PCIW_FIFOt7 < O . 3 3 A - 2
|
w PCIW_FIFOt7 < O . 3 3 A - 2
|
PCI to WBt7 < . S 7 - - - $ >n n >>n - - Arial w@
|
PCI to WBt7 < . S 7 - - - $ >n n >>n - - Arial w@
|
t
UwUw 0 - Arial w@
|
t
UwUw 0 - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
u
Configuration H 8 8 7 8 ! 8 8 8 2
|
u
Configuration H 8 8 7 8 ! 8 8 8 2
|
R Space C 8 8 2 8 - - - $ 2 2 2 - - Arial w@ r
|
R Space C 8 8 2 8 - - - $ 2 2 2 - - Arial w@ r
|
Q
UwUw 0 - - . - 2
|
Q
UwUw 0 - - . - 2
|
_ RESET U.< 7 7 7 4 < - - - $ 2Z2Z2 - - Arial w@
|
_ RESET U.< 7 7 7 4 < - - - $ 2Z2Z2 - - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
Error U.7 . < - - - $ 2 22 - - Arial w@
|
Error U.7 . < - - - $ 2 22 - - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
Interrupt U. . . . . < - - - $ F
|
Interrupt U. . . . . < - - - $ F
|
FF
|
FF
|
FF
|
FF
|
- - Arial w@
|
- - Arial w@
|
o
UwUw 0 - Arial w@
|
o
UwUw 0 - Arial w@
|
m
UwUw 0 - - . - 2
|
m
UwUw 0 - - . - 2
|
wA PCIlC H 2
|
wA PCIlC H 2
|
R I/Ol N - - - $ > nn>nng g > - - Arial w@
|
R I/Ol N - - - $ > nn>nng g > - - Arial w@
|
u
UwUw 0 - - . - 2
|
u
UwUw 0 - - . - 2
|
RL System- ! " % 9 - - - $ Z 2 n2 nZ n n Z - - Arial w@ r
|
RL System- ! " % 9 - - - $ Z 2 n2 nZ n n Z - - Arial w@ r
|
R
UwUw 0 - - . - 2
|
R
UwUw 0 - - . - 2
|
n $ Arbitration.- % % % % - - - $ FZZ2F - - - - $ F B q q B 2 F - - - - $ 2n'VFVF2n - - - - $ F22vF - -
|
n $ Arbitration.- % % % % - - - $ FZZ2F - - - - $ F B q q B 2 F - - - - $ 2n'VFVF2n - - - - $ F22vF - -
|
- % u - - - - , $ 2}zv2 - - - - , $ Fvz}~}}}}}}~F - -
|
- % u - - - - , $ 2}zv2 - - - - , $ Fvz}~}}}}}}~F - -
|
- % RuR - - - - , $ 2Rqnjgc_\XTPMIEA>:732R - - - - , $ FR37:>A~E}I}M}P}T}X}\~_cgjnqFR - -
|
- % RuR - - - - , $ 2Rqnjgc_\XTPMIEA>:732R - - - - , $ FR37:>A~E}I}M}P}T}X}\~_cgjnqFR - -
|
- % u - - - - , $ 22 - - - - , $ F~}}}}}}~F - - - - $ '>'n??n' - - - - $ 2
|
- % u - - - - , $ 22 - - - - , $ F~}}}}}}~F - - - - $ '>'n??n' - - - - $ 2
|
+
|
+
|
|
|
|
|
F
|
F
|
2 - - Arial w@
|
2 - - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
D PCI Read Address- 0 0 % % % - % % % " " - - - $ 2 b 2 - - - - " $ r ; ; - nQ - - - z p ` V F < , " v l \ R B 8 ( # * 5 < G N Y ` k r b X H > ; ; ; ; ; ; ; # ; 3 ; = ; M ; W ; g ; q ; ; ; ; ; ; ; ; ; ; ; ;
; ; ' ; 7 ; A ; Q ; [ ; k ; u ; ; ; ; ; ; ; - # y n y n u { o h \ U Q \ f v - - - Arial w@
|
D PCI Read Address- 0 0 % % % - % % % " " - - - $ 2 b 2 - - - - " $ r ; ; - nQ - - - z p ` V F < , " v l \ R B 8 ( # * 5 < G N Y ` k r b X H > ; ; ; ; ; ; ; # ; 3 ; = ; M ; W ; g ; q ; ; ; ; ; ; ; ; ; ; ; ;
; ; ' ; 7 ; A ; Q ; [ ; k ; u ; ; ; ; ; ; ; - # y n y n u { o h \ U Q \ f v - - - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
% PCI HOSTC H H N C > - - - $ Z nnZnGn G - - Arial w@
|
% PCI HOSTC H H N C > - - - $ Z nnZnGn G - - Arial w@
|
UwUw 0 - - . - 2
|
UwUw 0 - - . - 2
|
& Addr/Datat- % % 0 % % - - - $ v nnvnbn b - - Arial w@
|
& Addr/Datat- % % 0 % % - - - $ v nnvnbn b - - Arial w@
|
q
UwUw 0 - - . - 2
|
q
UwUw 0 - - . - 2
|
Q ControlT0 % % % - - - $ nnn~n0 0 ~ - - Arial w@
|
Q ControlT0 % % % - - - $ nnn~n0 0 ~ - - Arial w@
|
w
UwUw 0 - - . - 2
|
w
UwUw 0 - - . - 2
|
@ Interruptt % % % % - - - $ # nn#nnK K # - - Arial w@ r
|
@ Interruptt % % % % - - - $ # nn#nnK K # - - Arial w@ r
|
T
UwUw 0 - - . - 2
|
T
UwUw 0 - - . - 2
|
7r Error - % - - - $ #2#2 a a#h#hnnnn# - - - - $ 6 #j<6 <6 e e M 6 - - - - $ ?22 - - - - $ >ZBBss>Z - - - - $
|
7r Error - % - - - $ #2#2 a a#h#hnnnn# - - - - $ 6 #j<6 <6 e e M 6 - - - - $ ?22 - - - - $ >ZBBss>Z - - - - $
|
|
|
?
|
?
|
2 2
|
2 2
|
|
|
|
|
- - - - $ 2 Z
|
- - - - $ 2 Z
|
|
|
B
|
B
|
B
|
B
|
s
|
s
|
s
|
s
|
2 Z - - - - $ ;k2 k2 ; - - Arial w@
|
2 Z - - - - $ ;k2 k2 ; - - Arial w@
|
n
UwUw 0 - - . - 2
|
n
UwUw 0 - - . - 2
|
OD WB Read AddressB - 0 % % % - % % % " " - - - $ b$2 $2 - - Arial w@
|
OD WB Read AddressB - 0 % % % - % % % " " - - - $ b$2 $2 - - Arial w@
|
UwUw 0 - - . - - - - $
Z
2Y2YZYY
Z - - Arial w@
|
UwUw 0 - - . - - - - $
Z
2Y2YZYY
Z - - Arial w@
|
UwUw 0 - - . -
2
|
UwUw 0 - - . -
2
|
na Data0 % % - - - $
G
YYGY3Y
3
- - Arial w@
|
na Data0 % % - - - $
G
YYGY3Y
3
- - Arial w@
|
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P a r t S u b t i t l e ] $$pd ]p 6@CJ" KH R R
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P a r t T i t l e ^ pd ]p @CJ< OJ QJ kHT , T T a b l e o f A u t h o r i t i e s _
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P a r t T i t l e ^ pd ]p @CJ< OJ QJ kHT , T T a b l e o f A u t h o r i t i e s _
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