//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// File name "wbw_wbr_fifos.v" ////
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//// File name "wbw_wbr_fifos.v" ////
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//// ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - mihad@opencores.org ////
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//// - mihad@opencores.org ////
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//// - Miha Dolenc ////
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//// - Miha Dolenc ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.pdf ////
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//// All additional information is avaliable in the README.pdf ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////
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//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2001/06/12 11:13:34 mihad
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// Revision 1.4 2001/06/12 11:13:34 mihad
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// Changed module parameters
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// Changed module parameters
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//
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//
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//
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//
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`include "constants.v"
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`include "constants.v"
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`include "fifo_control.v"
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`include "fifo_control.v"
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`include "dp_sram.v"
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`include "dp_sram.v"
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`include "dp_async_ram.v"
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`include "dp_async_ram.v"
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|
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module WBW_WBR_FIFOS( wb_clock_in, pci_clock_in, reset_in,
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module WBW_WBR_FIFOS( wb_clock_in, pci_clock_in, reset_in,
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wbw_wenable_in, wbw_addr_data_in,
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wbw_wenable_in, wbw_addr_data_in,
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wbw_cbe_in, wbw_control_in,
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wbw_cbe_in, wbw_control_in,
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wbw_renable_in, wbw_addr_data_out,
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wbw_renable_in, wbw_addr_data_out,
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wbw_cbe_out, wbw_control_out,
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wbw_cbe_out, wbw_control_out,
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wbw_flush_in, wbw_almost_full_out, wbw_full_out,
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wbw_flush_in, wbw_almost_full_out, wbw_full_out,
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wbw_almost_empty_out, wbw_empty_out, wbw_transaction_ready_out,
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wbw_almost_empty_out, wbw_empty_out, wbw_transaction_ready_out,
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wbr_wenable_in, wbr_data_in,
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wbr_wenable_in, wbr_data_in,
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wbr_be_in, wbr_control_in,
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wbr_be_in, wbr_control_in,
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wbr_renable_in, wbr_data_out,
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wbr_renable_in, wbr_data_out,
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wbr_be_out, wbr_control_out,
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wbr_be_out, wbr_control_out,
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wbr_flush_in, wbr_almost_full_out, wbr_full_out,
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wbr_flush_in, wbr_almost_full_out, wbr_full_out,
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wbr_almost_empty_out, wbr_empty_out, wbr_transaction_ready_out) ;
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wbr_almost_empty_out, wbr_empty_out, wbr_transaction_ready_out) ;
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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System inputs:
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System inputs:
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wb_clock_in - WISHBONE bus clock
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wb_clock_in - WISHBONE bus clock
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pci_clock_in - PCI bus clock
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pci_clock_in - PCI bus clock
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reset_in - reset from control logic
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reset_in - reset from control logic
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-------------------------------------------------------------------------------------------------------------*/
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-------------------------------------------------------------------------------------------------------------*/
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input wb_clock_in, pci_clock_in, reset_in ;
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input wb_clock_in, pci_clock_in, reset_in ;
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|
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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WISHBONE WRITE FIFO interface signals prefixed with wbw_ - FIFO is used for posted writes initiated by
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WISHBONE WRITE FIFO interface signals prefixed with wbw_ - FIFO is used for posted writes initiated by
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WISHBONE master, traveling through FIFO and are completed on PCI by PCI master interface
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WISHBONE master, traveling through FIFO and are completed on PCI by PCI master interface
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|
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write enable signal:
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write enable signal:
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wbw_wenable_in = write enable input for WBW_FIFO - driven by WISHBONE slave interface
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wbw_wenable_in = write enable input for WBW_FIFO - driven by WISHBONE slave interface
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|
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data input signals:
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data input signals:
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wbw_addr_data_in = data input - data from WISHBONE bus - first entry of transaction is address others are data entries
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wbw_addr_data_in = data input - data from WISHBONE bus - first entry of transaction is address others are data entries
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wbw_cbe_in = bus command/byte enable(~SEL[3:0]) input - first entry of transaction is bus command, other are byte enables
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wbw_cbe_in = bus command/byte enable(~SEL[3:0]) input - first entry of transaction is bus command, other are byte enables
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wbw_control_in = control input - encoded control bus input
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wbw_control_in = control input - encoded control bus input
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|
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read enable signal:
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read enable signal:
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wbw_renable_in = read enable input driven by PCI master interface
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wbw_renable_in = read enable input driven by PCI master interface
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data output signals:
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data output signals:
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wbw_addr_data_out = data output - data from WISHBONE bus - first entry of transaction is address, others are data entries
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wbw_addr_data_out = data output - data from WISHBONE bus - first entry of transaction is address, others are data entries
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wbw_cbe_out = bus command/byte enable output - first entry of transaction is bus command, others are byte enables
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wbw_cbe_out = bus command/byte enable output - first entry of transaction is bus command, others are byte enables
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wbw_control_out = control input - encoded control bus input
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wbw_control_out = control input - encoded control bus input
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status signals - monitored by various resources in the core
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status signals - monitored by various resources in the core
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wbw_flush_in = flush signal input for WBW_FIFO - when asserted, fifo is flushed(emptied)
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wbw_flush_in = flush signal input for WBW_FIFO - when asserted, fifo is flushed(emptied)
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wbw_almost_full_out = almost full output from WBW_FIFO
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wbw_almost_full_out = almost full output from WBW_FIFO
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wbw_full_out = full output from WBW_FIFO
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wbw_full_out = full output from WBW_FIFO
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wbw_almost_empty_out = almost empty output from WBW_FIFO
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wbw_almost_empty_out = almost empty output from WBW_FIFO
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wbw_empty_out = empty output from WBW_FIFO
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wbw_empty_out = empty output from WBW_FIFO
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wbw_transaction_ready_out = output indicating that one complete transaction is waiting in WBW_FIFO
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wbw_transaction_ready_out = output indicating that one complete transaction is waiting in WBW_FIFO
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-----------------------------------------------------------------------------------------------------------*/
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-----------------------------------------------------------------------------------------------------------*/
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// input control and data
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// input control and data
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input wbw_wenable_in ;
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input wbw_wenable_in ;
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input [31:0] wbw_addr_data_in ;
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input [31:0] wbw_addr_data_in ;
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input [3:0] wbw_cbe_in ;
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input [3:0] wbw_cbe_in ;
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input [3:0] wbw_control_in ;
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input [3:0] wbw_control_in ;
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// output control and data
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// output control and data
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input wbw_renable_in ;
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input wbw_renable_in ;
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output [31:0] wbw_addr_data_out ;
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output [31:0] wbw_addr_data_out ;
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output [3:0] wbw_cbe_out ;
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output [3:0] wbw_cbe_out ;
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output [3:0] wbw_control_out ;
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output [3:0] wbw_control_out ;
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// flush input
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// flush input
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input wbw_flush_in ;
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input wbw_flush_in ;
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// status outputs
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// status outputs
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output wbw_almost_full_out ;
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output wbw_almost_full_out ;
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output wbw_full_out ;
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output wbw_full_out ;
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output wbw_almost_empty_out ;
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output wbw_almost_empty_out ;
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output wbw_empty_out ;
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output wbw_empty_out ;
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output wbw_transaction_ready_out ;
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output wbw_transaction_ready_out ;
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|
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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WISHBONE READ FIFO interface signals prefixed with wbr_ - FIFO is used for holding delayed read completions
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WISHBONE READ FIFO interface signals prefixed with wbr_ - FIFO is used for holding delayed read completions
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initiated by master on WISHBONE bus and completed on PCI bus,
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initiated by master on WISHBONE bus and completed on PCI bus,
|
|
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write enable signal:
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write enable signal:
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wbr_wenable_in = write enable input for WBR_FIFO - driven by PCI master interface
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wbr_wenable_in = write enable input for WBR_FIFO - driven by PCI master interface
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|
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data input signals:
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data input signals:
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wbr_data_in = data input - data from PCI bus - there is no address entry here, since address is stored in separate register
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wbr_data_in = data input - data from PCI bus - there is no address entry here, since address is stored in separate register
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wbr_be_in = byte enable(~BE#[3:0]) input - byte enables - same through one transaction
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wbr_be_in = byte enable(~BE#[3:0]) input - byte enables - same through one transaction
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wbr_control_in = control input - encoded control bus input
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wbr_control_in = control input - encoded control bus input
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|
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read enable signal:
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read enable signal:
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wbr_renable_in = read enable input driven by WISHBONE slave interface
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wbr_renable_in = read enable input driven by WISHBONE slave interface
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|
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data output signals:
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data output signals:
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wbr_data_out = data output - data from PCI bus
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wbr_data_out = data output - data from PCI bus
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wbr_be_out = byte enable output(~#BE)
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wbr_be_out = byte enable output(~#BE)
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wbr_control_out = control output - encoded control bus output
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wbr_control_out = control output - encoded control bus output
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|
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status signals - monitored by various resources in the core
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status signals - monitored by various resources in the core
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wbr_flush_in = flush signal input for WBR_FIFO - when asserted, fifo is flushed(emptied)
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wbr_flush_in = flush signal input for WBR_FIFO - when asserted, fifo is flushed(emptied)
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wbr_almost_full_out = almost full output from WBR_FIFO
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wbr_almost_full_out = almost full output from WBR_FIFO
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wbr full_out = full output from WBR_FIFO
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wbr full_out = full output from WBR_FIFO
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wbr_almost_empty_out = almost empty output from WBR_FIFO
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wbr_almost_empty_out = almost empty output from WBR_FIFO
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wbr_empty_out = empty output from WBR_FIFO
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wbr_empty_out = empty output from WBR_FIFO
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wbr_transaction_ready_out = output indicating that one complete transaction is waiting in WBR_FIFO
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wbr_transaction_ready_out = output indicating that one complete transaction is waiting in WBR_FIFO
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-----------------------------------------------------------------------------------------------------------*/
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-----------------------------------------------------------------------------------------------------------*/
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// input control and data
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// input control and data
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input wbr_wenable_in ;
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input wbr_wenable_in ;
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input [31:0] wbr_data_in ;
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input [31:0] wbr_data_in ;
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input [3:0] wbr_be_in ;
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input [3:0] wbr_be_in ;
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input [3:0] wbr_control_in ;
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input [3:0] wbr_control_in ;
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|
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// output control and data
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// output control and data
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input wbr_renable_in ;
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input wbr_renable_in ;
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output [31:0] wbr_data_out ;
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output [31:0] wbr_data_out ;
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output [3:0] wbr_be_out ;
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output [3:0] wbr_be_out ;
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output [3:0] wbr_control_out ;
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output [3:0] wbr_control_out ;
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// flush input
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// flush input
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input wbr_flush_in ;
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input wbr_flush_in ;
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// status outputs
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// status outputs
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output wbr_almost_full_out ;
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output wbr_almost_full_out ;
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output wbr_full_out ;
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output wbr_full_out ;
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output wbr_almost_empty_out ;
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output wbr_almost_empty_out ;
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output wbr_empty_out ;
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output wbr_empty_out ;
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output wbr_transaction_ready_out ;
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output wbr_transaction_ready_out ;
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|
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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FIFO depth parameters:
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FIFO depth parameters:
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WBW_DEPTH = defines WBW_FIFO depth
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WBW_DEPTH = defines WBW_FIFO depth
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WBR_DEPTH = defines WBR_FIFO depth
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WBR_DEPTH = defines WBR_FIFO depth
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WBW_ADDR_LENGTH = defines WBW_FIFO's location address length = log2(WBW_DEPTH)
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WBW_ADDR_LENGTH = defines WBW_FIFO's location address length = log2(WBW_DEPTH)
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WBR_ADDR_LENGTH = defines WBR_FIFO's location address length = log2(WBR_DEPTH)
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WBR_ADDR_LENGTH = defines WBR_FIFO's location address length = log2(WBR_DEPTH)
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-----------------------------------------------------------------------------------------------------------*/
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-----------------------------------------------------------------------------------------------------------*/
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parameter WBW_DEPTH = `WBW_DEPTH ;
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parameter WBW_DEPTH = `WBW_DEPTH ;
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parameter WBW_ADDR_LENGTH = `WBW_ADDR_LENGTH ;
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parameter WBW_ADDR_LENGTH = `WBW_ADDR_LENGTH ;
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parameter WBR_DEPTH = `WBR_DEPTH ;
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parameter WBR_DEPTH = `WBR_DEPTH ;
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parameter WBR_ADDR_LENGTH = `WBR_ADDR_LENGTH ;
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parameter WBR_ADDR_LENGTH = `WBR_ADDR_LENGTH ;
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// obvious
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// obvious
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wire vcc = 1'b1 ;
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wire vcc = 1'b1 ;
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wire gnd = 1'b0 ;
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wire gnd = 1'b0 ;
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|
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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wbw_wallow = WBW_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
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wbw_wallow = WBW_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
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wbw_rallow = WBW_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
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wbw_rallow = WBW_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
|
-----------------------------------------------------------------------------------------------------------*/
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-----------------------------------------------------------------------------------------------------------*/
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wire wbw_wallow ;
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wire wbw_wallow ;
|
wire wbw_rallow ;
|
wire wbw_rallow ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
wbr_wallow = WBR_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
|
wbr_wallow = WBR_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
|
wbr_rallow = WBR_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
|
wbr_rallow = WBR_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire wbr_wallow ;
|
wire wbr_wallow ;
|
wire wbr_rallow ;
|
wire wbr_rallow ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
wires for address port conections from WBW_FIFO control logic to RAM blocks used for WBW_FIFO
|
wires for address port conections from WBW_FIFO control logic to RAM blocks used for WBW_FIFO
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire [(WBW_ADDR_LENGTH - 1):0] wbw_raddr ;
|
wire [(WBW_ADDR_LENGTH - 1):0] wbw_raddr ;
|
wire [(WBW_ADDR_LENGTH - 1):0] wbw_waddr ;
|
wire [(WBW_ADDR_LENGTH - 1):0] wbw_waddr ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
wires for address port conections from WBR_FIFO control logic to RAM blocks used for WBR_FIFO
|
wires for address port conections from WBR_FIFO control logic to RAM blocks used for WBR_FIFO
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire [(WBR_ADDR_LENGTH - 1):0] wbr_raddr ;
|
wire [(WBR_ADDR_LENGTH - 1):0] wbr_raddr ;
|
wire [(WBR_ADDR_LENGTH - 1):0] wbr_waddr ;
|
wire [(WBR_ADDR_LENGTH - 1):0] wbr_waddr ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
WBW_FIFO transaction counters: used to count incoming transactions and outgoing transactions. When number of
|
WBW_FIFO transaction counters: used to count incoming transactions and outgoing transactions. When number of
|
input transactions is equal to number of output transactions, it means that there isn't any complete transaction
|
input transactions is equal to number of output transactions, it means that there isn't any complete transaction
|
currently present in the FIFO.
|
currently present in the FIFO.
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
reg [(WBW_ADDR_LENGTH - 1):0] wbw_inTransactionCount ;
|
reg [(WBW_ADDR_LENGTH - 1):0] wbw_inTransactionCount ;
|
reg [(WBW_ADDR_LENGTH - 1):0] wbw_outTransactionCount ;
|
reg [(WBW_ADDR_LENGTH - 1):0] wbw_outTransactionCount ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
FlipFlops for indicating if complete delayed read completion is present in the FIFO
|
FlipFlops for indicating if complete delayed read completion is present in the FIFO
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
reg wbr_inTransactionCount ;
|
reg wbr_inTransactionCount ;
|
reg wbr_outTransactionCount ;
|
reg wbr_outTransactionCount ;
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
wires monitoring control bus. When control bus on a write transaction has a value of `LAST, it means that
|
wires monitoring control bus. When control bus on a write transaction has a value of `LAST, it means that
|
complete transaction is in the FIFO. When control bus on a read transaction has a value of `LAST,
|
complete transaction is in the FIFO. When control bus on a read transaction has a value of `LAST,
|
it means that there was one complete transaction taken out of FIFO.
|
it means that there was one complete transaction taken out of FIFO.
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire wbw_last_in = wbw_wallow && (wbw_control_in == `LAST) ;
|
wire wbw_last_in = wbw_wallow && (wbw_control_in == `LAST) ;
|
wire wbw_last_out = wbw_rallow && (wbw_control_out == `LAST) ;
|
wire wbw_last_out = wbw_rallow && (wbw_control_out == `LAST) ;
|
|
|
wire wbr_last_in = wbr_wallow && (wbr_control_in == `LAST) ;
|
wire wbr_last_in = wbr_wallow && (wbr_control_in == `LAST) ;
|
wire wbr_last_out = wbr_rallow && (wbr_control_out == `LAST) ;
|
wire wbr_last_out = wbr_rallow && (wbr_control_out == `LAST) ;
|
|
|
wire wbw_empty ;
|
wire wbw_empty ;
|
wire wbr_empty ;
|
wire wbr_empty ;
|
|
|
assign wbw_empty_out = wbw_empty ;
|
assign wbw_empty_out = wbw_empty ;
|
assign wbr_empty_out = wbr_empty ;
|
assign wbr_empty_out = wbr_empty ;
|
|
|
// clear wires for fifos
|
// clear wires for fifos
|
wire wbw_clear = reset_in || wbw_flush_in ; // WBW_FIFO clear
|
wire wbw_clear = reset_in || wbw_flush_in ; // WBW_FIFO clear
|
wire wbr_clear = reset_in || wbr_flush_in ; // WBR_FIFO clear
|
wire wbr_clear = reset_in || wbr_flush_in ; // WBR_FIFO clear
|
|
|
`ifdef FPGA
|
`ifdef FPGA
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
this code is included only for FPGA core usage - somewhat different logic because of sharing
|
this code is included only for FPGA core usage - somewhat different logic because of sharing
|
one block selectRAM+ between two FIFOs
|
one block selectRAM+ between two FIFOs
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
`ifdef BIG
|
`ifdef BIG
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Big FPGAs
|
Big FPGAs
|
WBW_FIFO and WBR_FIFO address prefixes - used for extending read and write addresses because of varible
|
WBW_FIFO and WBR_FIFO address prefixes - used for extending read and write addresses because of varible
|
FIFO depth and fixed SelectRAM+ size. Addresses are zero paded on the left to form long enough address
|
FIFO depth and fixed SelectRAM+ size. Addresses are zero paded on the left to form long enough address
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire [(7 - WBW_ADDR_LENGTH):0] wbw_addr_prefix = {( 8 - WBW_ADDR_LENGTH){1'b0}} ;
|
wire [(7 - WBW_ADDR_LENGTH):0] wbw_addr_prefix = {( 8 - WBW_ADDR_LENGTH){1'b0}} ;
|
wire [(7 - WBR_ADDR_LENGTH):0] wbr_addr_prefix = {( 8 - WBR_ADDR_LENGTH){1'b0}} ;
|
wire [(7 - WBR_ADDR_LENGTH):0] wbr_addr_prefix = {( 8 - WBR_ADDR_LENGTH){1'b0}} ;
|
|
|
// compose addresses
|
// compose addresses
|
wire [7:0] wbw_whole_waddr = {wbw_addr_prefix, wbw_waddr} ;
|
wire [7:0] wbw_whole_waddr = {wbw_addr_prefix, wbw_waddr} ;
|
wire [7:0] wbw_whole_raddr = {wbw_addr_prefix, wbw_raddr} ;
|
wire [7:0] wbw_whole_raddr = {wbw_addr_prefix, wbw_raddr} ;
|
|
|
wire [7:0] wbr_whole_waddr = {wbr_addr_prefix, wbr_waddr} ;
|
wire [7:0] wbr_whole_waddr = {wbr_addr_prefix, wbr_waddr} ;
|
wire [7:0] wbr_whole_raddr = {wbr_addr_prefix, wbr_raddr} ;
|
wire [7:0] wbr_whole_raddr = {wbr_addr_prefix, wbr_raddr} ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Only 8 bits out of 16 are used in ram3 and ram6 - wires for referencing them
|
Only 8 bits out of 16 are used in ram3 and ram6 - wires for referencing them
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire [15:0] dpram3_portB_output ;
|
wire [15:0] dpram3_portB_output ;
|
wire [15:0] dpram6_portA_output ;
|
wire [15:0] dpram6_portA_output ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Control out assignements from ram3 output
|
Control out assignements from ram3 output
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
assign wbw_control_out = dpram3_portB_output[15:12] ;
|
assign wbw_control_out = dpram3_portB_output[15:12] ;
|
assign wbr_control_out = dpram6_portA_output[15:12] ;
|
assign wbr_control_out = dpram6_portA_output[15:12] ;
|
|
|
assign wbw_cbe_out = dpram3_portB_output[3:0] ;
|
assign wbw_cbe_out = dpram3_portB_output[3:0] ;
|
assign wbr_be_out = dpram6_portA_output[3:0] ;
|
assign wbr_be_out = dpram6_portA_output[3:0] ;
|
|
|
wire wbw_read_enable = wbw_rallow || wbw_empty ;
|
wire wbw_read_enable = wbw_rallow || wbw_empty ;
|
wire wbr_read_enable = wbr_rallow || wbr_empty ;
|
wire wbr_read_enable = wbr_rallow || wbr_empty ;
|
|
|
// Block SelectRAM+ cells instantiation
|
// Block SelectRAM+ cells instantiation
|
RAMB4_S16_S16 dpram16_1 (.ADDRA(wbw_whole_waddr), .DIA(wbw_addr_data_in[15:0]),
|
RAMB4_S16_S16 dpram16_1 (.ADDRA(wbw_whole_waddr), .DIA(wbw_addr_data_in[15:0]),
|
.ENA(vcc), .RSTA(reset_in),
|
.ENA(vcc), .RSTA(reset_in),
|
.CLKA(wb_clock_in), .WEA(wbw_wallow),
|
.CLKA(wb_clock_in), .WEA(wbw_wallow),
|
.DOA(),
|
.DOA(),
|
.ADDRB(wbw_whole_raddr), .DIB(16'h0000),
|
.ADDRB(wbw_whole_raddr), .DIB(16'h0000),
|
.ENB(wbw_read_enable), .RSTB(reset_in),
|
.ENB(wbw_read_enable), .RSTB(reset_in),
|
.CLKB(pci_clock_in), .WEB(gnd),
|
.CLKB(pci_clock_in), .WEB(gnd),
|
.DOB(wbw_addr_data_out[15:0])) ;
|
.DOB(wbw_addr_data_out[15:0])) ;
|
|
|
RAMB4_S16_S16 dpram16_2 (.ADDRA(wbw_whole_waddr), .DIA(wbw_addr_data_in[31:16]),
|
RAMB4_S16_S16 dpram16_2 (.ADDRA(wbw_whole_waddr), .DIA(wbw_addr_data_in[31:16]),
|
.ENA(vcc), .RSTA(reset_in),
|
.ENA(vcc), .RSTA(reset_in),
|
.CLKA(wb_clock_in), .WEA(wbw_wallow),
|
.CLKA(wb_clock_in), .WEA(wbw_wallow),
|
.DOA(),
|
.DOA(),
|
.ADDRB(wbw_whole_raddr), .DIB(16'h0000),
|
.ADDRB(wbw_whole_raddr), .DIB(16'h0000),
|
.ENB(wbw_read_enable), .RSTB(reset_in),
|
.ENB(wbw_read_enable), .RSTB(reset_in),
|
.CLKB(pci_clock_in), .WEB(gnd),
|
.CLKB(pci_clock_in), .WEB(gnd),
|
.DOB(wbw_addr_data_out[31:16])) ;
|
.DOB(wbw_addr_data_out[31:16])) ;
|
|
|
RAMB4_S16_S16 dpram16_3 (.ADDRA(wbw_whole_waddr), .DIA({wbw_control_in, 8'h00, wbw_cbe_in}),
|
RAMB4_S16_S16 dpram16_3 (.ADDRA(wbw_whole_waddr), .DIA({wbw_control_in, 8'h00, wbw_cbe_in}),
|
.ENA(vcc), .RSTA(reset_in),
|
.ENA(vcc), .RSTA(reset_in),
|
.CLKA(wb_clock_in), .WEA(wbw_wallow),
|
.CLKA(wb_clock_in), .WEA(wbw_wallow),
|
.DOA(),
|
.DOA(),
|
.ADDRB(wbw_whole_raddr), .DIB(16'h0000),
|
.ADDRB(wbw_whole_raddr), .DIB(16'h0000),
|
.ENB(wbw_read_enable), .RSTB(reset_in),
|
.ENB(wbw_read_enable), .RSTB(reset_in),
|
.CLKB(pci_clock_in), .WEB(gnd),
|
.CLKB(pci_clock_in), .WEB(gnd),
|
.DOB(dpram3_portB_output)) ;
|
.DOB(dpram3_portB_output)) ;
|
|
|
RAMB4_S16_S16 dpram16_4 (.ADDRA(wbr_whole_raddr), .DIA(16'h0000),
|
RAMB4_S16_S16 dpram16_4 (.ADDRA(wbr_whole_raddr), .DIA(16'h0000),
|
.ENA(wbr_read_enable), .RSTA(reset_in),
|
.ENA(wbr_read_enable), .RSTA(reset_in),
|
.CLKA(wb_clock_in), .WEA(gnd),
|
.CLKA(wb_clock_in), .WEA(gnd),
|
.DOA(wbr_data_out[15:0]),
|
.DOA(wbr_data_out[15:0]),
|
.ADDRB(wbr_whole_waddr), .DIB(wbr_data_in[15:0]),
|
.ADDRB(wbr_whole_waddr), .DIB(wbr_data_in[15:0]),
|
.ENB(vcc), .RSTB(reset_in),
|
.ENB(vcc), .RSTB(reset_in),
|
.CLKB(pci_clock_in), .WEB(wbr_wallow),
|
.CLKB(pci_clock_in), .WEB(wbr_wallow),
|
.DOB()) ;
|
.DOB()) ;
|
|
|
RAMB4_S16_S16 dpram16_5 (.ADDRA(wbr_whole_raddr), .DIA(16'h0000),
|
RAMB4_S16_S16 dpram16_5 (.ADDRA(wbr_whole_raddr), .DIA(16'h0000),
|
.ENA(wbr_read_enable), .RSTA(reset_in),
|
.ENA(wbr_read_enable), .RSTA(reset_in),
|
.CLKA(wb_clock_in), .WEA(gnd),
|
.CLKA(wb_clock_in), .WEA(gnd),
|
.DOA(wbr_data_out[31:16]),
|
.DOA(wbr_data_out[31:16]),
|
.ADDRB(wbr_whole_waddr), .DIB(wbr_data_in[31:16]),
|
.ADDRB(wbr_whole_waddr), .DIB(wbr_data_in[31:16]),
|
.ENB(vcc), .RSTB(reset_in),
|
.ENB(vcc), .RSTB(reset_in),
|
.CLKB(pci_clock_in), .WEB(wbr_wallow),
|
.CLKB(pci_clock_in), .WEB(wbr_wallow),
|
.DOB()) ;
|
.DOB()) ;
|
|
|
RAMB4_S16_S16 dpram16_6 (.ADDRA(wbr_whole_raddr), .DIA(16'h0000),
|
RAMB4_S16_S16 dpram16_6 (.ADDRA(wbr_whole_raddr), .DIA(16'h0000),
|
.ENA(wbr_read_enable), .RSTA(reset_in),
|
.ENA(wbr_read_enable), .RSTA(reset_in),
|
.CLKA(wb_clock_in), .WEA(gnd),
|
.CLKA(wb_clock_in), .WEA(gnd),
|
.DOA(dpram6_portA_output),
|
.DOA(dpram6_portA_output),
|
.ADDRB(wbr_whole_waddr), .DIB({wbr_control_in, 8'h00, wbr_be_in}),
|
.ADDRB(wbr_whole_waddr), .DIB({wbr_control_in, 8'h00, wbr_be_in}),
|
.ENB(vcc), .RSTB(reset_in),
|
.ENB(vcc), .RSTB(reset_in),
|
.CLKB(pci_clock_in), .WEB(wbr_wallow),
|
.CLKB(pci_clock_in), .WEB(wbr_wallow),
|
.DOB()) ;
|
.DOB()) ;
|
|
|
`else // SMALL FPGAs
|
`else // SMALL FPGAs
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Small FPGAs
|
Small FPGAs
|
WBW_FIFO and WBR_FIFO address prefixes - used for extending read and write addresses because of varible
|
WBW_FIFO and WBR_FIFO address prefixes - used for extending read and write addresses because of varible
|
FIFO depth and fixed SelectRAM+ size. Addresses are always paded, because of RAM sharing between FIFOs
|
FIFO depth and fixed SelectRAM+ size. Addresses are always paded, because of RAM sharing between FIFOs
|
WBW addresses are zero padded on the left, WBR addresses are padded
|
WBW addresses are zero padded on the left, WBR addresses are padded
|
with ones on the left
|
with ones on the left
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire [(7 - WBW_ADDR_LENGTH):0] wbw_addr_prefix = {( 8 - WBW_ADDR_LENGTH){1'b0}} ;
|
wire [(7 - WBW_ADDR_LENGTH):0] wbw_addr_prefix = {( 8 - WBW_ADDR_LENGTH){1'b0}} ;
|
wire [(7 - WBR_ADDR_LENGTH):0] wbr_addr_prefix = {( 8 - WBR_ADDR_LENGTH){1'b1}} ;
|
wire [(7 - WBR_ADDR_LENGTH):0] wbr_addr_prefix = {( 8 - WBR_ADDR_LENGTH){1'b1}} ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Only 8 bits out of 16 are used in ram3 - wires for referencing them
|
Only 8 bits out of 16 are used in ram3 - wires for referencing them
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire [15:0] dpram3_portA_output ;
|
wire [15:0] dpram3_portA_output ;
|
wire [15:0] dpram3_portB_output ;
|
wire [15:0] dpram3_portB_output ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Control out assignements from ram3 output
|
Control out assignements from ram3 output
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
assign wbw_control_out = dpram3_portB_output[15:12] ;
|
assign wbw_control_out = dpram3_portB_output[15:12] ;
|
assign wbr_control_out = dpram3_portA_output[15:12] ;
|
assign wbr_control_out = dpram3_portA_output[15:12] ;
|
|
|
assign wbw_cbe_out = dpram3_portB_output[3:0] ;
|
assign wbw_cbe_out = dpram3_portB_output[3:0] ;
|
assign wbr_be_out = dpram3_portA_output[3:0] ;
|
assign wbr_be_out = dpram3_portA_output[3:0] ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Logic used for extending port's enable input for one clock cycle to allow address and date change from
|
Logic used for extending port's enable input for one clock cycle to allow address and date change from
|
WISHBONE write fifo's write address and data back to WISHBONE read fifo's address and data ( turnaround cycle )
|
WISHBONE write fifo's write address and data back to WISHBONE read fifo's address and data ( turnaround cycle )
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
reg wbw_write_performed ;
|
reg wbw_write_performed ;
|
always@(posedge wb_clock_in or posedge reset_in)
|
always@(posedge wb_clock_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
wbw_write_performed <= #`FF_DELAY 1'b0 ;
|
wbw_write_performed <= #`FF_DELAY 1'b0 ;
|
else
|
else
|
wbw_write_performed <= #`FF_DELAY wbw_wallow ;
|
wbw_write_performed <= #`FF_DELAY wbw_wallow ;
|
end
|
end
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Logic used for extending port's enable input for one clock cycle to allow address and date change from
|
Logic used for extending port's enable input for one clock cycle to allow address and date change from
|
WISHBONE read fifo's write address and data back to WISHBONE write fifo's address and data ( turnaround cycle )
|
WISHBONE read fifo's write address and data back to WISHBONE write fifo's address and data ( turnaround cycle )
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
reg wbr_write_performed ;
|
reg wbr_write_performed ;
|
always@(posedge pci_clock_in or posedge reset_in)
|
always@(posedge pci_clock_in or posedge reset_in)
|
begin
|
begin
|
if (reset_in)
|
if (reset_in)
|
wbr_write_performed <= #`FF_DELAY 1'b0 ;
|
wbr_write_performed <= #`FF_DELAY 1'b0 ;
|
else
|
else
|
wbr_write_performed <= #`FF_DELAY wbr_wallow ;
|
wbr_write_performed <= #`FF_DELAY wbr_wallow ;
|
end
|
end
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Additional register storing actual WBW read address. It must be applied to port B during turnaround cycle
|
Additional register storing actual WBW read address. It must be applied to port B during turnaround cycle
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
reg [(WBW_ADDR_LENGTH - 1):0] wbw_raddr_0 ;
|
reg [(WBW_ADDR_LENGTH - 1):0] wbw_raddr_0 ;
|
|
|
always@(posedge pci_clock_in or posedge wbw_clear)
|
always@(posedge pci_clock_in or posedge wbw_clear)
|
begin
|
begin
|
if (wbw_clear)
|
if (wbw_clear)
|
wbw_raddr_0 <= #`FF_DELAY {WBW_ADDR_LENGTH{1'b0}} ;
|
wbw_raddr_0 <= #`FF_DELAY {WBW_ADDR_LENGTH{1'b0}} ;
|
else
|
else
|
if(wbw_rallow)
|
if(wbw_rallow)
|
wbw_raddr_0 <= #`FF_DELAY wbw_raddr ;
|
wbw_raddr_0 <= #`FF_DELAY wbw_raddr ;
|
end
|
end
|
|
|
wire [(WBW_ADDR_LENGTH - 1):0] wbw_raddr_calc = wbr_write_performed ? wbw_raddr_0 : wbw_raddr ;
|
wire [(WBW_ADDR_LENGTH - 1):0] wbw_raddr_calc = wbr_write_performed ? wbw_raddr_0 : wbw_raddr ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Additional register storing actual WBR read address. It must be applied to port A during turnaround cycle
|
Additional register storing actual WBR read address. It must be applied to port A during turnaround cycle
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
reg [(WBR_ADDR_LENGTH - 1):0] wbr_raddr_0 ;
|
reg [(WBR_ADDR_LENGTH - 1):0] wbr_raddr_0 ;
|
|
|
always@(posedge wb_clock_in or posedge wbr_clear)
|
always@(posedge wb_clock_in or posedge wbr_clear)
|
begin
|
begin
|
if(wbr_clear)
|
if(wbr_clear)
|
wbr_raddr_0 <= #`FF_DELAY {WBR_ADDR_LENGTH{1'b0}} ;
|
wbr_raddr_0 <= #`FF_DELAY {WBR_ADDR_LENGTH{1'b0}} ;
|
else
|
else
|
if(wbr_rallow)
|
if(wbr_rallow)
|
wbr_raddr_0 <= #`FF_DELAY wbr_raddr ;
|
wbr_raddr_0 <= #`FF_DELAY wbr_raddr ;
|
end
|
end
|
|
|
wire [(WBR_ADDR_LENGTH - 1):0] wbr_raddr_calc = wbw_write_performed ? wbr_raddr_0 : wbr_raddr ;
|
wire [(WBR_ADDR_LENGTH - 1):0] wbr_raddr_calc = wbw_write_performed ? wbr_raddr_0 : wbr_raddr ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Port A and B enables
|
Port A and B enables
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire portA_enable = wbw_wallow || wbr_rallow || wbr_empty || wbw_write_performed ;
|
wire portA_enable = wbw_wallow || wbr_rallow || wbr_empty || wbw_write_performed ;
|
wire portB_enable = wbr_wallow || wbw_rallow || wbw_empty || wbr_write_performed ;
|
wire portB_enable = wbr_wallow || wbw_rallow || wbw_empty || wbr_write_performed ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Port A address generation for block SelectRam+ in SpartanII or Virtex
|
Port A address generation for block SelectRam+ in SpartanII or Virtex
|
Port A is clocked by WISHBONE clock, DIA is input for wbw_fifo, DOA is output for wbr_fifo. Address is multiplexed
|
Port A is clocked by WISHBONE clock, DIA is input for wbw_fifo, DOA is output for wbr_fifo. Address is multiplexed
|
between two values.
|
between two values.
|
Address multiplexing:
|
Address multiplexing:
|
wbw_wenable == 1 => ADDRA = wbw_waddr (write pointer of WBW_FIFO)
|
wbw_wenable == 1 => ADDRA = wbw_waddr (write pointer of WBW_FIFO)
|
else ADDRA = wbr_raddr (read pointer of WBR_FIFO)
|
else ADDRA = wbr_raddr (read pointer of WBR_FIFO)
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire [7:0] portA_addr = wbw_wallow ? {wbw_addr_prefix, wbw_waddr} : {wbr_addr_prefix, wbr_raddr_calc} ;
|
wire [7:0] portA_addr = wbw_wallow ? {wbw_addr_prefix, wbw_waddr} : {wbr_addr_prefix, wbr_raddr_calc} ;
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Port B address generation for block SelectRam+ in SpartanII or Virtex
|
Port B address generation for block SelectRam+ in SpartanII or Virtex
|
Port B is clocked by PCI clock, DIB is input for wbr_fifo, DOB is output for wbw_fifo. Address is multiplexed
|
Port B is clocked by PCI clock, DIB is input for wbr_fifo, DOB is output for wbw_fifo. Address is multiplexed
|
between two values.
|
between two values.
|
Address multiplexing:
|
Address multiplexing:
|
wbr_wenable == 1 => ADDRB = wbr_waddr (write pointer of WBR_FIFO)
|
wbr_wenable == 1 => ADDRB = wbr_waddr (write pointer of WBR_FIFO)
|
else ADDRB = wbw_raddr (read pointer of WBW_FIFO)
|
else ADDRB = wbw_raddr (read pointer of WBW_FIFO)
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
wire [7:0] portB_addr = wbr_wallow ? {wbr_addr_prefix, wbr_waddr} : {wbw_addr_prefix, wbw_raddr_calc} ;
|
wire [7:0] portB_addr = wbr_wallow ? {wbr_addr_prefix, wbr_waddr} : {wbw_addr_prefix, wbw_raddr_calc} ;
|
|
|
// Block SelectRAM+ cells instantiation
|
// Block SelectRAM+ cells instantiation
|
RAMB4_S16_S16 dpram16_1 (.ADDRA(portA_addr), .DIA(wbw_addr_data_in[15:0]),
|
RAMB4_S16_S16 dpram16_1 (.ADDRA(portA_addr), .DIA(wbw_addr_data_in[15:0]),
|
.ENA(portA_enable), .RSTA(reset_in),
|
.ENA(portA_enable), .RSTA(reset_in),
|
.CLKA(wb_clock_in), .WEA(wbw_wallow),
|
.CLKA(wb_clock_in), .WEA(wbw_wallow),
|
.DOA(wbr_data_out[15:0]),
|
.DOA(wbr_data_out[15:0]),
|
.ADDRB(portB_addr), .DIB(wbr_data_in[15:0]),
|
.ADDRB(portB_addr), .DIB(wbr_data_in[15:0]),
|
.ENB(portB_enable), .RSTB(reset_in),
|
.ENB(portB_enable), .RSTB(reset_in),
|
.CLKB(pci_clock_in), .WEB(wbr_wallow),
|
.CLKB(pci_clock_in), .WEB(wbr_wallow),
|
.DOB(wbw_addr_data_out[15:0])) ;
|
.DOB(wbw_addr_data_out[15:0])) ;
|
|
|
RAMB4_S16_S16 dpram16_2 (.ADDRA(portA_addr), .DIA(wbw_addr_data_in[31:16]),
|
RAMB4_S16_S16 dpram16_2 (.ADDRA(portA_addr), .DIA(wbw_addr_data_in[31:16]),
|
.ENA(portA_enable), .RSTA(reset_in),
|
.ENA(portA_enable), .RSTA(reset_in),
|
.CLKA(wb_clock_in), .WEA(wbw_wallow),
|
.CLKA(wb_clock_in), .WEA(wbw_wallow),
|
.DOA(wbr_data_out[31:16]),
|
.DOA(wbr_data_out[31:16]),
|
.ADDRB(portB_addr), .DIB(wbr_data_in[31:16]),
|
.ADDRB(portB_addr), .DIB(wbr_data_in[31:16]),
|
.ENB(portB_enable), .RSTB(reset_in),
|
.ENB(portB_enable), .RSTB(reset_in),
|
.CLKB(pci_clock_in), .WEB(wbr_wallow),
|
.CLKB(pci_clock_in), .WEB(wbr_wallow),
|
.DOB(wbw_addr_data_out[31:16])) ;
|
.DOB(wbw_addr_data_out[31:16])) ;
|
|
|
RAMB4_S16_S16 dpram16_3 (.ADDRA(portA_addr), .DIA({wbw_control_in, 8'h00, wbw_cbe_in}),
|
RAMB4_S16_S16 dpram16_3 (.ADDRA(portA_addr), .DIA({wbw_control_in, 8'h00, wbw_cbe_in}),
|
.ENA(portA_enable), .RSTA(reset_in),
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.ENA(portA_enable), .RSTA(reset_in),
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.CLKA(wb_clock_in), .WEA(wbw_wallow),
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.CLKA(wb_clock_in), .WEA(wbw_wallow),
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.DOA(dpram3_portA_output),
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.DOA(dpram3_portA_output),
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.ADDRB(portB_addr), .DIB({wbr_control_in, 8'h00, wbr_be_in}),
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.ADDRB(portB_addr), .DIB({wbr_control_in, 8'h00, wbr_be_in}),
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.ENB(portB_enable), .RSTB(reset_in),
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.ENB(portB_enable), .RSTB(reset_in),
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.CLKB(pci_clock_in), .WEB(wbr_wallow),
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.CLKB(pci_clock_in), .WEB(wbr_wallow),
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.DOB(dpram3_portB_output)) ;
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.DOB(dpram3_portB_output)) ;
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`endif
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`endif
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`else
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`else
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wire [39:0] wbw_ram_data_out ;
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wire [39:0] wbw_ram_data_out ;
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wire [39:0] wbw_ram_data_in = {wbw_control_in, wbw_cbe_in, wbw_addr_data_in} ;
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wire [39:0] wbw_ram_data_in = {wbw_control_in, wbw_cbe_in, wbw_addr_data_in} ;
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wire [39:0] wbr_ram_data_in = {wbr_control_in, wbr_be_in, wbr_data_in} ;
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wire [39:0] wbr_ram_data_in = {wbr_control_in, wbr_be_in, wbr_data_in} ;
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wire [39:0] wbr_ram_data_out ;
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wire [39:0] wbr_ram_data_out ;
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assign wbw_control_out = wbw_ram_data_out[39:36] ;
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assign wbw_control_out = wbw_ram_data_out[39:36] ;
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assign wbw_cbe_out = wbw_ram_data_out[35:32] ;
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assign wbw_cbe_out = wbw_ram_data_out[35:32] ;
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assign wbw_addr_data_out = wbw_ram_data_out [31:0] ;
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assign wbw_addr_data_out = wbw_ram_data_out [31:0] ;
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assign wbr_control_out = wbr_ram_data_out[39:36] ;
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assign wbr_control_out = wbr_ram_data_out[39:36] ;
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assign wbr_be_out = wbr_ram_data_out[35:32] ;
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assign wbr_be_out = wbr_ram_data_out[35:32] ;
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assign wbr_data_out = wbr_ram_data_out [31:0] ;
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assign wbr_data_out = wbr_ram_data_out [31:0] ;
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`ifdef SYNCHRONOUS
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`ifdef SYNCHRONOUS
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/*-----------------------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------------------
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ASIC memory primitives will be added here in the near future - currently there is only some generic,
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ASIC memory primitives will be added here in the near future - currently there is only some generic,
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behavioral dual port ram here
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behavioral dual port ram here
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-----------------------------------------------------------------------------------------------------------*/
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-----------------------------------------------------------------------------------------------------------*/
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|
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wire wbw_read_enable = wbw_rallow || wbw_empty ;
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wire wbw_read_enable = wbw_rallow || wbw_empty ;
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wire wbr_read_enable = wbr_rallow || wbr_empty ;
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wire wbr_read_enable = wbr_rallow || wbr_empty ;
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|
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DP_SRAM #(WBW_ADDR_LENGTH, WBW_DEPTH) wbw_ram (.reset_in(reset_in), .wclock_in(wb_clock_in), .rclock_in(pci_clock_in), .data_in(wbw_ram_data_in),
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DP_SRAM #(WBW_ADDR_LENGTH, WBW_DEPTH) wbw_ram (.reset_in(reset_in), .wclock_in(wb_clock_in), .rclock_in(pci_clock_in), .data_in(wbw_ram_data_in),
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.raddr_in(wbw_raddr), .waddr_in(wbw_waddr), .data_out(wbw_ram_data_out), .renable_in(wbw_read_enable), .wenable_in(wbw_wallow));
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.raddr_in(wbw_raddr), .waddr_in(wbw_waddr), .data_out(wbw_ram_data_out), .renable_in(wbw_read_enable), .wenable_in(wbw_wallow));
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|
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DP_SRAM #(WBR_ADDR_LENGTH, WBR_DEPTH) wbr_ram (.reset_in(reset_in), .wclock_in(pci_clock_in), .rclock_in(wb_clock_in), .data_in(wbr_ram_data_in),
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DP_SRAM #(WBR_ADDR_LENGTH, WBR_DEPTH) wbr_ram (.reset_in(reset_in), .wclock_in(pci_clock_in), .rclock_in(wb_clock_in), .data_in(wbr_ram_data_in),
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.raddr_in(wbr_raddr), .waddr_in(wbr_waddr), .data_out(wbr_ram_data_out), .renable_in(wbr_read_enable), .wenable_in(wbr_wallow));
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.raddr_in(wbr_raddr), .waddr_in(wbr_waddr), .data_out(wbr_ram_data_out), .renable_in(wbr_read_enable), .wenable_in(wbr_wallow));
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|
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`else //ASYNCHRONOUS RAM
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`else //ASYNCHRONOUS RAM
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DP_ASYNC_RAM #(WBW_ADDR_LENGTH, WBW_DEPTH) wbw_ram (.reset_in(reset_in), .wclock_in(wb_clock_in), .data_in(wbw_ram_data_in),
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DP_ASYNC_RAM #(WBW_ADDR_LENGTH, WBW_DEPTH) wbw_ram (.reset_in(reset_in), .wclock_in(wb_clock_in), .data_in(wbw_ram_data_in),
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.raddr_in(wbw_raddr), .waddr_in(wbw_waddr), .data_out(wbw_ram_data_out), .wenable_in(wbw_wallow));
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.raddr_in(wbw_raddr), .waddr_in(wbw_waddr), .data_out(wbw_ram_data_out), .wenable_in(wbw_wallow));
|
|
|
DP_ASYNC_RAM #(WBR_ADDR_LENGTH, WBR_DEPTH) wbr_ram (.reset_in(reset_in), .wclock_in(pci_clock_in), .data_in(wbr_ram_data_in),
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DP_ASYNC_RAM #(WBR_ADDR_LENGTH, WBR_DEPTH) wbr_ram (.reset_in(reset_in), .wclock_in(pci_clock_in), .data_in(wbr_ram_data_in),
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.raddr_in(wbr_raddr), .waddr_in(wbr_waddr), .data_out(wbr_ram_data_out), .wenable_in(wbr_wallow));
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.raddr_in(wbr_raddr), .waddr_in(wbr_waddr), .data_out(wbr_ram_data_out), .wenable_in(wbr_wallow));
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
/*-----------------------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------------------
|
Instantiation of two control logic modules - one for WBW_FIFO and one for WBR_FIFO
|
Instantiation of two control logic modules - one for WBW_FIFO and one for WBR_FIFO
|
-----------------------------------------------------------------------------------------------------------*/
|
-----------------------------------------------------------------------------------------------------------*/
|
FIFO_CONTROL #(WBW_ADDR_LENGTH) wbw_fifo_ctrl
|
FIFO_CONTROL #(WBW_ADDR_LENGTH) wbw_fifo_ctrl
|
(.rclock_in(pci_clock_in), .wclock_in(wb_clock_in), .renable_in(wbw_renable_in),
|
(.rclock_in(pci_clock_in), .wclock_in(wb_clock_in), .renable_in(wbw_renable_in),
|
.wenable_in(wbw_wenable_in), .reset_in(reset_in), .flush_in(wbw_flush_in),
|
.wenable_in(wbw_wenable_in), .reset_in(reset_in), .flush_in(wbw_flush_in),
|
.almost_full_out(wbw_almost_full_out), .full_out(wbw_full_out),
|
.almost_full_out(wbw_almost_full_out), .full_out(wbw_full_out),
|
.almost_empty_out(wbw_almost_empty_out), .empty_out(wbw_empty),
|
.almost_empty_out(wbw_almost_empty_out), .empty_out(wbw_empty),
|
.waddr_out(wbw_waddr), .raddr_out(wbw_raddr),
|
.waddr_out(wbw_waddr), .raddr_out(wbw_raddr),
|
.rallow_out(wbw_rallow), .wallow_out(wbw_wallow));
|
.rallow_out(wbw_rallow), .wallow_out(wbw_wallow));
|
|
|
FIFO_CONTROL #(WBR_ADDR_LENGTH) wbr_fifo_ctrl
|
FIFO_CONTROL #(WBR_ADDR_LENGTH) wbr_fifo_ctrl
|
(.rclock_in(wb_clock_in), .wclock_in(pci_clock_in), .renable_in(wbr_renable_in),
|
(.rclock_in(wb_clock_in), .wclock_in(pci_clock_in), .renable_in(wbr_renable_in),
|
.wenable_in(wbr_wenable_in), .reset_in(reset_in), .flush_in(wbr_flush_in),
|
.wenable_in(wbr_wenable_in), .reset_in(reset_in), .flush_in(wbr_flush_in),
|
.almost_full_out(wbr_almost_full_out), .full_out(wbr_full_out),
|
.almost_full_out(wbr_almost_full_out), .full_out(wbr_full_out),
|
.almost_empty_out(wbr_almost_empty_out), .empty_out(wbr_empty),
|
.almost_empty_out(wbr_almost_empty_out), .empty_out(wbr_empty),
|
.waddr_out(wbr_waddr), .raddr_out(wbr_raddr),
|
.waddr_out(wbr_waddr), .raddr_out(wbr_raddr),
|
.rallow_out(wbr_rallow), .wallow_out(wbr_wallow));
|
.rallow_out(wbr_rallow), .wallow_out(wbr_wallow));
|
|
|
|
|
// in and out transaction counters
|
// in and out transaction counters
|
always@(posedge wb_clock_in or posedge wbw_clear)
|
always@(posedge wb_clock_in or posedge wbw_clear)
|
begin
|
begin
|
if (wbw_clear)
|
if (wbw_clear)
|
wbw_inTransactionCount <= #`FF_DELAY {WBW_ADDR_LENGTH{1'b0}} ;
|
wbw_inTransactionCount <= #`FF_DELAY {WBW_ADDR_LENGTH{1'b0}} ;
|
else
|
else
|
if (wbw_last_in && wbw_wallow)
|
if (wbw_last_in && wbw_wallow)
|
wbw_inTransactionCount <= #`FF_DELAY wbw_inTransactionCount + 1'b1 ;
|
wbw_inTransactionCount <= #`FF_DELAY wbw_inTransactionCount + 1'b1 ;
|
end
|
end
|
|
|
always@(posedge pci_clock_in or posedge wbw_clear)
|
always@(posedge pci_clock_in or posedge wbw_clear)
|
begin
|
begin
|
if (wbw_clear)
|
if (wbw_clear)
|
wbw_outTransactionCount <= #`FF_DELAY {WBW_ADDR_LENGTH{1'b0}} ;
|
wbw_outTransactionCount <= #`FF_DELAY {WBW_ADDR_LENGTH{1'b0}} ;
|
else
|
else
|
if (wbw_last_out)
|
if (wbw_last_out)
|
wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
|
wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
|
end
|
end
|
|
|
always@(posedge pci_clock_in or posedge wbr_clear)
|
always@(posedge pci_clock_in or posedge wbr_clear)
|
begin
|
begin
|
if (wbr_clear)
|
if (wbr_clear)
|
wbr_inTransactionCount <= #`FF_DELAY 1'b0 ;
|
wbr_inTransactionCount <= #`FF_DELAY 1'b0 ;
|
else
|
else
|
if (wbr_last_in && wbr_wallow)
|
if (wbr_last_in && wbr_wallow)
|
wbr_inTransactionCount <= #`FF_DELAY ~wbr_inTransactionCount ;
|
wbr_inTransactionCount <= #`FF_DELAY ~wbr_inTransactionCount ;
|
end
|
end
|
|
|
always@(posedge wb_clock_in or posedge wbr_clear)
|
always@(posedge wb_clock_in or posedge wbr_clear)
|
begin
|
begin
|
if (wbr_clear)
|
if (wbr_clear)
|
wbr_outTransactionCount <= #`FF_DELAY 1'b0 ;
|
wbr_outTransactionCount <= #`FF_DELAY 1'b0 ;
|
else
|
else
|
if (wbr_last_out)
|
if (wbr_last_out)
|
wbr_outTransactionCount <= #`FF_DELAY ~wbr_outTransactionCount ;
|
wbr_outTransactionCount <= #`FF_DELAY ~wbr_outTransactionCount ;
|
end
|
end
|
|
|
assign wbw_transaction_ready_out = !(wbw_inTransactionCount == wbw_outTransactionCount) ;
|
assign wbw_transaction_ready_out = !(wbw_inTransactionCount == wbw_outTransactionCount) ;
|
assign wbr_transaction_ready_out = !(wbr_inTransactionCount == wbr_outTransactionCount) ;
|
assign wbr_transaction_ready_out = !(wbr_inTransactionCount == wbr_outTransactionCount) ;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
