//==========================//
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//==========================//
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// PCI Target state machine //
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// PCI Target state machine //
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//==========================//
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//==========================//
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`include "pci_stat.v"
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`include "pci_stat.v"
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module pci_target32_sm
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module pci_target32_sm
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(
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(
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// system inputs
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// system inputs
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clk_in,
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clk_in,
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reset_in,
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reset_in,
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// master inputs
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// master inputs
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pci_frame_in,
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pci_frame_in,
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pci_irdy_in,
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pci_irdy_in,
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// target response outputs
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// target response outputs
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pci_trdy_out,
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pci_trdy_out,
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pci_stop_out,
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pci_stop_out,
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pci_devsel_out,
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pci_devsel_out,
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// address, data, bus command, byte enable in/outs
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// address, data, bus command, byte enable in/outs
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pci_ad_in,
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pci_ad_in,
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pci_ad_out,
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pci_ad_out,
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pci_ad_en_out,
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pci_ad_en_out,
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pci_cbe_in,
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pci_cbe_in,
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// other side of state machine
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// other side of state machine
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address_o,
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address_o,
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addr_claim_i,
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addr_claim_i,
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bc_o,
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bc_o,
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data_o,
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data_o,
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data_i,
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data_i,
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be_o,
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be_o,
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req_o,
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req_o,
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rdy_o,
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rdy_o,
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status_i,
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status_i,
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last_o
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last_o
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) ;
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) ;
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// system inputs
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// system inputs
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input clk_in,
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input clk_in,
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reset_in ;
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reset_in ;
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/*==================================================================================================================
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/*==================================================================================================================
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PCI interface signals - bidirectional signals are divided to inputs and outputs in I/O cells instantiation
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PCI interface signals - bidirectional signals are divided to inputs and outputs in I/O cells instantiation
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module. Enables are separate signals.
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module. Enables are separate signals.
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==================================================================================================================*/
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==================================================================================================================*/
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// master inputs
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// master inputs
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input pci_frame_in ;
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input pci_frame_in ;
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input pci_irdy_in ;
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input pci_irdy_in ;
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// target response outputs
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// target response outputs
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output pci_trdy_out,
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output pci_trdy_out,
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pci_stop_out,
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pci_stop_out,
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pci_devsel_out ;
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pci_devsel_out ;
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// address, data, bus command, byte enable in/outs
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// address, data, bus command, byte enable in/outs
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input [31:0] pci_ad_in ;
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input [31:0] pci_ad_in ;
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output [31:0] pci_ad_out ;
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output [31:0] pci_ad_out ;
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output pci_ad_en_out ;
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output pci_ad_en_out ;
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input [3:0] pci_cbe_in ;
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input [3:0] pci_cbe_in ;
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/*==================================================================================================================
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/*==================================================================================================================
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Other side of master state machine - the one that issues requests.
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Other side of master state machine - the one that issues requests.
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==================================================================================================================*/
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==================================================================================================================*/
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/*==================================================================================================================
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/*==================================================================================================================
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address output - address always qualifies current data present at data_i input or data_o output and because of that
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address output - address always qualifies current data present at data_i input or data_o output and because of that
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it must be written to counter at address phase. After all dta phases address counter must be
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it must be written to counter at address phase. After all dta phases address counter must be
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incremented and the address claim input signal tells if the address falls into valid address space.
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incremented and the address claim input signal tells if the address falls into valid address space.
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If address (address from PCI bus at address phase) is not claimed, then PCI Target must not respond
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If address (address from PCI bus at address phase) is not claimed, then PCI Target must not respond
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in any way, but if address from burst transfere crosses valid address space boundaries after first
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in any way, but if address from burst transfere crosses valid address space boundaries after first
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data phase, then PCI Target respond with Target Abort.
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data phase, then PCI Target respond with Target Abort.
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==================================================================================================================*/
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==================================================================================================================*/
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output [31:0] address_o ; // current request address output
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output [31:0] address_o ; // current request address output
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/*==================================================================================================================
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/*==================================================================================================================
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address claim input - address claim input always confirms if current address present at address_o output falls
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address claim input - address claim input always confirms if current address present at address_o output falls
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into valid address space (for address phase) or is still in the valid address space (for all
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into valid address space (for address phase) or is still in the valid address space (for all
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data phases after first one). Address decoders with address translation are implemented at
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data phases after first one). Address decoders with address translation are implemented at
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the backend.
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the backend.
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==================================================================================================================*/
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==================================================================================================================*/
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input addr_claim_i ; // current request address claim input
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input addr_claim_i ; // current request address claim input
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/*==================================================================================================================
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/*==================================================================================================================
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bus command output - bus command output must be valid through all transfere to identifie what backend should do (it
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bus command output - bus command output must be valid through all transfere to identifie what backend should do (it
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is PCI bus command). Because of that it must be latched at address phase when req_o is
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is PCI bus command). Because of that it must be latched at address phase when req_o is
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asserted.
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asserted.
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==================================================================================================================*/
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==================================================================================================================*/
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output [3:0] bc_o ; // current request bus command output
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output [3:0] bc_o ; // current request bus command output
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/*==================================================================================================================
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/*==================================================================================================================
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data input - for PCI read bus commands - this bus provides valid read data from backend during read commands when
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data input - for PCI read bus commands - this bus provides valid read data from backend during read commands when
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req_o and rdy_o are asserted (rdy_o - PCI Target state machine is ready to receive data) and backend
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req_o and rdy_o are asserted (rdy_o - PCI Target state machine is ready to receive data) and backend
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signals `TRANSFERED status on status_i bus. On the rising edge of clock data must be latched from
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signals `TRANSFERED status on status_i bus. On the rising edge of clock data must be latched from
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data_i bus. After this, PCI Target state machine must deasert rdy_o if it is not ready to accept more
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data_i bus. After this, PCI Target state machine must deasert rdy_o if it is not ready to accept more
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data.
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data.
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==================================================================================================================*/
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==================================================================================================================*/
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input [31:0] data_i ; // for read operations - current dataphase data input
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input [31:0] data_i ; // for read operations - current dataphase data input
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/*==================================================================================================================
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/*==================================================================================================================
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data output - for PCI write bus commands - data on this bus is provided from PCI Target state machine during write
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data output - for PCI write bus commands - data on this bus is provided from PCI Target state machine during write
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commands and is qualified with rdy_o asserted. Backend is responsible for storing the data. Backend
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commands and is qualified with rdy_o asserted. Backend is responsible for storing the data. Backend
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signals if it is ready to store data with `TRANSFERED status on status_i bus. When that happens, PCI
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signals if it is ready to store data with `TRANSFERED status on status_i bus. When that happens, PCI
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Target state machine should provide new data imediately after rising clock edge or deassert rdy_o if
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Target state machine should provide new data imediately after rising clock edge or deassert rdy_o if
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it is not ready to do so.
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it is not ready to do so.
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==================================================================================================================*/
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==================================================================================================================*/
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output [31:0] data_o ; // for write operations - current request data output
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output [31:0] data_o ; // for write operations - current request data output
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/*==================================================================================================================
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/*==================================================================================================================
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byte enable output - active low byte enables drived from BE# pins on pci during transfers - they are valid at every
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byte enable output - active low byte enables drived from BE# pins on pci during transfers - they are valid at every
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data phase (rdy_o asserted). No matter which byte enables are active still all data must be
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data phase (rdy_o asserted). No matter which byte enables are active still all data must be
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privided to backend or to PCI (write or read).
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privided to backend or to PCI (write or read).
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==================================================================================================================*/
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==================================================================================================================*/
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output [3:0] be_o ; // current dataphase byte enable outputs
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output [3:0] be_o ; // current dataphase byte enable outputs
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/*==================================================================================================================
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/*==================================================================================================================
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request and ready outputs from PCI Target - req_o output means that PCI target has some transaction request for
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request and ready outputs from PCI Target - req_o output means that PCI target has some transaction request for
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backend (address and all data phases following).
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backend (address and all data phases following).
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During write requests PCI Target must provide address and bus command at address phase (and all data phases) and
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During write requests PCI Target must provide address and bus command at address phase (and all data phases) and
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byte enables and data during all data phases. During whole request req_o must be aserted, meanwhile rdy_o is
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byte enables and data during all data phases. During whole request req_o must be aserted, meanwhile rdy_o is
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asserted with valid byte enables and data. Transaction and data phases are completed regarding status_i bus from
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asserted with valid byte enables and data. Transaction and data phases are completed regarding status_i bus from
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backend described later.
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backend described later.
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During read requests PCI Target must provide address and bus command at address phase (and all data phases) and
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During read requests PCI Target must provide address and bus command at address phase (and all data phases) and
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byte enables during all data phases. During whole request req_o must be aserted, meanwhile rdy_o is asserted when
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byte enables during all data phases. During whole request req_o must be aserted, meanwhile rdy_o is asserted when
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PCI Target state machine is ready (PCI Master is pending for data) for data until backend signal status on status_i
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PCI Target state machine is ready (PCI Master is pending for data) for data until backend signal status on status_i
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bus that data are ready (`TRANSFERED) or to terminate with reatry (`RETRY - because all read transactions are
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bus that data are ready (`TRANSFERED) or to terminate with reatry (`RETRY - because all read transactions are
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delayed read transactions). Other posibilitys on status_i bus are described later. When status `TRANSFERED is
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delayed read transactions). Other posibilitys on status_i bus are described later. When status `TRANSFERED is
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signaled by backend, PCI Target must release rdy_o signal if it is not capable to receive more data. When PCI
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signaled by backend, PCI Target must release rdy_o signal if it is not capable to receive more data. When PCI
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Target state machine terminates with retry, PCI Master will release the PCI bus and PCI Target must also deasert
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Target state machine terminates with retry, PCI Master will release the PCI bus and PCI Target must also deasert
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req_o signal.
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req_o signal.
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==================================================================================================================*/
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==================================================================================================================*/
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output req_o ; // PCI Target cycle is requested to backend
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output req_o ; // PCI Target cycle is requested to backend
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output rdy_o ; // requestor indicates that data is ready to be sent for write transaction and ready to
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output rdy_o ; // requestor indicates that data is ready to be sent for write transaction and ready to
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// be received on read transaction
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// be received on read transaction
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/*==================================================================================================================
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/*==================================================================================================================
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Last output - this output in conjuction with req_o and rdy_o qualifies last data beat in current request.
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Last output - this output in conjuction with req_o and rdy_o qualifies last data beat in current request.
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for single transfers all three signals are asserted in parallel, for burst transfers last_o is inactive
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for single transfers all three signals are asserted in parallel, for burst transfers last_o is inactive
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until last intended data is present at data_o ( assign last_o = pci_frame_in && ~pci_irdy_in ; boath
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until last intended data is present at data_o ( assign last_o = pci_frame_in && ~pci_irdy_in ; boath
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PCI signals are active low ).
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PCI signals are active low ).
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==================================================================================================================*/
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==================================================================================================================*/
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output last_o ; // last dataphase in current transaction indicator
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output last_o ; // last dataphase in current transaction indicator
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/*==================================================================================================================
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/*==================================================================================================================
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Status input - Status is always provided from the backend depending on FIFO progress. Status descriptions:
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Status input - Status is always provided from the backend depending on FIFO progress. Status descriptions:
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`WAIT - Default status - Means that current request is not processed in any way yet - this status is propagated
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`WAIT - Default status - Means that current request is not processed in any way yet - this status is propagated
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to Target state machine when backend is waiting FIFO to be ready while Target state machine wants to read/
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to Target state machine when backend is waiting FIFO to be ready while Target state machine wants to read/
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write from/to FIFO (PCI Target then inserts wait states), or rdy_o output is down (nothing is to be done).
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write from/to FIFO (PCI Target then inserts wait states), or rdy_o output is down (nothing is to be done).
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`TRANSFERED - Status means, that current data phase is completing succesfully on FIFO. During writes, this status
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`TRANSFERED - Status means, that current data phase is completing succesfully on FIFO. During writes, this status
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signals to the PCI Target state machine that it should provide new data imediately after rising clock
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signals to the PCI Target state machine that it should provide new data imediately after rising clock
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edge or deassert rdy_o if it is not ready to do so. During reads, this status signals to the PCI Target
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edge or deassert rdy_o if it is not ready to do so. During reads, this status signals to the PCI Target
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state machine that on the rising edge of clock data must be latched from data_i bus. After this, PCI
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state machine that on the rising edge of clock data must be latched from data_i bus. After this, PCI
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Target state machine must deasert rdy_o if it is not ready to accept more data.
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Target state machine must deasert rdy_o if it is not ready to accept more data.
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`DISCONNECT_WO_DATA - Backend signals this status to the PCI Target state machine when e.g. during write transaction,
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`DISCONNECT_WO_DATA - Backend signals this status to the PCI Target state machine when e.g. during write transaction,
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in the middle of the burst, FIFO becommes full and no data can be written into it anymore.
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in the middle of the burst, FIFO becommes full and no data can be written into it anymore.
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Disconnect without data is normal termination and PCI Target state machine must also emediately
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Disconnect without data is normal termination and PCI Target state machine must also emediately
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deaserts rdy_o and req_o.
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deaserts rdy_o and req_o.
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`DISCONNECT_W_DATA - Backend signals this status to the PCI Target state machine when e.g. during write transaction,
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`DISCONNECT_W_DATA - Backend signals this status to the PCI Target state machine when e.g. during write transaction,
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in the middle of the burst, FIFO is almost full and only this data can be written into it or
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in the middle of the burst, FIFO is almost full and only this data can be written into it or
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if burst is attempt to I/O space, to which only single transactions are allowed, this way
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if burst is attempt to I/O space, to which only single transactions are allowed, this way
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burst is broken into single transfers.
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burst is broken into single transfers.
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Disconnect with data is normal termination and PCI Target state machine must also emediately
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Disconnect with data is normal termination and PCI Target state machine must also emediately
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deaserts rdy_o and req_o.
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deaserts rdy_o and req_o.
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`TABORT - Target Abort status - Backend signals this status to PCI Target state machine when there e.g. data parrity
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`TABORT - Target Abort status - Backend signals this status to PCI Target state machine when there e.g. data parrity
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error occures (depending of the backend design) in the middle of the transfere or
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error occures (depending of the backend design) in the middle of the transfere or
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e.g. address parrity error occurs at the beginning of the transfere or if address
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e.g. address parrity error occurs at the beginning of the transfere or if address
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in the middle of the burst transfere crosses the valid address space boundaries.
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in the middle of the burst transfere crosses the valid address space boundaries.
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PCI Target state machine must terminate the transaction with Target Abort if it
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PCI Target state machine must terminate the transaction with Target Abort if it
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receives this status and it must deaserts rdy_o and req_o.
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receives this status and it must deaserts rdy_o and req_o.
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`RETRY - Backend signals this status to PCI Target state machine whenever there is a read transaction and backend
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`RETRY - Backend signals this status to PCI Target state machine whenever there is a read transaction and backend
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cannot start providing data because it does not have any data ready yet (e.g. FIFO still empty since all
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cannot start providing data because it does not have any data ready yet (e.g. FIFO still empty since all
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reads are delayed reads) or when there is a write transaction and backend cannot start receiving data
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reads are delayed reads) or when there is a write transaction and backend cannot start receiving data
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because FIFO is still full.
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because FIFO is still full.
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PCI Target state machine is responsible to terminate transaxction with retry and emediately deaserts
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PCI Target state machine is responsible to terminate transaxction with retry and emediately deaserts
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rdy_o and req_o.
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rdy_o and req_o.
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==================================================================================================================*/
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==================================================================================================================*/
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input [3:0] status_i ; // current dataphase completion status
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input [3:0] status_i ; // current dataphase completion status
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