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2713 North 750 East Lehi, Utah 84043
1-801-766-0285 1-801-280-9168
HYPERLINK "http://www.gutzlogic.com" www.gutzlogic.com
Cyclic Redundancy Code Verilog Code 16 bit data
Features
Verilog LCRC code for PCI Express TLP packets
16 bit data in 32 bit LCRC out
Functional Description
Designers commonly use Cyclic Redundacy Codes (CRC) as an alternative to parity and checksum calcutions for checking and correcting errors in data transmissions.
The CRC method for error detection and correction treats the data frame as a huge binary number. The binary number is divided (at the CRC generation end) by a fixed binary number (the CRC generator polynomial) and the resulting remainder of this division (CRC value) is appended to the end of the data frame. The receiver upon reception of the data frame repeats the calculation and compares its calculated CRC value the CRC value attached to the data frame. The traditional method for implementing a CRC generator uses a shift register with XOR gates and feedback taps as shown in Figure 1 for the X25 polynomial.
Figure SEQ Figure \* ARABIC 1
The classic serial implementation is widely used, but it is too slow for PCI Express LCRC and Gigabit Ethernet where bit rates can top 100 Mb/sec. The alternative method is parallel CRC calculations. This parallel conversion effectively divides the input clock frequency by 8, 16, or 32.
Implementation
We also ofter a crc_gen.c file for compiling any size data width and common CRC. Please see HYPERLINK "http://www.gutzlogic.com" www.gutzlogic.com.
After compiling the crc_gen.c source code with your preferred C-compiler invoke the executable program. You will be presented with a menu of several commonly used CRC polynomials. Also, choose how many bits you want calculated in parallel (up to 32). Once all of the menu selections have been entered the program will generate a fully synthesizable completely behavioral Verilog file called crc.v. This Verilog file can be modified as the user desires (for example adding registers), but the parallel crc equations should not be tampered with for they are correct for the entered polynomial. If the polynomial you want to generate Verilog code for is not in the menu, select the Enter your polynomial option. Then enter your polynomial. For example, the PCI Express DLLP CRC16 polynomial would be entered as: 10001000000001011.
This CRC generator program is very useful for generating the equations necessary for PCI Express 32-bit LCRC, scrambler LFSR, and 16-bit DLLP CRC equations. One needs to remember that once the PCI express CRC has been calculated it first needs to bit swapped and bit inverted before being tacked onto the end of a TLP or DLLP. Below shows how this would be accomplished for PCI Express 32-bit LCRC.
assign lcrcN = {(~lcrc[0] ,~lcrc[1],~lcrc[2],~lcrc[3],~lcrc[4],~lcrc[5],~lcrc[6],~lcrc[7],
~lcrc[8],~lcrc[9],~lcrc[10],~lcrc[11],~lcrc[12],~lcrc[13],~lcrc[14],~lcrc[15],
~lcrc[16],~lcrc[17],~lcrc[18],~lcrc[19],~lcrc[20],~lcrc[21],~lcrc[22],~lcrc[23],
~lcrc[24],~lcrc[25],~lcrc[26],~lcrc[27],~lcrc[28],~lcrc[29],~lcrc[30],~lcrc[31]};
Supported Polynomials
There are several common generator polynomials as follows:
CRC8, ATM (HEC)
x8 + x2 + x + 1
CRC10, ATM (OAM Cell)
x10 + x9 + x5 + x4 +x +1
CANbus
x15 + x14 + x10 + x8 + x7 + x4 + x3 + 1
CRC16
x16 + x12 + x2 + 1
CRC16 inverted
x16 + x14 + x + 1
PCI Express DLLP CRC16
x16 + x12 + x3 + x + 1
X25 (SDLC, HDLC, CRC-CCITT)
x16 + x12 + x5 + 1
PCI Express LCRC
x32 + x26 + x23 + x22 + x16 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
CRC32 (Ethernet, FDDI)
x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
User-defined polynomials up to 32nd order (comparable to CRC32, for example) are supported.
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ࡱ > ~ { | } y q` bjbjqPqP - : : * * * > b
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2713 North 750 East Lehi, Utah 84043
1-801-766-0285 1-801-280-9168
HYPERLINK "http://www.gutzlogic.com" www.gutzlogic.com
Cyclic Redundancy Code Verilog Code 16 bit data
Features
Verilog LCRC code for PCI Express TLP packets
16 bit data in 32 bit LCRC out
Functional Description
Designers commonly use Cyclic Redundacy Codes (CRC) as an alternative to parity and checksum calcutions for checking and correcting errors in data transmissions.
The CRC method for error detection and correction treats the data frame as a huge binary number. The binary number is divided (at the CRC generation end) by a fixed binary number (the CRC generator polynomial) and the resulting remainder of this division (CRC value) is appended to the end of the data frame. The receiver upon reception of the data frame repeats the calculation and compares its calculated CRC value the CRC value attached to the data frame. The traditional method for implementing a CRC generator uses a shift register with XOR gates and feedback taps as shown in Figure 1 for the X25 polynomial.
Figure SEQ Figure \* ARABIC 1
The classic serial implementation is widely used, but it is too slow for PCI Express LCRC and Gigabit Ethernet where bit rates can top 100 Mb/sec. The alternative method is parallel CRC calculations. This parallel conversion effectively divides the input clock frequency by 8, 16, or 32.
Implementation
We also ofter a crc_gen.c file for compiling any size data width and common CRC. Please see HYPERLINK "http://www.gutzlogic.com" www.gutzlogic.com.
After compiling the crc_gen.c source code with your preferred C-compiler invoke the executable program. You will be presented with a menu of several commonly used CRC polynomials. Also, choose how many bits you want calculated in parallel (up to 32). Once all of the menu selections have been entered the program will generate a fully synthesizable completely behavioral Verilog file called crc.v. This Verilog file can be modified as the user desires (for example adding registers), but the parallel crc equations should not be tampered with for they are correct for the entered polynomial. If the polynomial you want to generate Verilog code for is not in the menu, select the Enter your polynomial option. Then enter your polynomial. For example, the PCI Express DLLP CRC16 polynomial would be entered as: 10001000000001011.
This CRC generator program is very useful for generating the equations necessary for PCI Express 32-bit LCRC, scrambler LFSR, and 16-bit DLLP CRC equations. One needs to remember that once the PCI express CRC has been calculated it first needs to bit swapped and bit inverted before being tacked onto the end of a TLP or DLLP. Below shows how this would be accomplished for PCI Express 32-bit LCRC.
assign lcrcN = {(~lcrc[0] ,~lcrc[1],~lcrc[2],~lcrc[3],~lcrc[4],~lcrc[5],~lcrc[6],~lcrc[7],
~lcrc[8],~lcrc[9],~lcrc[10],~lcrc[11],~lcrc[12],~lcrc[13],~lcrc[14],~lcrc[15],
~lcrc[16],~lcrc[17],~lcrc[18],~lcrc[19],~lcrc[20],~lcrc[21],~lcrc[22],~lcrc[23],
~lcrc[24],~lcrc[25],~lcrc[26],~lcrc[27],~lcrc[28],~lcrc[29],~lcrc[30],~lcrc[31]};
Supported Polynomials
There are several common generator polynomials as follows:
CRC8, ATM (HEC)
x8 + x2 + x + 1
CRC10, ATM (OAM Cell)
x10 + x9 + x5 + x4 +x +1
CANbus
x15 + x14 + x10 + x8 + x7 + x4 + x3 + 1
CRC16
x16 + x12 + x2 + 1
CRC16 inverted
x16 + x14 + x + 1
PCI Express DLLP CRC16
x16 + x12 + x3 + x + 1
X25 (SDLC, HDLC, CRC-CCITT)
x16 + x12 + x5 + 1
PCI Express LCRC
x32 + x26 + x23 + x22 + x16 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
CRC32 (Ethernet, FDDI)
x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
User-defined polynomials up to 32nd order (comparable to CRC32, for example) are supported.
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