-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Title : core64_pb_disp
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-- Title : core64_pb_disp
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-- Author : Dmitry Smekhov
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-- Author : Dmitry Smekhov
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-- Company : Instrumental Systems
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-- Company : Instrumental Systems
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-- E-mail : dsmv@insys.ru
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-- E-mail : dsmv@insys.ru
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--
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--
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-- Version : 1.2
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-- Version : 1.2
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Description : Диспетчер шины PB_BUS
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-- Description : Диспетчер шины PB_BUS
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Version 1.2 14.12.2011 Dmitry Smekhov
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-- Version 1.2 14.12.2011 Dmitry Smekhov
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-- Исправлено формирование сигналов reg_disp_back.data_we,
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-- Исправлено формирование сигналов reg_disp_back.data_we,
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-- reg_disp_back.complete
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-- reg_disp_back.complete
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--
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--
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Version 1.1 28.09.2011 Dmitry Smekhov
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-- Version 1.1 28.09.2011 Dmitry Smekhov
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-- Добавлен сигнал pb_slave.complete
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-- Добавлен сигнал pb_slave.complete
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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|
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use work.core64_type_pkg.all;
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use work.core64_type_pkg.all;
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|
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package core64_pb_disp_pkg is
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package core64_pb_disp_pkg is
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|
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component core64_pb_disp is
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component core64_pb_disp is
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port(
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port(
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--- General ---
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--- General ---
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rstp : in std_logic; --! 1 - сброс
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rstp : in std_logic; --! 1 - сброс
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clk : in std_logic; --! тактовая частота ядра - 250 MHz
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clk : in std_logic; --! тактовая частота ядра - 250 MHz
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|
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---- PB_DISP ----
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---- PB_DISP ----
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reg_disp : in type_reg_disp; --! запрос на доступ к регистрам из BAR1
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reg_disp : in type_reg_disp; --! запрос на доступ к регистрам из BAR1
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reg_disp_back : out type_reg_disp_back; --! ответ на запрос
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reg_disp_back : out type_reg_disp_back; --! ответ на запрос
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|
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---- EXT_FIFO ----
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---- EXT_FIFO ----
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ext_fifo_disp : in type_ext_fifo_disp; --! запрос на доступ от узла EXT_FIFO
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ext_fifo_disp : in type_ext_fifo_disp; --! запрос на доступ от узла EXT_FIFO
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ext_fifo_disp_back : out type_ext_fifo_disp_back; --! ответ на запрос
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ext_fifo_disp_back : out type_ext_fifo_disp_back; --! ответ на запрос
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---- BAR1 ----
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---- BAR1 ----
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aclk : in std_logic; --! тактовая частота локальной шины - 266 МГц
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aclk : in std_logic; --! тактовая частота локальной шины - 266 МГц
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pb_master : out type_pb_master; --! запрос
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pb_master : out type_pb_master; --! запрос
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pb_slave : in type_pb_slave --! ответ
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pb_slave : in type_pb_slave --! ответ
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);
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);
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end component;
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end component;
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end package;
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end package;
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library unisim;
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library unisim;
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use unisim.vcomponents.all;
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use unisim.vcomponents.all;
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use work.core64_type_pkg.all;
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use work.core64_type_pkg.all;
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entity core64_pb_disp is
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entity core64_pb_disp is
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port(
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port(
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--- General ---
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--- General ---
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rstp : in std_logic; --! 1 - сброс
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rstp : in std_logic; --! 1 - сброс
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clk : in std_logic; --! тактовая частота ядра - 250 MHz
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clk : in std_logic; --! тактовая частота ядра - 250 MHz
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---- PB_DISP ----
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---- PB_DISP ----
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reg_disp : in type_reg_disp; --! запрос на доступ к регистрам из BAR1
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reg_disp : in type_reg_disp; --! запрос на доступ к регистрам из BAR1
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reg_disp_back : out type_reg_disp_back; --! ответ на запрос
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reg_disp_back : out type_reg_disp_back; --! ответ на запрос
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---- EXT_FIFO ----
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---- EXT_FIFO ----
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ext_fifo_disp : in type_ext_fifo_disp; --! запрос на доступ от узла EXT_FIFO
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ext_fifo_disp : in type_ext_fifo_disp; --! запрос на доступ от узла EXT_FIFO
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ext_fifo_disp_back : out type_ext_fifo_disp_back; --! ответ на запрос
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ext_fifo_disp_back : out type_ext_fifo_disp_back; --! ответ на запрос
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---- BAR1 ----
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---- BAR1 ----
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aclk : in std_logic; --! тактовая частота локальной шины - 266 МГц
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aclk : in std_logic; --! тактовая частота локальной шины - 266 МГц
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pb_master : out type_pb_master; --! запрос
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pb_master : out type_pb_master; --! запрос
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pb_slave : in type_pb_slave --! ответ
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pb_slave : in type_pb_slave --! ответ
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);
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);
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end core64_pb_disp;
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end core64_pb_disp;
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architecture core64_pb_disp of core64_pb_disp is
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architecture core64_pb_disp of core64_pb_disp is
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signal reg_req_wr : std_logic;
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signal reg_req_wr : std_logic;
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signal reg_req_wr_z : std_logic;
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signal reg_req_wr_z : std_logic;
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signal reg_req_rd : std_logic;
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signal reg_req_rd : std_logic;
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signal reg_req_rd_z : std_logic;
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signal reg_req_rd_z : std_logic;
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signal pb_sel : std_logic;
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signal pb_sel : std_logic;
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signal master_data : std_logic_vector( 63 downto 0 );
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signal master_data : std_logic_vector( 63 downto 0 );
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signal master_stb0 : std_logic;
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signal master_stb0 : std_logic;
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signal master_stb1 : std_logic;
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signal master_stb1 : std_logic;
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signal master_cmd : std_logic_vector( 2 downto 0 );
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signal master_cmd : std_logic_vector( 2 downto 0 );
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signal reg_stb1 : std_logic;
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signal reg_stb1 : std_logic;
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signal rstpz : std_logic;
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signal rstpz : std_logic;
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type stp_type is ( s0, sr1, sr2, sr3, sr5, sf1, sf2, sf3 );
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type stp_type is ( s0, sr1, sr2, sr3, sr5, sf1, sf2, sf3 );
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signal stp : stp_type;
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signal stp : stp_type;
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signal pb_slave_stb1_z : std_logic;
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signal pb_slave_stb1_z : std_logic;
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signal ex_fifo_stb1_z : std_logic;
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signal ex_fifo_stb1_z : std_logic;
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signal ext_fifo_eot : std_logic;
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signal ext_fifo_eot : std_logic;
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signal master_adr : std_logic_vector( 31 downto 0 );
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signal master_adr : std_logic_vector( 31 downto 0 );
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signal dmar : std_logic_vector( 1 downto 0 );
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signal dmar : std_logic_vector( 1 downto 0 );
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signal fifo_allow_wr : std_logic;
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signal fifo_allow_wr : std_logic;
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signal fifo_data_en : std_logic;
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signal fifo_data_en : std_logic;
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signal reg_data_we_set : std_logic;
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signal reg_data_we_set : std_logic;
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signal reg_data_we : std_logic;
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signal reg_data_we : std_logic;
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signal reg_data_we_z1 : std_logic;
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signal reg_data_we_z1 : std_logic;
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signal reg_data_we_z2 : std_logic;
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signal reg_data_we_z2 : std_logic;
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signal reg_data_we_clr : std_logic;
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signal reg_data_we_clr : std_logic;
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signal reg_data_we_clr_z1 : std_logic;
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signal reg_data_we_clr_z1 : std_logic;
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signal reg_data_we_clr_z2 : std_logic;
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signal reg_data_we_clr_z2 : std_logic;
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signal reg_complete : std_logic;
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signal reg_complete : std_logic;
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signal timeout_cnt : std_logic_vector( 12 downto 0 );
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signal slave_timeout : std_logic;
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attribute tig : string;
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attribute tig : string;
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attribute tig of master_adr : signal is "";
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attribute tig of master_adr : signal is "";
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attribute tig of dmar : signal is "";
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attribute tig of dmar : signal is "";
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attribute tig of rstp : signal is "";
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attribute tig of rstp : signal is "";
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begin
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begin
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rstpz <= rstp after 1 ns when rising_edge( aclk );
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rstpz <= rstp after 1 ns when rising_edge( aclk );
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reg_req_wr <= reg_disp.request_reg_wr after 1 ns when rising_edge( aclk );
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reg_req_wr <= reg_disp.request_reg_wr after 1 ns when rising_edge( aclk );
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reg_req_wr_z <= reg_req_wr after 1 ns when rising_edge( aclk );
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reg_req_wr_z <= reg_req_wr after 1 ns when rising_edge( aclk );
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reg_req_rd <= reg_disp.request_reg_rd after 1 ns when rising_edge( aclk );
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reg_req_rd <= reg_disp.request_reg_rd after 1 ns when rising_edge( aclk );
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reg_req_rd_z <= reg_req_rd after 1 ns when rising_edge( aclk );
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reg_req_rd_z <= reg_req_rd after 1 ns when rising_edge( aclk );
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master_adr <= reg_disp.adr when pb_sel='0' else ext_fifo_disp.adr;
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master_adr <= reg_disp.adr when pb_sel='0' else ext_fifo_disp.adr;
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pb_master.adr <= master_adr;
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pb_master.adr <= master_adr;
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master_data( 31 downto 0 ) <= reg_disp.data when pb_sel='0' else ext_fifo_disp.data( 31 downto 0 );
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master_data( 31 downto 0 ) <= reg_disp.data when pb_sel='0' else ext_fifo_disp.data( 31 downto 0 );
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master_data( 63 downto 32 ) <= ext_fifo_disp.data( 63 downto 32 );
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master_data( 63 downto 32 ) <= ext_fifo_disp.data( 63 downto 32 );
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master_stb1 <= reg_stb1 or ext_fifo_disp.data_we;
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master_stb1 <= reg_stb1 or ext_fifo_disp.data_we;
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pb_master.data <= master_data after 1 ns when rising_edge( aclk );
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pb_master.data <= master_data after 1 ns when rising_edge( aclk );
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pb_master.cmd <= master_cmd;
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pb_master.cmd <= master_cmd;
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pb_master.stb0 <= master_stb0 after 1 ns when rising_edge( aclk );
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pb_master.stb0 <= master_stb0 after 1 ns when rising_edge( aclk );
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pb_master.stb1 <= master_stb1 after 1 ns when rising_edge( aclk );
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pb_master.stb1 <= master_stb1 after 1 ns when rising_edge( aclk );
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reg_disp_back.data <= pb_slave.data( 31 downto 0 ) after 1 ns when rising_edge( aclk ) and pb_slave.stb1='1';
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reg_disp_back.data <= pb_slave.data( 31 downto 0 ) after 1 ns when rising_edge( aclk ) and pb_slave.stb1='1';
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ext_fifo_disp_back.data <= pb_slave.data after 1 ns when rising_edge( aclk );
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ext_fifo_disp_back.data <= pb_slave.data after 1 ns when rising_edge( aclk );
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ext_fifo_disp_back.data_we <= pb_slave.stb1 and fifo_data_en after 1 ns when rising_edge( aclk );
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ext_fifo_disp_back.data_we <= pb_slave.stb1 and fifo_data_en after 1 ns when rising_edge( aclk );
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dmar <= pb_slave.dmar;
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dmar <= pb_slave.dmar;
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ext_fifo_disp_back.dmar <= dmar;
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ext_fifo_disp_back.dmar <= dmar;
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ext_fifo_disp_back.irq <= pb_slave.irq;
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ext_fifo_disp_back.irq <= pb_slave.irq;
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pb_sel <= master_cmd(2) after 1 ns;
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pb_sel <= master_cmd(2) after 1 ns;
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pr_state: process( aclk ) begin
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pr_state: process( aclk ) begin
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if( rising_edge( aclk ) ) then
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if( rising_edge( aclk ) ) then
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case( stp ) is
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case( stp ) is
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when s0 =>
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when s0 =>
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master_cmd <= "000" after 1 ns;
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master_cmd <= "000" after 1 ns;
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master_stb0 <= '0' after 1 ns;
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master_stb0 <= '0' after 1 ns;
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--reg_disp_back.complete <= '0' after 1 ns;
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--reg_disp_back.complete <= '0' after 1 ns;
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reg_complete <= '0' after 1 ns;
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reg_complete <= '0' after 1 ns;
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reg_data_we_set <= '0' after 1 ns;
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reg_data_we_set <= '0' after 1 ns;
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fifo_allow_wr <= '0' after 1 ns;
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fifo_allow_wr <= '0' after 1 ns;
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reg_stb1 <= '0' after 1 ns;
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reg_stb1 <= '0' after 1 ns;
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fifo_data_en <= '0' after 1 ns;
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fifo_data_en <= '0' after 1 ns;
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ext_fifo_disp_back.complete <= '0' after 1 ns;
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ext_fifo_disp_back.complete <= '0' after 1 ns;
|
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timeout_cnt <= (others=>'0') after 1 ns;
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|
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if( reg_req_wr_z='1' or reg_req_rd_z='1' ) then
|
if( reg_req_wr_z='1' or reg_req_rd_z='1' ) then
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stp <= sr1 after 1 ns;
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stp <= sr1 after 1 ns;
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elsif( ext_fifo_disp.request_wr='1' or ext_fifo_disp.request_rd='1' ) then
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elsif( ext_fifo_disp.request_wr='1' or ext_fifo_disp.request_rd='1' ) then
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stp <= sf1 after 1 ns;
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stp <= sf1 after 1 ns;
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end if;
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end if;
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|
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when sr1 => ---- Обращение к регистрам ----
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when sr1 => ---- Обращение к регистрам ----
|
master_cmd(0) <= reg_req_wr_z after 1 ns; -- 1 - запись
|
master_cmd(0) <= reg_req_wr_z after 1 ns; -- 1 - запись
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master_cmd(1) <= reg_req_rd_z after 1 ns; -- 1 - чтение
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master_cmd(1) <= reg_req_rd_z after 1 ns; -- 1 - чтение
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master_cmd(2) <= '0'; -- только одно 32-х разрядное слово
|
master_cmd(2) <= '0'; -- только одно 32-х разрядное слово
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master_stb0 <= '1' after 1 ns; -- строб команды
|
master_stb0 <= '1' after 1 ns; -- строб команды
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stp <= sr2 after 1 ns;
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stp <= sr2 after 1 ns;
|
|
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when sr2 => ---- Строб записи слова ----
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when sr2 => ---- Строб записи слова ----
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master_stb0 <= '0' after 1 ns;
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master_stb0 <= '0' after 1 ns;
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reg_stb1 <= reg_req_wr_z after 1 ns;
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reg_stb1 <= reg_req_wr_z after 1 ns;
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stp <= sr3 after 1 ns;
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stp <= sr3 after 1 ns;
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|
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|
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when sr3 => ---- Ожидание подтверждения команды ---
|
when sr3 => ---- Ожидание подтверждения команды ---
|
reg_stb1 <= '0' after 1 ns;
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reg_stb1 <= '0' after 1 ns;
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-- if( pb_slave.stb0='1' ) then
|
-- if( pb_slave.stb0='1' ) then
|
-- if( reg_req_rd_z='1' ) then
|
-- if( reg_req_rd_z='1' ) then
|
-- stp <= sr4 after 1 ns;
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-- stp <= sr4 after 1 ns;
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-- else
|
-- else
|
-- stp <= sr5 after 1 ns;
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-- stp <= sr5 after 1 ns;
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-- end if;
|
-- end if;
|
-- end if;
|
-- end if;
|
|
timeout_cnt <= timeout_cnt + 1 after 1 ns;
|
reg_data_we_set <= pb_slave.stb1 after 1 ns;
|
reg_data_we_set <= pb_slave.stb1 after 1 ns;
|
if( pb_slave.complete='1' ) then
|
if( pb_slave.complete='1' or slave_timeout='1') then
|
stp <= sr5 after 1 ns;
|
stp <= sr5 after 1 ns;
|
end if;
|
end if;
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|
|
|
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-- when sr4 => ---- Ожидание данных ----
|
-- when sr4 => ---- Ожидание данных ----
|
-- if( pb_slave.stb1='1' ) then
|
-- if( pb_slave.stb1='1' ) then
|
-- reg_disp_back.data_we <= '1' after 1 ns;
|
-- reg_disp_back.data_we <= '1' after 1 ns;
|
-- stp <= sr5 after 1 ns;
|
-- stp <= sr5 after 1 ns;
|
-- end if;
|
-- end if;
|
|
|
when sr5 => ---- Ожидание снятия запроса ----
|
when sr5 => ---- Ожидание снятия запроса ----
|
master_cmd <= "000";
|
master_cmd <= "000";
|
reg_data_we_set <= '0' after 1 ns;
|
reg_data_we_set <= '0' after 1 ns;
|
--reg_disp_back.complete <= '1' after 1 ns;
|
--reg_disp_back.complete <= '1' after 1 ns;
|
reg_complete <= '1' after 1 ns;
|
reg_complete <= '1' after 1 ns;
|
if( reg_req_wr_z='0' and reg_req_rd_z='0' ) then
|
if( reg_req_wr_z='0' and reg_req_rd_z='0' ) then
|
stp <= s0 after 1 ns;
|
stp <= s0 after 1 ns;
|
end if;
|
end if;
|
|
|
|
|
|
|
when sf1 =>
|
when sf1 =>
|
master_cmd(0) <= ext_fifo_disp.request_wr after 1 ns; -- 1 - запись
|
master_cmd(0) <= ext_fifo_disp.request_wr after 1 ns; -- 1 - запись
|
master_cmd(1) <= ext_fifo_disp.request_rd after 1 ns; -- 1 - чтение
|
master_cmd(1) <= ext_fifo_disp.request_rd after 1 ns; -- 1 - чтение
|
master_cmd(2) <= '1'; -- блок 512 слов
|
master_cmd(2) <= '1'; -- блок 512 слов
|
master_stb0 <= '1' after 1 ns; -- строб команды
|
master_stb0 <= '1' after 1 ns; -- строб команды
|
stp <= sf2 after 1 ns;
|
stp <= sf2 after 1 ns;
|
|
|
when sf2 =>
|
when sf2 =>
|
master_stb0 <= '0' after 1 ns; -- строб команды
|
master_stb0 <= '0' after 1 ns; -- строб команды
|
fifo_allow_wr <= ext_fifo_disp.request_wr and pb_slave.ready after 1 ns;
|
fifo_allow_wr <= ext_fifo_disp.request_wr and pb_slave.ready after 1 ns;
|
fifo_data_en <= '1' after 1 ns;
|
fifo_data_en <= '1' after 1 ns;
|
if( pb_slave.complete='1' ) then
|
timeout_cnt <= timeout_cnt + 1 after 1 ns;
|
|
if( pb_slave.complete='1' or slave_timeout='1' ) then
|
ext_fifo_disp_back.complete <= '1' after 1 ns;
|
ext_fifo_disp_back.complete <= '1' after 1 ns;
|
stp <= sf3 after 1 ns;
|
stp <= sf3 after 1 ns;
|
end if;
|
end if;
|
|
|
when sf3 =>
|
when sf3 =>
|
ext_fifo_disp_back.complete <= '0' after 1 ns;
|
ext_fifo_disp_back.complete <= '0' after 1 ns;
|
fifo_allow_wr <= '0' after 1 ns;
|
fifo_allow_wr <= '0' after 1 ns;
|
if( ext_fifo_disp.request_wr='0' and ext_fifo_disp.request_rd='0' ) then
|
if( ext_fifo_disp.request_wr='0' and ext_fifo_disp.request_rd='0' ) then
|
stp <= s0 after 1 ns;
|
stp <= s0 after 1 ns;
|
end if;
|
end if;
|
|
|
|
|
end case;
|
end case;
|
|
|
if( rstpz='1' ) then
|
if( rstpz='1' ) then
|
stp <= s0 after 1 ns;
|
stp <= s0 after 1 ns;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
slave_timeout <= timeout_cnt(12) after 1 ns when rising_edge( clk );
|
|
|
ext_fifo_disp_back.allow_wr <= fifo_allow_wr;
|
ext_fifo_disp_back.allow_wr <= fifo_allow_wr;
|
|
|
pb_slave_stb1_z <= pb_slave.stb1 after 1 ns when rising_edge( aclk );
|
pb_slave_stb1_z <= pb_slave.stb1 after 1 ns when rising_edge( aclk );
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ex_fifo_stb1_z <= ext_fifo_disp.data_we after 1 ns when rising_edge( aclk );
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ex_fifo_stb1_z <= ext_fifo_disp.data_we after 1 ns when rising_edge( aclk );
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--ext_fifo_eot <= (pb_slave_stb1_z and not pb_slave.stb1) or
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--ext_fifo_eot <= (pb_slave_stb1_z and not pb_slave.stb1) or
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-- (ex_fifo_stb1_z and not ext_fifo_disp.data_we ) after 1 ns when rising_edge( aclk );
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-- (ex_fifo_stb1_z and not ext_fifo_disp.data_we ) after 1 ns when rising_edge( aclk );
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--
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--
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--ext_fifo_eot <= pb_slave.complete after 1 ns when rising_edge( clk );
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--ext_fifo_eot <= pb_slave.complete after 1 ns when rising_edge( clk );
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pr_reg_data_we: process( aclk ) begin
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pr_reg_data_we: process( aclk ) begin
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if( rising_edge( aclk ) ) then
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if( rising_edge( aclk ) ) then
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if( reg_data_we_clr_z2='1' ) then
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if( reg_data_we_clr_z2='1' ) then
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reg_data_we <= '0' after 1 ns;
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reg_data_we <= '0' after 1 ns;
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elsif( reg_data_we_set='1' ) then
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elsif( reg_data_we_set='1' ) then
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reg_data_we <= '1' after 1 ns;
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reg_data_we <= '1' after 1 ns;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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reg_data_we_z1 <= reg_data_we after 1 ns when rising_edge( clk );
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reg_data_we_z1 <= reg_data_we after 1 ns when rising_edge( clk );
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reg_data_we_z2 <= reg_data_we_z1 after 1 ns when rising_edge( clk );
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reg_data_we_z2 <= reg_data_we_z1 after 1 ns when rising_edge( clk );
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reg_disp_back.data_we <= reg_data_we_z2 and reg_disp.request_reg_rd after 1 ns when rising_edge( clk );
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reg_disp_back.data_we <= reg_data_we_z2 and reg_disp.request_reg_rd after 1 ns when rising_edge( clk );
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reg_data_we_clr <= reg_data_we_z2 after 1 ns when rising_edge( aclk );
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reg_data_we_clr <= reg_data_we_z2 after 1 ns when rising_edge( aclk );
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reg_data_we_clr_z1 <= reg_data_we_clr after 1 ns when rising_edge( aclk );
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reg_data_we_clr_z1 <= reg_data_we_clr after 1 ns when rising_edge( aclk );
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reg_data_we_clr_z2 <= reg_data_we_clr_z1 after 1 ns when rising_edge( aclk );
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reg_data_we_clr_z2 <= reg_data_we_clr_z1 after 1 ns when rising_edge( aclk );
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xcomlete: srl16 port map( q=>reg_disp_back.complete, clk=>clk, d=>reg_complete, a3=>'0', a2=>'0', a1=>'1', a0=>'0' );
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xcomlete: srl16 port map( q=>reg_disp_back.complete, clk=>clk, d=>reg_complete, a3=>'0', a2=>'0', a1=>'1', a0=>'0' );
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end core64_pb_disp;
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end core64_pb_disp;
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