-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
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--
|
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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--
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--
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-- This file contains confidential and proprietary information
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- international copyright and other intellectual property
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-- laws.
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-- laws.
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--
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--
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-- DISCLAIMER
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- rights to the materials distributed herewith. Except as
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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|
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|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Project : Series-7 Integrated Block for PCI Express
|
-- Project : Series-7 Integrated Block for PCI Express
|
-- File : cl_a7pcie_x4_axi_basic_rx.vhd
|
-- File : cl_a7pcie_x4_axi_basic_rx.vhd
|
-- Version : 1.10
|
-- Version : 1.11
|
-- Description:
|
-- Description:
|
-- TRN to AXI RX module. Instantiates pipeline and null generator RX
|
-- TRN to AXI RX module. Instantiates pipeline and null generator RX
|
-- submodules.
|
-- submodules.
|
--
|
--
|
-- Notes:
|
-- Notes:
|
-- Optional notes section.
|
-- Optional notes section.
|
--
|
--
|
-- Hierarchical:
|
-- Hierarchical:
|
-- axi_basic_top
|
-- axi_basic_top
|
-- axi_basic_rx
|
-- axi_basic_rx
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Library Declarations
|
-- Library Declarations
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
LIBRARY ieee;
|
LIBRARY ieee;
|
USE ieee.std_logic_1164.all;
|
USE ieee.std_logic_1164.all;
|
USE ieee.std_logic_unsigned.all;
|
USE ieee.std_logic_unsigned.all;
|
|
|
|
|
ENTITY cl_a7pcie_x4_axi_basic_rx IS
|
ENTITY cl_a7pcie_x4_axi_basic_rx IS
|
GENERIC (
|
GENERIC (
|
C_DATA_WIDTH : INTEGER := 128; -- RX/TX interface data width
|
C_DATA_WIDTH : INTEGER := 128; -- RX/TX interface data width
|
C_FAMILY : STRING := "X7"; -- Targeted FPGA family
|
C_FAMILY : STRING := "X7"; -- Targeted FPGA family
|
C_ROOT_PORT : BOOLEAN := FALSE; -- PCIe block is in root port mode
|
C_ROOT_PORT : BOOLEAN := FALSE; -- PCIe block is in root port mode
|
C_PM_PRIORITY : BOOLEAN := FALSE; -- Disable TX packet boundary thrtl
|
C_PM_PRIORITY : BOOLEAN := FALSE; -- Disable TX packet boundary thrtl
|
TCQ : INTEGER := 1; -- Clock to Q time
|
TCQ : INTEGER := 1; -- Clock to Q time
|
|
|
C_REM_WIDTH : INTEGER := 1 -- trem/rrem width
|
C_REM_WIDTH : INTEGER := 1 -- trem/rrem width
|
|
|
);
|
);
|
PORT (
|
PORT (
|
-------------------------------------------------
|
-------------------------------------------------
|
-- User Design I/O --
|
-- User Design I/O --
|
-------------------------------------------------
|
-------------------------------------------------
|
-- AXI RX
|
-- AXI RX
|
-------------
|
-------------
|
|
|
M_AXIS_RX_TDATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0):=(OTHERS=>'0'); -- RX data to user
|
M_AXIS_RX_TDATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0):=(OTHERS=>'0'); -- RX data to user
|
M_AXIS_RX_TVALID : OUT STD_LOGIC :='0'; -- RX data is valid
|
M_AXIS_RX_TVALID : OUT STD_LOGIC :='0'; -- RX data is valid
|
M_AXIS_RX_TREADY : IN STD_LOGIC :='0'; -- RX ready for data
|
M_AXIS_RX_TREADY : IN STD_LOGIC :='0'; -- RX ready for data
|
m_axis_rx_tkeep : OUT STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0):=(OTHERS=>'0'); -- RX strobe byte enables
|
m_axis_rx_tkeep : OUT STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0):=(OTHERS=>'0'); -- RX strobe byte enables
|
M_AXIS_RX_TLAST : OUT STD_LOGIC :='0'; -- RX data is last
|
M_AXIS_RX_TLAST : OUT STD_LOGIC :='0'; -- RX data is last
|
M_AXIS_RX_TUSER : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) :=(OTHERS=>'0'); -- RX user signals
|
M_AXIS_RX_TUSER : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) :=(OTHERS=>'0'); -- RX user signals
|
-------------------------------------------------
|
-------------------------------------------------
|
-- PCIe Block I/O --
|
-- PCIe Block I/O --
|
-------------------------------------------------
|
-------------------------------------------------
|
-- TRN RX
|
-- TRN RX
|
-------------
|
-------------
|
TRN_RD : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) :=(OTHERS=>'0'); -- RX data from block
|
TRN_RD : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) :=(OTHERS=>'0'); -- RX data from block
|
TRN_RSOF : IN STD_LOGIC :='0'; -- RX start of packet
|
TRN_RSOF : IN STD_LOGIC :='0'; -- RX start of packet
|
TRN_REOF : IN STD_LOGIC :='0'; -- RX end of packet
|
TRN_REOF : IN STD_LOGIC :='0'; -- RX end of packet
|
TRN_RSRC_RDY : IN STD_LOGIC :='0'; -- RX source ready
|
TRN_RSRC_RDY : IN STD_LOGIC :='0'; -- RX source ready
|
TRN_RDST_RDY : OUT STD_LOGIC :='0'; -- RX destination ready
|
TRN_RDST_RDY : OUT STD_LOGIC :='0'; -- RX destination ready
|
TRN_RSRC_DSC : IN STD_LOGIC :='0'; -- RX source discontinue
|
TRN_RSRC_DSC : IN STD_LOGIC :='0'; -- RX source discontinue
|
TRN_RREM : IN STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0) :=(OTHERS=>'0'); -- RX remainder
|
TRN_RREM : IN STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0) :=(OTHERS=>'0'); -- RX remainder
|
TRN_RERRFWD : IN STD_LOGIC :='0'; -- RX error forward
|
TRN_RERRFWD : IN STD_LOGIC :='0'; -- RX error forward
|
TRN_RBAR_HIT : IN STD_LOGIC_VECTOR(6 DOWNTO 0) :=(OTHERS=>'0'); -- RX BAR hit
|
TRN_RBAR_HIT : IN STD_LOGIC_VECTOR(6 DOWNTO 0) :=(OTHERS=>'0'); -- RX BAR hit
|
TRN_RECRC_ERR : IN STD_LOGIC :='0'; -- RX ECRC error
|
TRN_RECRC_ERR : IN STD_LOGIC :='0'; -- RX ECRC error
|
|
|
-- System
|
-- System
|
-------------
|
-------------
|
NP_COUNTER : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) :=(OTHERS=>'0'); -- Non-posted counter
|
NP_COUNTER : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) :=(OTHERS=>'0'); -- Non-posted counter
|
USER_CLK : IN STD_LOGIC :='0'; -- user clock from block
|
USER_CLK : IN STD_LOGIC :='0'; -- user clock from block
|
USER_RST : IN STD_LOGIC :='0' -- user reset from block
|
USER_RST : IN STD_LOGIC :='0' -- user reset from block
|
);
|
);
|
END cl_a7pcie_x4_axi_basic_rx;
|
END cl_a7pcie_x4_axi_basic_rx;
|
|
|
-------------------------------------------------
|
-------------------------------------------------
|
-- RX Data Pipeline --
|
-- RX Data Pipeline --
|
-------------------------------------------------
|
-------------------------------------------------
|
|
|
|
|
ARCHITECTURE TRANS OF cl_a7pcie_x4_axi_basic_rx IS
|
ARCHITECTURE TRANS OF cl_a7pcie_x4_axi_basic_rx IS
|
|
|
SIGNAL null_rx_tvalid : STD_LOGIC;
|
SIGNAL null_rx_tvalid : STD_LOGIC:= '0';
|
SIGNAL null_rx_tlast : STD_LOGIC;
|
SIGNAL null_rx_tlast : STD_LOGIC:= '0';
|
SIGNAL null_rx_tkeep : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0);
|
SIGNAL null_rx_tkeep : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0):= (others => '0');
|
SIGNAL null_rdst_rdy : STD_LOGIC;
|
SIGNAL null_rdst_rdy : STD_LOGIC:= '0';
|
SIGNAL null_is_eof : STD_LOGIC_VECTOR(4 DOWNTO 0);
|
SIGNAL null_is_eof : STD_LOGIC_VECTOR(4 DOWNTO 0):= (others => '0');
|
|
|
-- Declare intermediate signals for referenced outputs
|
-- Declare intermediate signals for referenced outputs
|
SIGNAL m_axis_rx_tdata_xhdl0 : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0);
|
SIGNAL m_axis_rx_tdata_xhdl0 : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0):= (others => '0');
|
SIGNAL m_axis_rx_tvalid_xhdl4 : STD_LOGIC;
|
SIGNAL m_axis_rx_tvalid_xhdl4 : STD_LOGIC:= '0';
|
SIGNAL m_axis_rx_tkeep_xhdl2 : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0);
|
SIGNAL m_axis_rx_tkeep_xhdl2 : STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0):= (others => '0');
|
SIGNAL m_axis_rx_tlast_xhdl1 : STD_LOGIC;
|
SIGNAL m_axis_rx_tlast_xhdl1 : STD_LOGIC:= '0';
|
SIGNAL m_axis_rx_tuser_xhdl3 : STD_LOGIC_VECTOR(21 DOWNTO 0);
|
SIGNAL m_axis_rx_tuser_xhdl3 : STD_LOGIC_VECTOR(21 DOWNTO 0):= (others => '0');
|
SIGNAL trn_rdst_rdy_xhdl6 : STD_LOGIC;
|
SIGNAL trn_rdst_rdy_xhdl6 : STD_LOGIC:= '0';
|
SIGNAL np_counter_xhdl5 : STD_LOGIC_VECTOR(2 DOWNTO 0);
|
SIGNAL np_counter_xhdl5 : STD_LOGIC_VECTOR(2 DOWNTO 0):= (others => '0');
|
|
|
COMPONENT cl_a7pcie_x4_axi_basic_rx_null_gen IS
|
COMPONENT cl_a7pcie_x4_axi_basic_rx_null_gen IS
|
GENERIC (
|
GENERIC (
|
C_DATA_WIDTH : INTEGER := 128;
|
C_DATA_WIDTH : INTEGER := 128;
|
TCQ : INTEGER := 1
|
TCQ : INTEGER := 1
|
);
|
);
|
PORT (
|
PORT (
|
M_AXIS_RX_TDATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
|
M_AXIS_RX_TDATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
|
M_AXIS_RX_TVALID : IN STD_LOGIC := '0';
|
M_AXIS_RX_TVALID : IN STD_LOGIC := '0';
|
M_AXIS_RX_TREADY : IN STD_LOGIC := '0';
|
M_AXIS_RX_TREADY : IN STD_LOGIC := '0';
|
M_AXIS_RX_TLAST : IN STD_LOGIC := '0';
|
M_AXIS_RX_TLAST : IN STD_LOGIC := '0';
|
M_AXIS_RX_TUSER : IN STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS=>'0');
|
M_AXIS_RX_TUSER : IN STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS=>'0');
|
|
|
NULL_RX_TVALID : OUT STD_LOGIC := '0';
|
NULL_RX_TVALID : OUT STD_LOGIC := '0';
|
NULL_RX_TLAST : OUT STD_LOGIC := '0';
|
NULL_RX_TLAST : OUT STD_LOGIC := '0';
|
NULL_RX_tkeep : OUT STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0) := (OTHERS=>'0');
|
NULL_RX_tkeep : OUT STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0) := (OTHERS=>'0');
|
NULL_RDST_RDY : OUT STD_LOGIC := '0';
|
NULL_RDST_RDY : OUT STD_LOGIC := '0';
|
NULL_IS_EOF : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS=>'0');
|
NULL_IS_EOF : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS=>'0');
|
|
|
USER_CLK : IN STD_LOGIC := '0';
|
USER_CLK : IN STD_LOGIC := '0';
|
USER_RST : IN STD_LOGIC := '0'
|
USER_RST : IN STD_LOGIC := '0'
|
);
|
);
|
END COMPONENT cl_a7pcie_x4_axi_basic_rx_null_gen;
|
END COMPONENT cl_a7pcie_x4_axi_basic_rx_null_gen;
|
|
|
-------------------------------------------------
|
-------------------------------------------------
|
-- RX Data Pipeline --
|
-- RX Data Pipeline --
|
-------------------------------------------------
|
-------------------------------------------------
|
COMPONENT cl_a7pcie_x4_axi_basic_rx_pipeline IS
|
COMPONENT cl_a7pcie_x4_axi_basic_rx_pipeline IS
|
GENERIC (
|
GENERIC (
|
C_DATA_WIDTH : INTEGER := 128;
|
C_DATA_WIDTH : INTEGER := 128;
|
C_FAMILY : STRING := "X7";
|
C_FAMILY : STRING := "X7";
|
TCQ : INTEGER := 1;
|
TCQ : INTEGER := 1;
|
|
|
C_REM_WIDTH : INTEGER := 1
|
C_REM_WIDTH : INTEGER := 1
|
);
|
);
|
PORT (
|
PORT (
|
|
|
M_AXIS_RX_TDATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
|
M_AXIS_RX_TDATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
|
M_AXIS_RX_TVALID : OUT STD_LOGIC := '0';
|
M_AXIS_RX_TVALID : OUT STD_LOGIC := '0';
|
M_AXIS_RX_TREADY : IN STD_LOGIC := '0';
|
M_AXIS_RX_TREADY : IN STD_LOGIC := '0';
|
m_axis_rx_tkeep : OUT STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0) := (OTHERS=>'0');
|
m_axis_rx_tkeep : OUT STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0) := (OTHERS=>'0');
|
M_AXIS_RX_TLAST : OUT STD_LOGIC := '0';
|
M_AXIS_RX_TLAST : OUT STD_LOGIC := '0';
|
M_AXIS_RX_TUSER : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS=>'0');
|
M_AXIS_RX_TUSER : OUT STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS=>'0');
|
|
|
TRN_RD : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
|
TRN_RD : IN STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
|
TRN_RSOF : IN STD_LOGIC := '0';
|
TRN_RSOF : IN STD_LOGIC := '0';
|
TRN_REOF : IN STD_LOGIC := '0';
|
TRN_REOF : IN STD_LOGIC := '0';
|
TRN_RSRC_RDY : IN STD_LOGIC := '0';
|
TRN_RSRC_RDY : IN STD_LOGIC := '0';
|
TRN_RDST_RDY : OUT STD_LOGIC := '0';
|
TRN_RDST_RDY : OUT STD_LOGIC := '0';
|
TRN_RSRC_DSC : IN STD_LOGIC := '0';
|
TRN_RSRC_DSC : IN STD_LOGIC := '0';
|
TRN_RREM : IN STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
|
TRN_RREM : IN STD_LOGIC_VECTOR(C_REM_WIDTH - 1 DOWNTO 0) := (OTHERS=>'0');
|
TRN_RERRFWD : IN STD_LOGIC := '0';
|
TRN_RERRFWD : IN STD_LOGIC := '0';
|
TRN_RBAR_HIT : IN STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS=>'0');
|
TRN_RBAR_HIT : IN STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS=>'0');
|
TRN_RECRC_ERR : IN STD_LOGIC := '0';
|
TRN_RECRC_ERR : IN STD_LOGIC := '0';
|
|
|
NULL_RX_TVALID : IN STD_LOGIC := '0';
|
NULL_RX_TVALID : IN STD_LOGIC := '0';
|
NULL_RX_TLAST : IN STD_LOGIC := '0';
|
NULL_RX_TLAST : IN STD_LOGIC := '0';
|
NULL_RX_tkeep : IN STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0) := (OTHERS=>'0') ;
|
NULL_RX_tkeep : IN STD_LOGIC_VECTOR((C_DATA_WIDTH/8)-1 DOWNTO 0) := (OTHERS=>'0') ;
|
NULL_RDST_RDY : IN STD_LOGIC := '0';
|
NULL_RDST_RDY : IN STD_LOGIC := '0';
|
NULL_IS_EOF : IN STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS=>'0');
|
NULL_IS_EOF : IN STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS=>'0');
|
|
|
NP_COUNTER : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) :=(OTHERS=>'0');
|
NP_COUNTER : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) :=(OTHERS=>'0');
|
USER_CLK : IN STD_LOGIC :='0';
|
USER_CLK : IN STD_LOGIC :='0';
|
USER_RST : IN STD_LOGIC :='0'
|
USER_RST : IN STD_LOGIC :='0'
|
);
|
);
|
END COMPONENT cl_a7pcie_x4_axi_basic_rx_pipeline;
|
END COMPONENT cl_a7pcie_x4_axi_basic_rx_pipeline;
|
BEGIN
|
BEGIN
|
-- Drive referenced outputs
|
-- Drive referenced outputs
|
M_AXIS_RX_TDATA <= m_axis_rx_tdata_xhdl0;
|
M_AXIS_RX_TDATA <= m_axis_rx_tdata_xhdl0;
|
M_AXIS_RX_TVALID <= m_axis_rx_tvalid_xhdl4;
|
M_AXIS_RX_TVALID <= m_axis_rx_tvalid_xhdl4;
|
m_axis_rx_tkeep <= m_axis_rx_tkeep_xhdl2;
|
m_axis_rx_tkeep <= m_axis_rx_tkeep_xhdl2;
|
M_AXIS_RX_TLAST <= m_axis_rx_tlast_xhdl1;
|
M_AXIS_RX_TLAST <= m_axis_rx_tlast_xhdl1;
|
M_AXIS_RX_TUSER <= m_axis_rx_tuser_xhdl3;
|
M_AXIS_RX_TUSER <= m_axis_rx_tuser_xhdl3;
|
TRN_RDST_RDY <= trn_rdst_rdy_xhdl6;
|
TRN_RDST_RDY <= trn_rdst_rdy_xhdl6;
|
NP_COUNTER <= np_counter_xhdl5;
|
NP_COUNTER <= np_counter_xhdl5;
|
|
|
|
|
rx_pipeline_inst : cl_a7pcie_x4_axi_basic_rx_pipeline
|
rx_pipeline_inst : cl_a7pcie_x4_axi_basic_rx_pipeline
|
GENERIC MAP (
|
GENERIC MAP (
|
C_DATA_WIDTH => C_DATA_WIDTH,
|
C_DATA_WIDTH => C_DATA_WIDTH,
|
C_FAMILY => C_FAMILY,
|
C_FAMILY => C_FAMILY,
|
TCQ => TCQ,
|
TCQ => TCQ,
|
C_REM_WIDTH => C_REM_WIDTH
|
C_REM_WIDTH => C_REM_WIDTH
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
|
|
----------------------
|
----------------------
|
-- Outgoing AXI TX
|
-- Outgoing AXI TX
|
----------------------
|
----------------------
|
M_AXIS_RX_TDATA => m_axis_rx_tdata_xhdl0,
|
M_AXIS_RX_TDATA => m_axis_rx_tdata_xhdl0,
|
M_AXIS_RX_TVALID => m_axis_rx_tvalid_xhdl4,
|
M_AXIS_RX_TVALID => m_axis_rx_tvalid_xhdl4,
|
M_AXIS_RX_TREADY => M_AXIS_RX_TREADY,
|
M_AXIS_RX_TREADY => M_AXIS_RX_TREADY,
|
m_axis_rx_tkeep => m_axis_rx_tkeep_xhdl2,
|
m_axis_rx_tkeep => m_axis_rx_tkeep_xhdl2,
|
M_AXIS_RX_TLAST => m_axis_rx_tlast_xhdl1,
|
M_AXIS_RX_TLAST => m_axis_rx_tlast_xhdl1,
|
M_AXIS_RX_TUSER => m_axis_rx_tuser_xhdl3,
|
M_AXIS_RX_TUSER => m_axis_rx_tuser_xhdl3,
|
|
|
----------------------
|
----------------------
|
-- Incoming TRN RX
|
-- Incoming TRN RX
|
----------------------
|
----------------------
|
TRN_RD => TRN_RD,
|
TRN_RD => TRN_RD,
|
TRN_RSOF => TRN_RSOF,
|
TRN_RSOF => TRN_RSOF,
|
TRN_REOF => TRN_REOF,
|
TRN_REOF => TRN_REOF,
|
TRN_RSRC_RDY => TRN_RSRC_RDY,
|
TRN_RSRC_RDY => TRN_RSRC_RDY,
|
TRN_RDST_RDY => trn_rdst_rdy_xhdl6,
|
TRN_RDST_RDY => trn_rdst_rdy_xhdl6,
|
TRN_RSRC_DSC => TRN_RSRC_DSC,
|
TRN_RSRC_DSC => TRN_RSRC_DSC,
|
TRN_RREM => TRN_RREM,
|
TRN_RREM => TRN_RREM,
|
TRN_RERRFWD => TRN_RERRFWD,
|
TRN_RERRFWD => TRN_RERRFWD,
|
TRN_RBAR_HIT => TRN_RBAR_HIT,
|
TRN_RBAR_HIT => TRN_RBAR_HIT,
|
TRN_RECRC_ERR => TRN_RECRC_ERR,
|
TRN_RECRC_ERR => TRN_RECRC_ERR,
|
|
|
----------------------
|
----------------------
|
-- Null Inputs
|
-- Null Inputs
|
----------------------
|
----------------------
|
NULL_RX_TVALID => null_rx_tvalid,
|
NULL_RX_TVALID => null_rx_tvalid,
|
NULL_RX_TLAST => null_rx_tlast,
|
NULL_RX_TLAST => null_rx_tlast,
|
NULL_RX_tkeep => null_rx_tkeep,
|
NULL_RX_tkeep => null_rx_tkeep,
|
NULL_RDST_RDY => null_rdst_rdy,
|
NULL_RDST_RDY => null_rdst_rdy,
|
NULL_IS_EOF => null_is_eof,
|
NULL_IS_EOF => null_is_eof,
|
|
|
----------------------
|
----------------------
|
-- System
|
-- System
|
----------------------
|
----------------------
|
NP_COUNTER => np_counter_xhdl5,
|
NP_COUNTER => np_counter_xhdl5,
|
USER_CLK => USER_CLK,
|
USER_CLK => USER_CLK,
|
USER_RST => USER_RST
|
USER_RST => USER_RST
|
);
|
);
|
|
|
|
|
|
|
rx_null_gen_inst : cl_a7pcie_x4_axi_basic_rx_null_gen
|
rx_null_gen_inst : cl_a7pcie_x4_axi_basic_rx_null_gen
|
GENERIC MAP (
|
GENERIC MAP (
|
C_DATA_WIDTH => C_DATA_WIDTH,
|
C_DATA_WIDTH => C_DATA_WIDTH,
|
TCQ => TCQ
|
TCQ => TCQ
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
----------------------
|
----------------------
|
-- Inputs
|
-- Inputs
|
----------------------
|
----------------------
|
M_AXIS_RX_TDATA => m_axis_rx_tdata_xhdl0,
|
M_AXIS_RX_TDATA => m_axis_rx_tdata_xhdl0,
|
M_AXIS_RX_TVALID => m_axis_rx_tvalid_xhdl4,
|
M_AXIS_RX_TVALID => m_axis_rx_tvalid_xhdl4,
|
M_AXIS_RX_TREADY => M_AXIS_RX_TREADY,
|
M_AXIS_RX_TREADY => M_AXIS_RX_TREADY,
|
M_AXIS_RX_TLAST => m_axis_rx_tlast_xhdl1,
|
M_AXIS_RX_TLAST => m_axis_rx_tlast_xhdl1,
|
M_AXIS_RX_TUSER => m_axis_rx_tuser_xhdl3,
|
M_AXIS_RX_TUSER => m_axis_rx_tuser_xhdl3,
|
|
|
----------------------
|
----------------------
|
-- Null Outputs
|
-- Null Outputs
|
----------------------
|
----------------------
|
NULL_RX_TVALID => null_rx_tvalid,
|
NULL_RX_TVALID => null_rx_tvalid,
|
NULL_RX_TLAST => null_rx_tlast,
|
NULL_RX_TLAST => null_rx_tlast,
|
NULL_RX_tkeep => null_rx_tkeep,
|
NULL_RX_tkeep => null_rx_tkeep,
|
NULL_RDST_RDY => null_rdst_rdy,
|
NULL_RDST_RDY => null_rdst_rdy,
|
NULL_IS_EOF => null_is_eof,
|
NULL_IS_EOF => null_is_eof,
|
|
|
----------------------
|
----------------------
|
-- System
|
-- System
|
----------------------
|
----------------------
|
USER_CLK => USER_CLK,
|
USER_CLK => USER_CLK,
|
USER_RST => USER_RST
|
USER_RST => USER_RST
|
);
|
);
|
|
|
END TRANS;
|
END TRANS;
|
|
|