//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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//
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// This file contains confidential and proprietary information
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// international copyright and other intellectual property
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_gtp_pipe_drp.v
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// File : cl_a7pcie_x4_gtp_pipe_drp.v
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// Version : 1.10
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// Version : 1.11
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Filename : gtp_pipe_drp.v
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// Filename : gtp_pipe_drp.v
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// Description : GTP PIPE DRP Module for 7 Series Transceiver
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// Description : GTP PIPE DRP Module for 7 Series Transceiver
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// Version : 19.0
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// Version : 19.0
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//---------- GTP PIPE DRP Module -----------------------------------------------
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//---------- GTP PIPE DRP Module -----------------------------------------------
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module cl_a7pcie_x4_gtp_pipe_drp #
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module cl_a7pcie_x4_gtp_pipe_drp #
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(
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(
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parameter LOAD_CNT_MAX = 2'd1, // Load max count
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parameter LOAD_CNT_MAX = 2'd1, // Load max count
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parameter INDEX_MAX = 1'd0 // Index max count
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parameter INDEX_MAX = 1'd0 // Index max count
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)
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)
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(
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(
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//---------- Input -------------------------------------
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//---------- Input -------------------------------------
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input DRP_CLK,
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input DRP_CLK,
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input DRP_RST_N,
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input DRP_RST_N,
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input DRP_X16,
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input DRP_X16,
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input DRP_START,
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input DRP_START,
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input [15:0] DRP_DO,
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input [15:0] DRP_DO,
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input DRP_RDY,
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input DRP_RDY,
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//---------- Output ------------------------------------
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//---------- Output ------------------------------------
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output [ 8:0] DRP_ADDR,
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output [ 8:0] DRP_ADDR,
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output DRP_EN,
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output DRP_EN,
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output [15:0] DRP_DI,
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output [15:0] DRP_DI,
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output DRP_WE,
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output DRP_WE,
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output DRP_DONE,
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output DRP_DONE,
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output [ 2:0] DRP_FSM
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output [ 2:0] DRP_FSM
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);
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);
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//---------- Input Registers ---------------------------
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//---------- Input Registers ---------------------------
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
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//---------- Internal Signals --------------------------
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//---------- Internal Signals --------------------------
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reg [ 1:0] load_cnt = 2'd0;
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reg [ 1:0] load_cnt = 2'd0;
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reg [ 4:0] index = 5'd0;
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reg [ 4:0] index = 5'd0;
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reg [ 8:0] addr_reg = 9'd0;
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reg [ 8:0] addr_reg = 9'd0;
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reg [15:0] di_reg = 16'd0;
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reg [15:0] di_reg = 16'd0;
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//---------- Output Registers --------------------------
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//---------- Output Registers --------------------------
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reg done = 1'd0;
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reg done = 1'd0;
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reg [ 2:0] fsm = 0;
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reg [ 2:0] fsm = 0;
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//---------- DRP Address -------------------------------
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//---------- DRP Address -------------------------------
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localparam ADDR_RX_DATAWIDTH = 9'h011;
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localparam ADDR_RX_DATAWIDTH = 9'h011;
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//---------- DRP Mask ----------------------------------
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//---------- DRP Mask ----------------------------------
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localparam MASK_RX_DATAWIDTH = 16'b1111011111111111; // Unmask bit [ 11]
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localparam MASK_RX_DATAWIDTH = 16'b1111011111111111; // Unmask bit [ 11]
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//---------- DRP Data for x16 --------------------------
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//---------- DRP Data for x16 --------------------------
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localparam X16_RX_DATAWIDTH = 16'b0000000000000000; // 2-byte (16-bit) internal data width
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localparam X16_RX_DATAWIDTH = 16'b0000000000000000; // 2-byte (16-bit) internal data width
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//---------- DRP Data for x20 --------------------------
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//---------- DRP Data for x20 --------------------------
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localparam X20_RX_DATAWIDTH = 16'b0000100000000000; // 2-byte (20-bit) internal data width
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localparam X20_RX_DATAWIDTH = 16'b0000100000000000; // 2-byte (20-bit) internal data width
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//---------- DRP Data ----------------------------------
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//---------- DRP Data ----------------------------------
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wire [15:0] data_rx_datawidth;
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wire [15:0] data_rx_datawidth;
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//---------- FSM ---------------------------------------
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//---------- FSM ---------------------------------------
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localparam FSM_IDLE = 0;
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localparam FSM_IDLE = 0;
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localparam FSM_LOAD = 1;
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localparam FSM_LOAD = 1;
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localparam FSM_READ = 2;
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localparam FSM_READ = 2;
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localparam FSM_RRDY = 3;
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localparam FSM_RRDY = 3;
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localparam FSM_WRITE = 4;
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localparam FSM_WRITE = 4;
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localparam FSM_WRDY = 5;
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localparam FSM_WRDY = 5;
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localparam FSM_DONE = 6;
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localparam FSM_DONE = 6;
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//---------- Input FF ----------------------------------------------------------
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//---------- Input FF ----------------------------------------------------------
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always @ (posedge DRP_CLK)
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always @ (posedge DRP_CLK)
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begin
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begin
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if (!DRP_RST_N)
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if (!DRP_RST_N)
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begin
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begin
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//---------- 1st Stage FF --------------------------
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//---------- 1st Stage FF --------------------------
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x16_reg1 <= 1'd0;
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x16_reg1 <= 1'd0;
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do_reg1 <= 16'd0;
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do_reg1 <= 16'd0;
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rdy_reg1 <= 1'd0;
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rdy_reg1 <= 1'd0;
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start_reg1 <= 1'd0;
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start_reg1 <= 1'd0;
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//---------- 2nd Stage FF --------------------------
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//---------- 2nd Stage FF --------------------------
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x16_reg2 <= 1'd0;
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x16_reg2 <= 1'd0;
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do_reg2 <= 16'd0;
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do_reg2 <= 16'd0;
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rdy_reg2 <= 1'd0;
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rdy_reg2 <= 1'd0;
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start_reg2 <= 1'd0;
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start_reg2 <= 1'd0;
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end
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end
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else
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else
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begin
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begin
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//---------- 1st Stage FF --------------------------
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//---------- 1st Stage FF --------------------------
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x16_reg1 <= DRP_X16;
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x16_reg1 <= DRP_X16;
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do_reg1 <= DRP_DO;
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do_reg1 <= DRP_DO;
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rdy_reg1 <= DRP_RDY;
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rdy_reg1 <= DRP_RDY;
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start_reg1 <= DRP_START;
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start_reg1 <= DRP_START;
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//---------- 2nd Stage FF --------------------------
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//---------- 2nd Stage FF --------------------------
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x16_reg2 <= x16_reg1;
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x16_reg2 <= x16_reg1;
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do_reg2 <= do_reg1;
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do_reg2 <= do_reg1;
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rdy_reg2 <= rdy_reg1;
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rdy_reg2 <= rdy_reg1;
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start_reg2 <= start_reg1;
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start_reg2 <= start_reg1;
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end
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end
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end
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end
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//---------- Select DRP Data ---------------------------------------------------
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//---------- Select DRP Data ---------------------------------------------------
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assign data_rx_datawidth = x16_reg2 ? X16_RX_DATAWIDTH : X20_RX_DATAWIDTH;
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assign data_rx_datawidth = x16_reg2 ? X16_RX_DATAWIDTH : X20_RX_DATAWIDTH;
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//---------- Load Counter ------------------------------------------------------
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//---------- Load Counter ------------------------------------------------------
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always @ (posedge DRP_CLK)
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always @ (posedge DRP_CLK)
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begin
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begin
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if (!DRP_RST_N)
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if (!DRP_RST_N)
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load_cnt <= 2'd0;
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load_cnt <= 2'd0;
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else
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else
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//---------- Increment Load Counter ----------------
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//---------- Increment Load Counter ----------------
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if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
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if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
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load_cnt <= load_cnt + 2'd1;
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load_cnt <= load_cnt + 2'd1;
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//---------- Hold Load Counter ---------------------
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//---------- Hold Load Counter ---------------------
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else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
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else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
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load_cnt <= load_cnt;
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load_cnt <= load_cnt;
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//---------- Reset Load Counter --------------------
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//---------- Reset Load Counter --------------------
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else
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else
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load_cnt <= 2'd0;
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load_cnt <= 2'd0;
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end
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end
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//---------- Update DRP Address and Data ---------------------------------------
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//---------- Update DRP Address and Data ---------------------------------------
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always @ (posedge DRP_CLK)
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always @ (posedge DRP_CLK)
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begin
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begin
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if (!DRP_RST_N)
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if (!DRP_RST_N)
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begin
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begin
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addr_reg <= 9'd0;
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addr_reg <= 9'd0;
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di_reg <= 16'd0;
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di_reg <= 16'd0;
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end
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end
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else
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else
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begin
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begin
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case (index)
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case (index)
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//--------------------------------------------------
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//--------------------------------------------------
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1'd0 :
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1'd0 :
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begin
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begin
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addr_reg <= ADDR_RX_DATAWIDTH;
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addr_reg <= ADDR_RX_DATAWIDTH;
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di_reg <= (do_reg2 & MASK_RX_DATAWIDTH) | data_rx_datawidth;
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di_reg <= (do_reg2 & MASK_RX_DATAWIDTH) | data_rx_datawidth;
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end
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end
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//--------------------------------------------------
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//--------------------------------------------------
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default :
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default :
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begin
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begin
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addr_reg <= 9'd0;
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addr_reg <= 9'd0;
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di_reg <= 16'd0;
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di_reg <= 16'd0;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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//---------- PIPE DRP FSM ------------------------------------------------------
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//---------- PIPE DRP FSM ------------------------------------------------------
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always @ (posedge DRP_CLK)
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always @ (posedge DRP_CLK)
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begin
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begin
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if (!DRP_RST_N)
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if (!DRP_RST_N)
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begin
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begin
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fsm <= FSM_IDLE;
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fsm <= FSM_IDLE;
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index <= 5'd0;
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index <= 5'd0;
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done <= 1'd0;
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done <= 1'd0;
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end
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end
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else
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else
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begin
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begin
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case (fsm)
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case (fsm)
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//---------- Idle State ----------------------------
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//---------- Idle State ----------------------------
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FSM_IDLE :
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FSM_IDLE :
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begin
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begin
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//---------- Reset or Rate Change --------------
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//---------- Reset or Rate Change --------------
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if (start_reg2)
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if (start_reg2)
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begin
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begin
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fsm <= FSM_LOAD;
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fsm <= FSM_LOAD;
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index <= 5'd0;
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index <= 5'd0;
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done <= 1'd0;
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done <= 1'd0;
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end
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end
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//---------- Idle ------------------------------
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//---------- Idle ------------------------------
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else
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else
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begin
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begin
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fsm <= FSM_IDLE;
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fsm <= FSM_IDLE;
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index <= 5'd0;
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index <= 5'd0;
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done <= 1'd1;
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done <= 1'd1;
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end
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end
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end
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end
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//---------- Load DRP Address ---------------------
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//---------- Load DRP Address ---------------------
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FSM_LOAD :
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FSM_LOAD :
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begin
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begin
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fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
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fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
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index <= index;
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index <= index;
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done <= 1'd0;
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done <= 1'd0;
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end
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end
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//---------- Read DRP ------------------------------
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//---------- Read DRP ------------------------------
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FSM_READ :
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FSM_READ :
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begin
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begin
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fsm <= FSM_RRDY;
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fsm <= FSM_RRDY;
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index <= index;
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index <= index;
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done <= 1'd0;
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done <= 1'd0;
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end
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end
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//---------- Read DRP Ready ------------------------
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//---------- Read DRP Ready ------------------------
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FSM_RRDY :
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FSM_RRDY :
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begin
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begin
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fsm <= rdy_reg2 ? FSM_WRITE : FSM_RRDY;
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fsm <= rdy_reg2 ? FSM_WRITE : FSM_RRDY;
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index <= index;
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index <= index;
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done <= 1'd0;
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done <= 1'd0;
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end
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end
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//---------- Write DRP -----------------------------
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//---------- Write DRP -----------------------------
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FSM_WRITE :
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FSM_WRITE :
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begin
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begin
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fsm <= FSM_WRDY;
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fsm <= FSM_WRDY;
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index <= index;
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index <= index;
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done <= 1'd0;
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done <= 1'd0;
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end
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end
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//---------- Write DRP Ready -----------------------
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//---------- Write DRP Ready -----------------------
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FSM_WRDY :
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FSM_WRDY :
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begin
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begin
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fsm <= rdy_reg2 ? FSM_DONE : FSM_WRDY;
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fsm <= rdy_reg2 ? FSM_DONE : FSM_WRDY;
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index <= index;
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index <= index;
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done <= 1'd0;
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done <= 1'd0;
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end
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end
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//---------- DRP Done ------------------------------
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//---------- DRP Done ------------------------------
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FSM_DONE :
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FSM_DONE :
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|
|
begin
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begin
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if (index == INDEX_MAX)
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if (index == INDEX_MAX)
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begin
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begin
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fsm <= FSM_IDLE;
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fsm <= FSM_IDLE;
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index <= 5'd0;
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index <= 5'd0;
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done <= 1'd0;
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done <= 1'd0;
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end
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end
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else
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else
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begin
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begin
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fsm <= FSM_LOAD;
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fsm <= FSM_LOAD;
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index <= index + 5'd1;
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index <= index + 5'd1;
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done <= 1'd0;
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done <= 1'd0;
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end
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end
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end
|
end
|
|
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//---------- Default State -------------------------
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//---------- Default State -------------------------
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default :
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default :
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|
|
begin
|
begin
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fsm <= FSM_IDLE;
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fsm <= FSM_IDLE;
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index <= 5'd0;
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index <= 5'd0;
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done <= 1'd0;
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done <= 1'd0;
|
end
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end
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endcase
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endcase
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|
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end
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end
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end
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end
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//---------- PIPE DRP Output ---------------------------------------------------
|
//---------- PIPE DRP Output ---------------------------------------------------
|
assign DRP_ADDR = addr_reg;
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assign DRP_ADDR = addr_reg;
|
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
|
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
|
assign DRP_DI = di_reg;
|
assign DRP_DI = di_reg;
|
assign DRP_WE = (fsm == FSM_WRITE);
|
assign DRP_WE = (fsm == FSM_WRITE);
|
assign DRP_DONE = done;
|
assign DRP_DONE = done;
|
assign DRP_FSM = fsm;
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assign DRP_FSM = fsm;
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endmodule
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endmodule
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