//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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//
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// This file contains confidential and proprietary information
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// international copyright and other intellectual property
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// laws.
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// laws.
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//
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//
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// DISCLAIMER
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// CRITICAL APPLICATIONS
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_gtp_pipe_rate.v
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// File : cl_a7pcie_x4_gtp_pipe_rate.v
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// Version : 1.10
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// Version : 1.11
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Filename : gtp_pipe_rate.v
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// Filename : gtp_pipe_rate.v
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// Description : PIPE Rate Module for 7 Series Transceiver
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// Description : PIPE Rate Module for 7 Series Transceiver
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// Version : 19.0
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// Version : 19.0
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//---------- PIPE Rate Module --------------------------------------------------
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//---------- PIPE Rate Module --------------------------------------------------
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module cl_a7pcie_x4_gtp_pipe_rate #
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module cl_a7pcie_x4_gtp_pipe_rate #
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(
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(
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parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim mode
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parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim mode
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parameter TXDATA_WAIT_MAX = 4'd15 // TXDATA wait max
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parameter TXDATA_WAIT_MAX = 4'd15 // TXDATA wait max
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|
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)
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)
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(
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(
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//---------- Input -------------------------------------
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//---------- Input -------------------------------------
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input RATE_CLK,
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input RATE_CLK,
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input RATE_RST_N,
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input RATE_RST_N,
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input [ 1:0] RATE_RATE_IN,
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input [ 1:0] RATE_RATE_IN,
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input RATE_DRP_DONE,
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input RATE_DRP_DONE,
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input RATE_RXPMARESETDONE,
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input RATE_RXPMARESETDONE,
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input RATE_TXRATEDONE,
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input RATE_TXRATEDONE,
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input RATE_RXRATEDONE,
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input RATE_RXRATEDONE,
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input RATE_TXSYNC_DONE,
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input RATE_TXSYNC_DONE,
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input RATE_PHYSTATUS,
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input RATE_PHYSTATUS,
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//---------- Output ------------------------------------
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//---------- Output ------------------------------------
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output RATE_PCLK_SEL,
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output RATE_PCLK_SEL,
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output RATE_DRP_START,
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output RATE_DRP_START,
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output RATE_DRP_X16,
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output RATE_DRP_X16,
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output [ 2:0] RATE_RATE_OUT,
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output [ 2:0] RATE_RATE_OUT,
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output RATE_TXSYNC_START,
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output RATE_TXSYNC_START,
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output RATE_DONE,
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output RATE_DONE,
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output RATE_IDLE,
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output RATE_IDLE,
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output [ 4:0] RATE_FSM
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output [ 4:0] RATE_FSM
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|
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);
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);
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//---------- Input FF or Buffer ------------------------
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//---------- Input FF or Buffer ------------------------
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg2;
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//---------- Internal Signals --------------------------
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//---------- Internal Signals --------------------------
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wire [ 2:0] rate;
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wire [ 2:0] rate;
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reg [ 3:0] txdata_wait_cnt = 4'd0;
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reg [ 3:0] txdata_wait_cnt = 4'd0;
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reg txratedone = 1'd0;
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reg txratedone = 1'd0;
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reg rxratedone = 1'd0;
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reg rxratedone = 1'd0;
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reg phystatus = 1'd0;
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reg phystatus = 1'd0;
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reg ratedone = 1'd0;
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reg ratedone = 1'd0;
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//---------- Output FF or Buffer -----------------------
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//---------- Output FF or Buffer -----------------------
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reg pclk_sel = 1'd0;
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reg pclk_sel = 1'd0;
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reg [ 2:0] rate_out = 3'd0;
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reg [ 2:0] rate_out = 3'd0;
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reg [ 3:0] fsm = 0;
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reg [ 3:0] fsm = 0;
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//---------- FSM ---------------------------------------
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//---------- FSM ---------------------------------------
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localparam FSM_IDLE = 0;
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localparam FSM_IDLE = 0;
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localparam FSM_TXDATA_WAIT = 1;
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localparam FSM_TXDATA_WAIT = 1;
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localparam FSM_PCLK_SEL = 2;
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localparam FSM_PCLK_SEL = 2;
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localparam FSM_DRP_X16_START = 3;
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localparam FSM_DRP_X16_START = 3;
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localparam FSM_DRP_X16_DONE = 4;
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localparam FSM_DRP_X16_DONE = 4;
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localparam FSM_RATE_SEL = 5;
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localparam FSM_RATE_SEL = 5;
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localparam FSM_RXPMARESETDONE = 6;
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localparam FSM_RXPMARESETDONE = 6;
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localparam FSM_DRP_X20_START = 7;
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localparam FSM_DRP_X20_START = 7;
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localparam FSM_DRP_X20_DONE = 8;
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localparam FSM_DRP_X20_DONE = 8;
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localparam FSM_RATE_DONE = 9;
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localparam FSM_RATE_DONE = 9;
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localparam FSM_TXSYNC_START = 10;
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localparam FSM_TXSYNC_START = 10;
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localparam FSM_TXSYNC_DONE = 11;
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localparam FSM_TXSYNC_DONE = 11;
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localparam FSM_DONE = 12; // Must sync value to pipe_user.v
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localparam FSM_DONE = 12; // Must sync value to pipe_user.v
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//---------- Input FF ----------------------------------------------------------
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//---------- Input FF ----------------------------------------------------------
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always @ (posedge RATE_CLK)
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always @ (posedge RATE_CLK)
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begin
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begin
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if (!RATE_RST_N)
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if (!RATE_RST_N)
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begin
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begin
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//---------- 1st Stage FF --------------------------
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//---------- 1st Stage FF --------------------------
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rate_in_reg1 <= 2'd0;
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rate_in_reg1 <= 2'd0;
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drp_done_reg1 <= 1'd0;
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drp_done_reg1 <= 1'd0;
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rxpmaresetdone_reg1 <= 1'd0;
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rxpmaresetdone_reg1 <= 1'd0;
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txratedone_reg1 <= 1'd0;
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txratedone_reg1 <= 1'd0;
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rxratedone_reg1 <= 1'd0;
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rxratedone_reg1 <= 1'd0;
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phystatus_reg1 <= 1'd0;
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phystatus_reg1 <= 1'd0;
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txsync_done_reg1 <= 1'd0;
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txsync_done_reg1 <= 1'd0;
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//---------- 2nd Stage FF --------------------------
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//---------- 2nd Stage FF --------------------------
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rate_in_reg2 <= 2'd0;
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rate_in_reg2 <= 2'd0;
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drp_done_reg2 <= 1'd0;
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drp_done_reg2 <= 1'd0;
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rxpmaresetdone_reg2 <= 1'd0;
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rxpmaresetdone_reg2 <= 1'd0;
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txratedone_reg2 <= 1'd0;
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txratedone_reg2 <= 1'd0;
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rxratedone_reg2 <= 1'd0;
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rxratedone_reg2 <= 1'd0;
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phystatus_reg2 <= 1'd0;
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phystatus_reg2 <= 1'd0;
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txsync_done_reg2 <= 1'd0;
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txsync_done_reg2 <= 1'd0;
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end
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end
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else
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else
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begin
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begin
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//---------- 1st Stage FF --------------------------
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//---------- 1st Stage FF --------------------------
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rate_in_reg1 <= RATE_RATE_IN;
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rate_in_reg1 <= RATE_RATE_IN;
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drp_done_reg1 <= RATE_DRP_DONE;
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drp_done_reg1 <= RATE_DRP_DONE;
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rxpmaresetdone_reg1 <= RATE_RXPMARESETDONE;
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rxpmaresetdone_reg1 <= RATE_RXPMARESETDONE;
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txratedone_reg1 <= RATE_TXRATEDONE;
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txratedone_reg1 <= RATE_TXRATEDONE;
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rxratedone_reg1 <= RATE_RXRATEDONE;
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rxratedone_reg1 <= RATE_RXRATEDONE;
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phystatus_reg1 <= RATE_PHYSTATUS;
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phystatus_reg1 <= RATE_PHYSTATUS;
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txsync_done_reg1 <= RATE_TXSYNC_DONE;
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txsync_done_reg1 <= RATE_TXSYNC_DONE;
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//---------- 2nd Stage FF --------------------------
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//---------- 2nd Stage FF --------------------------
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rate_in_reg2 <= rate_in_reg1;
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rate_in_reg2 <= rate_in_reg1;
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drp_done_reg2 <= drp_done_reg1;
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drp_done_reg2 <= drp_done_reg1;
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rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
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rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
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txratedone_reg2 <= txratedone_reg1;
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txratedone_reg2 <= txratedone_reg1;
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rxratedone_reg2 <= rxratedone_reg1;
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rxratedone_reg2 <= rxratedone_reg1;
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phystatus_reg2 <= phystatus_reg1;
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phystatus_reg2 <= phystatus_reg1;
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txsync_done_reg2 <= txsync_done_reg1;
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txsync_done_reg2 <= txsync_done_reg1;
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end
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end
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end
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end
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//---------- Select Rate -------------------------------------------------------
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//---------- Select Rate -------------------------------------------------------
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// Gen1 : div 2 using [TX/RX]OUT_DIV = 2
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// Gen1 : div 2 using [TX/RX]OUT_DIV = 2
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// Gen2 : div 1 using [TX/RX]RATE = 3'd1
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// Gen2 : div 1 using [TX/RX]RATE = 3'd1
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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assign rate = (rate_in_reg2 == 2'd1) ? 3'd1 : 3'd0;
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assign rate = (rate_in_reg2 == 2'd1) ? 3'd1 : 3'd0;
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//---------- TXDATA Wait Counter -----------------------------------------------
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//---------- TXDATA Wait Counter -----------------------------------------------
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always @ (posedge RATE_CLK)
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always @ (posedge RATE_CLK)
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begin
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begin
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if (!RATE_RST_N)
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if (!RATE_RST_N)
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txdata_wait_cnt <= 4'd0;
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txdata_wait_cnt <= 4'd0;
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else
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else
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//---------- Increment Wait Counter ----------------
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//---------- Increment Wait Counter ----------------
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if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX))
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if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX))
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txdata_wait_cnt <= txdata_wait_cnt + 4'd1;
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txdata_wait_cnt <= txdata_wait_cnt + 4'd1;
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//---------- Hold Wait Counter ---------------------
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//---------- Hold Wait Counter ---------------------
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else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX))
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else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX))
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txdata_wait_cnt <= txdata_wait_cnt;
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txdata_wait_cnt <= txdata_wait_cnt;
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//---------- Reset Wait Counter --------------------
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//---------- Reset Wait Counter --------------------
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else
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else
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txdata_wait_cnt <= 4'd0;
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txdata_wait_cnt <= 4'd0;
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|
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end
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end
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//---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS -----------------------
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//---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS -----------------------
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always @ (posedge RATE_CLK)
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always @ (posedge RATE_CLK)
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begin
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begin
|
|
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if (!RATE_RST_N)
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if (!RATE_RST_N)
|
begin
|
begin
|
txratedone <= 1'd0;
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txratedone <= 1'd0;
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rxratedone <= 1'd0;
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rxratedone <= 1'd0;
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phystatus <= 1'd0;
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phystatus <= 1'd0;
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ratedone <= 1'd0;
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ratedone <= 1'd0;
|
end
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end
|
else
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else
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begin
|
begin
|
|
|
if ((fsm == FSM_RATE_DONE) || (fsm == FSM_RXPMARESETDONE) || (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE))
|
if ((fsm == FSM_RATE_DONE) || (fsm == FSM_RXPMARESETDONE) || (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE))
|
|
|
begin
|
begin
|
|
|
//---------- Latch TXRATEDONE ------------------
|
//---------- Latch TXRATEDONE ------------------
|
if (txratedone_reg2)
|
if (txratedone_reg2)
|
txratedone <= 1'd1;
|
txratedone <= 1'd1;
|
else
|
else
|
txratedone <= txratedone;
|
txratedone <= txratedone;
|
|
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//---------- Latch RXRATEDONE ------------------
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//---------- Latch RXRATEDONE ------------------
|
if (rxratedone_reg2)
|
if (rxratedone_reg2)
|
rxratedone <= 1'd1;
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rxratedone <= 1'd1;
|
else
|
else
|
rxratedone <= rxratedone;
|
rxratedone <= rxratedone;
|
|
|
//---------- Latch PHYSTATUS -------------------
|
//---------- Latch PHYSTATUS -------------------
|
if (phystatus_reg2)
|
if (phystatus_reg2)
|
phystatus <= 1'd1;
|
phystatus <= 1'd1;
|
else
|
else
|
phystatus <= phystatus;
|
phystatus <= phystatus;
|
|
|
//---------- Latch Rate Done -------------------
|
//---------- Latch Rate Done -------------------
|
if (rxratedone && txratedone && phystatus)
|
if (rxratedone && txratedone && phystatus)
|
ratedone <= 1'd1;
|
ratedone <= 1'd1;
|
else
|
else
|
ratedone <= ratedone;
|
ratedone <= ratedone;
|
|
|
end
|
end
|
|
|
else
|
else
|
|
|
begin
|
begin
|
txratedone <= 1'd0;
|
txratedone <= 1'd0;
|
rxratedone <= 1'd0;
|
rxratedone <= 1'd0;
|
phystatus <= 1'd0;
|
phystatus <= 1'd0;
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ratedone <= 1'd0;
|
ratedone <= 1'd0;
|
end
|
end
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- PIPE Rate FSM -----------------------------------------------------
|
//---------- PIPE Rate FSM -----------------------------------------------------
|
always @ (posedge RATE_CLK)
|
always @ (posedge RATE_CLK)
|
begin
|
begin
|
|
|
if (!RATE_RST_N)
|
if (!RATE_RST_N)
|
begin
|
begin
|
fsm <= FSM_IDLE;
|
fsm <= FSM_IDLE;
|
pclk_sel <= 1'd0;
|
pclk_sel <= 1'd0;
|
rate_out <= 3'd0;
|
rate_out <= 3'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
case (fsm)
|
case (fsm)
|
|
|
//---------- Idle State ----------------------------
|
//---------- Idle State ----------------------------
|
FSM_IDLE :
|
FSM_IDLE :
|
|
|
begin
|
begin
|
//---------- Detect Rate Change ----------------
|
//---------- Detect Rate Change ----------------
|
if (rate_in_reg2 != rate_in_reg1)
|
if (rate_in_reg2 != rate_in_reg1)
|
begin
|
begin
|
fsm <= FSM_TXDATA_WAIT;
|
fsm <= FSM_TXDATA_WAIT;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
fsm <= FSM_IDLE;
|
fsm <= FSM_IDLE;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
end
|
end
|
end
|
end
|
|
|
//---------- Wait for TXDATA to TX[P/N] Latency ----
|
//---------- Wait for TXDATA to TX[P/N] Latency ----
|
FSM_TXDATA_WAIT :
|
FSM_TXDATA_WAIT :
|
|
|
begin
|
begin
|
fsm <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT;
|
fsm <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
end
|
end
|
|
|
//---------- Select PCLK Frequency -----------------
|
//---------- Select PCLK Frequency -----------------
|
// Gen1 : PCLK = 125 MHz
|
// Gen1 : PCLK = 125 MHz
|
// Gen2 : PCLK = 250 MHz
|
// Gen2 : PCLK = 250 MHz
|
//--------------------------------------------------
|
//--------------------------------------------------
|
FSM_PCLK_SEL :
|
FSM_PCLK_SEL :
|
|
|
begin
|
begin
|
fsm <= (PCIE_SIM_SPEEDUP == "TRUE") ? FSM_RATE_SEL : FSM_DRP_X16_START;
|
fsm <= (PCIE_SIM_SPEEDUP == "TRUE") ? FSM_RATE_SEL : FSM_DRP_X16_START;
|
pclk_sel <= (rate_in_reg2 == 2'd1);
|
pclk_sel <= (rate_in_reg2 == 2'd1);
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
end
|
end
|
|
|
//---------- Start DRP x16 -------------------------
|
//---------- Start DRP x16 -------------------------
|
FSM_DRP_X16_START :
|
FSM_DRP_X16_START :
|
|
|
begin
|
begin
|
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
|
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
end
|
end
|
|
|
//---------- Wait for DRP x16 Done -----------------
|
//---------- Wait for DRP x16 Done -----------------
|
FSM_DRP_X16_DONE :
|
FSM_DRP_X16_DONE :
|
|
|
begin
|
begin
|
fsm <= drp_done_reg2 ? FSM_RATE_SEL : FSM_DRP_X16_DONE;
|
fsm <= drp_done_reg2 ? FSM_RATE_SEL : FSM_DRP_X16_DONE;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
end
|
end
|
|
|
//---------- Select Rate ---------------------------
|
//---------- Select Rate ---------------------------
|
FSM_RATE_SEL :
|
FSM_RATE_SEL :
|
|
|
begin
|
begin
|
fsm <= (PCIE_SIM_SPEEDUP == "TRUE") ? FSM_RATE_DONE : FSM_RXPMARESETDONE;
|
fsm <= (PCIE_SIM_SPEEDUP == "TRUE") ? FSM_RATE_DONE : FSM_RXPMARESETDONE;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
rate_out <= rate; // Update [TX/RX]RATE
|
rate_out <= rate; // Update [TX/RX]RATE
|
end
|
end
|
|
|
//---------- Wait for RXPMARESETDONE De-assertion --
|
//---------- Wait for RXPMARESETDONE De-assertion --
|
FSM_RXPMARESETDONE :
|
FSM_RXPMARESETDONE :
|
|
|
begin
|
begin
|
fsm <= (!rxpmaresetdone_reg2) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE;
|
fsm <= (!rxpmaresetdone_reg2) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
end
|
end
|
|
|
//---------- Start DRP x20 -------------------------
|
//---------- Start DRP x20 -------------------------
|
FSM_DRP_X20_START :
|
FSM_DRP_X20_START :
|
|
|
begin
|
begin
|
fsm <= (!drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
|
fsm <= (!drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
end
|
end
|
|
|
//---------- Wait for DRP x20 Done -----------------
|
//---------- Wait for DRP x20 Done -----------------
|
FSM_DRP_X20_DONE :
|
FSM_DRP_X20_DONE :
|
|
|
begin
|
begin
|
fsm <= drp_done_reg2 ? FSM_RATE_DONE : FSM_DRP_X20_DONE;
|
fsm <= drp_done_reg2 ? FSM_RATE_DONE : FSM_DRP_X20_DONE;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
end
|
end
|
|
|
//---------- Wait for Rate Change Done -------------
|
//---------- Wait for Rate Change Done -------------
|
FSM_RATE_DONE :
|
FSM_RATE_DONE :
|
|
|
begin
|
begin
|
if (ratedone)
|
if (ratedone)
|
fsm <= FSM_TXSYNC_START;
|
fsm <= FSM_TXSYNC_START;
|
else
|
else
|
fsm <= FSM_RATE_DONE;
|
fsm <= FSM_RATE_DONE;
|
|
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
end
|
end
|
|
|
//---------- Start TX Sync -------------------------
|
//---------- Start TX Sync -------------------------
|
FSM_TXSYNC_START:
|
FSM_TXSYNC_START:
|
|
|
begin
|
begin
|
fsm <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
|
fsm <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
end
|
end
|
|
|
//---------- Wait for TX Sync Done -----------------
|
//---------- Wait for TX Sync Done -----------------
|
FSM_TXSYNC_DONE:
|
FSM_TXSYNC_DONE:
|
|
|
begin
|
begin
|
fsm <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE);
|
fsm <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE);
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
end
|
end
|
|
|
//---------- Rate Change Done ----------------------
|
//---------- Rate Change Done ----------------------
|
FSM_DONE :
|
FSM_DONE :
|
|
|
begin
|
begin
|
fsm <= FSM_IDLE;
|
fsm <= FSM_IDLE;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
end
|
end
|
|
|
//---------- Default State -------------------------
|
//---------- Default State -------------------------
|
default :
|
default :
|
|
|
begin
|
begin
|
fsm <= FSM_IDLE;
|
fsm <= FSM_IDLE;
|
pclk_sel <= 1'd0;
|
pclk_sel <= 1'd0;
|
rate_out <= 3'd0;
|
rate_out <= 3'd0;
|
end
|
end
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- PIPE Rate Output --------------------------------------------------
|
//---------- PIPE Rate Output --------------------------------------------------
|
assign RATE_PCLK_SEL = pclk_sel;
|
assign RATE_PCLK_SEL = pclk_sel;
|
assign RATE_DRP_START = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
|
assign RATE_DRP_START = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
|
assign RATE_DRP_X16 = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
|
assign RATE_DRP_X16 = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
|
assign RATE_RATE_OUT = rate_out;
|
assign RATE_RATE_OUT = rate_out;
|
assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START);
|
assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START);
|
assign RATE_DONE = (fsm == FSM_DONE);
|
assign RATE_DONE = (fsm == FSM_DONE);
|
assign RATE_IDLE = (fsm == FSM_IDLE);
|
assign RATE_IDLE = (fsm == FSM_IDLE);
|
assign RATE_FSM = {1'd0, fsm};
|
assign RATE_FSM = {1'd0, fsm};
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
