//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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//
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// This file contains confidential and proprietary information
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// international copyright and other intellectual property
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// laws.
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// laws.
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//
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//
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// DISCLAIMER
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// Xilinx, and to the maximum extent permitted by applicable
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// CRITICAL APPLICATIONS
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// CRITICAL APPLICATIONS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_gtp_pipe_reset.v
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// File : cl_a7pcie_x4_gtp_pipe_reset.v
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// Version : 1.10
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// Version : 1.11
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Filename : gtp_pipe_reset.v
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// Filename : gtp_pipe_reset.v
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// Description : GTP PIPE Reset Module for 7 Series Transceiver
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// Description : GTP PIPE Reset Module for 7 Series Transceiver
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// Version : 19.0
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// Version : 19.0
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//---------- PIPE Reset Module -------------------------------------------------
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//---------- PIPE Reset Module -------------------------------------------------
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module cl_a7pcie_x4_gtp_pipe_reset #
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module cl_a7pcie_x4_gtp_pipe_reset #
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(
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(
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//---------- Global ------------------------------------
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//---------- Global ------------------------------------
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parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
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parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
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parameter PCIE_LANE = 1, // PCIe number of lanes
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parameter PCIE_LANE = 1, // PCIe number of lanes
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//---------- Local -------------------------------------
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//---------- Local -------------------------------------
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parameter CFG_WAIT_MAX = 6'd63, // Configuration wait max
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parameter CFG_WAIT_MAX = 6'd63, // Configuration wait max
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parameter BYPASS_RXCDRLOCK = 1 // Bypass RXCDRLOCK
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parameter BYPASS_RXCDRLOCK = 1 // Bypass RXCDRLOCK
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)
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)
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(
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(
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//---------- Input -------------------------------------
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//---------- Input -------------------------------------
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input RST_CLK,
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input RST_CLK,
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input RST_RXUSRCLK,
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input RST_RXUSRCLK,
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input RST_DCLK,
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input RST_DCLK,
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input RST_RST_N,
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input RST_RST_N,
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input [PCIE_LANE-1:0] RST_DRP_DONE,
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input [PCIE_LANE-1:0] RST_DRP_DONE,
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input [PCIE_LANE-1:0] RST_RXPMARESETDONE,
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input [PCIE_LANE-1:0] RST_RXPMARESETDONE,
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input RST_PLLLOCK,
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input RST_PLLLOCK,
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input [PCIE_LANE-1:0] RST_RATE_IDLE,
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input [PCIE_LANE-1:0] RST_RATE_IDLE,
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input [PCIE_LANE-1:0] RST_RXCDRLOCK,
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input [PCIE_LANE-1:0] RST_RXCDRLOCK,
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input RST_MMCM_LOCK,
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input RST_MMCM_LOCK,
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input [PCIE_LANE-1:0] RST_RESETDONE,
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input [PCIE_LANE-1:0] RST_RESETDONE,
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input [PCIE_LANE-1:0] RST_PHYSTATUS,
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input [PCIE_LANE-1:0] RST_PHYSTATUS,
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input [PCIE_LANE-1:0] RST_TXSYNC_DONE,
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input [PCIE_LANE-1:0] RST_TXSYNC_DONE,
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//---------- Output ------------------------------------
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//---------- Output ------------------------------------
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output RST_CPLLRESET,
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output RST_CPLLRESET,
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output RST_CPLLPD,
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output RST_CPLLPD,
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output reg RST_DRP_START,
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output reg RST_DRP_START,
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output reg RST_DRP_X16,
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output reg RST_DRP_X16,
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output RST_RXUSRCLK_RESET,
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output RST_RXUSRCLK_RESET,
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output RST_DCLK_RESET,
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output RST_DCLK_RESET,
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output RST_GTRESET,
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output RST_GTRESET,
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output RST_USERRDY,
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output RST_USERRDY,
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output RST_TXSYNC_START,
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output RST_TXSYNC_START,
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output RST_IDLE,
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output RST_IDLE,
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output [ 4:0] RST_FSM
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output [ 4:0] RST_FSM
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);
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);
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//---------- Input Register ----------------------------
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//---------- Input Register ----------------------------
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg plllock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg plllock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg plllock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg plllock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg2;
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//---------- Internal Signal ---------------------------
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//---------- Internal Signal ---------------------------
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reg [ 5:0] cfg_wait_cnt = 6'd0;
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reg [ 5:0] cfg_wait_cnt = 6'd0;
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//---------- Output Register ---------------------------
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//---------- Output Register ---------------------------
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reg pllreset = 1'd0;
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reg pllreset = 1'd0;
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reg pllpd = 1'd0;
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reg pllpd = 1'd0;
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reg rxusrclk_rst_reg1 = 1'd0;
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reg rxusrclk_rst_reg1 = 1'd0;
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reg rxusrclk_rst_reg2 = 1'd0;
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reg rxusrclk_rst_reg2 = 1'd0;
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reg dclk_rst_reg1 = 1'd0;
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reg dclk_rst_reg1 = 1'd0;
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reg dclk_rst_reg2 = 1'd0;
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reg dclk_rst_reg2 = 1'd0;
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reg gtreset = 1'd0;
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reg gtreset = 1'd0;
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reg userrdy = 1'd0;
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reg userrdy = 1'd0;
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reg [ 4:0] fsm = 5'h1;
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reg [ 4:0] fsm = 5'h1;
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//---------- FSM ---------------------------------------
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//---------- FSM ---------------------------------------
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localparam FSM_IDLE = 5'h0;
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localparam FSM_IDLE = 5'h0;
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localparam FSM_CFG_WAIT = 5'h1;
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localparam FSM_CFG_WAIT = 5'h1;
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localparam FSM_PLLRESET = 5'h2;
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localparam FSM_PLLRESET = 5'h2;
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localparam FSM_DRP_X16_START = 5'h3;
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localparam FSM_DRP_X16_START = 5'h3;
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localparam FSM_DRP_X16_DONE = 5'h4;
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localparam FSM_DRP_X16_DONE = 5'h4;
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localparam FSM_PLLLOCK = 5'h5;
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localparam FSM_PLLLOCK = 5'h5;
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localparam FSM_GTRESET = 5'h6;
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localparam FSM_GTRESET = 5'h6;
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localparam FSM_RXPMARESETDONE_1 = 5'h7;
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localparam FSM_RXPMARESETDONE_1 = 5'h7;
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localparam FSM_RXPMARESETDONE_2 = 5'h8;
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localparam FSM_RXPMARESETDONE_2 = 5'h8;
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localparam FSM_DRP_X20_START = 5'h9;
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localparam FSM_DRP_X20_START = 5'h9;
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localparam FSM_DRP_X20_DONE = 5'hA;
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localparam FSM_DRP_X20_DONE = 5'hA;
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localparam FSM_MMCM_LOCK = 5'hB;
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localparam FSM_MMCM_LOCK = 5'hB;
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localparam FSM_RESETDONE = 5'hC;
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localparam FSM_RESETDONE = 5'hC;
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localparam FSM_TXSYNC_START = 5'hD;
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localparam FSM_TXSYNC_START = 5'hD;
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localparam FSM_TXSYNC_DONE = 5'hE;
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localparam FSM_TXSYNC_DONE = 5'hE;
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//---------- Input FF ----------------------------------------------------------
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//---------- Input FF ----------------------------------------------------------
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always @ (posedge RST_CLK)
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always @ (posedge RST_CLK)
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begin
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begin
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if (!RST_RST_N)
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if (!RST_RST_N)
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begin
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begin
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//---------- 1st Stage FF --------------------------
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//---------- 1st Stage FF --------------------------
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drp_done_reg1 <= {PCIE_LANE{1'd0}};
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drp_done_reg1 <= {PCIE_LANE{1'd0}};
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rxpmaresetdone_reg1 <= {PCIE_LANE{1'd0}};
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rxpmaresetdone_reg1 <= {PCIE_LANE{1'd0}};
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plllock_reg1 <= 1'd0;
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plllock_reg1 <= 1'd0;
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rate_idle_reg1 <= {PCIE_LANE{1'd0}};
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rate_idle_reg1 <= {PCIE_LANE{1'd0}};
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rxcdrlock_reg1 <= {PCIE_LANE{1'd0}};
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rxcdrlock_reg1 <= {PCIE_LANE{1'd0}};
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mmcm_lock_reg1 <= 1'd0;
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mmcm_lock_reg1 <= 1'd0;
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resetdone_reg1 <= {PCIE_LANE{1'd0}};
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resetdone_reg1 <= {PCIE_LANE{1'd0}};
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phystatus_reg1 <= {PCIE_LANE{1'd0}};
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phystatus_reg1 <= {PCIE_LANE{1'd0}};
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txsync_done_reg1 <= {PCIE_LANE{1'd0}};
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txsync_done_reg1 <= {PCIE_LANE{1'd0}};
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//---------- 2nd Stage FF --------------------------
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//---------- 2nd Stage FF --------------------------
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drp_done_reg2 <= {PCIE_LANE{1'd0}};
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drp_done_reg2 <= {PCIE_LANE{1'd0}};
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rxpmaresetdone_reg2 <= {PCIE_LANE{1'd0}};
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rxpmaresetdone_reg2 <= {PCIE_LANE{1'd0}};
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plllock_reg2 <= 1'd0;
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plllock_reg2 <= 1'd0;
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rate_idle_reg2 <= {PCIE_LANE{1'd0}};
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rate_idle_reg2 <= {PCIE_LANE{1'd0}};
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rxcdrlock_reg2 <= {PCIE_LANE{1'd0}};
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rxcdrlock_reg2 <= {PCIE_LANE{1'd0}};
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mmcm_lock_reg2 <= 1'd0;
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mmcm_lock_reg2 <= 1'd0;
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resetdone_reg2 <= {PCIE_LANE{1'd0}};
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resetdone_reg2 <= {PCIE_LANE{1'd0}};
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phystatus_reg2 <= {PCIE_LANE{1'd0}};
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phystatus_reg2 <= {PCIE_LANE{1'd0}};
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txsync_done_reg2 <= {PCIE_LANE{1'd0}};
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txsync_done_reg2 <= {PCIE_LANE{1'd0}};
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end
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end
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else
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else
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begin
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begin
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//---------- 1st Stage FF --------------------------
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//---------- 1st Stage FF --------------------------
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drp_done_reg1 <= RST_DRP_DONE;
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drp_done_reg1 <= RST_DRP_DONE;
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rxpmaresetdone_reg1 <= RST_RXPMARESETDONE;
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rxpmaresetdone_reg1 <= RST_RXPMARESETDONE;
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plllock_reg1 <= RST_PLLLOCK;
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plllock_reg1 <= RST_PLLLOCK;
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rate_idle_reg1 <= RST_RATE_IDLE;
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rate_idle_reg1 <= RST_RATE_IDLE;
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rxcdrlock_reg1 <= RST_RXCDRLOCK;
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rxcdrlock_reg1 <= RST_RXCDRLOCK;
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mmcm_lock_reg1 <= RST_MMCM_LOCK;
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mmcm_lock_reg1 <= RST_MMCM_LOCK;
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resetdone_reg1 <= RST_RESETDONE;
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resetdone_reg1 <= RST_RESETDONE;
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phystatus_reg1 <= RST_PHYSTATUS;
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phystatus_reg1 <= RST_PHYSTATUS;
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txsync_done_reg1 <= RST_TXSYNC_DONE;
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txsync_done_reg1 <= RST_TXSYNC_DONE;
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//---------- 2nd Stage FF --------------------------
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//---------- 2nd Stage FF --------------------------
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drp_done_reg2 <= drp_done_reg1;
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drp_done_reg2 <= drp_done_reg1;
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rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
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rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
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plllock_reg2 <= plllock_reg1;
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plllock_reg2 <= plllock_reg1;
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rate_idle_reg2 <= rate_idle_reg1;
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rate_idle_reg2 <= rate_idle_reg1;
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rxcdrlock_reg2 <= rxcdrlock_reg1;
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rxcdrlock_reg2 <= rxcdrlock_reg1;
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mmcm_lock_reg2 <= mmcm_lock_reg1;
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mmcm_lock_reg2 <= mmcm_lock_reg1;
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resetdone_reg2 <= resetdone_reg1;
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resetdone_reg2 <= resetdone_reg1;
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phystatus_reg2 <= phystatus_reg1;
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phystatus_reg2 <= phystatus_reg1;
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txsync_done_reg2 <= txsync_done_reg1;
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txsync_done_reg2 <= txsync_done_reg1;
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end
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end
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end
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end
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//---------- Configuration Reset Wait Counter ----------------------------------
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//---------- Configuration Reset Wait Counter ----------------------------------
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always @ (posedge RST_CLK)
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always @ (posedge RST_CLK)
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begin
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begin
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|
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if (!RST_RST_N)
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if (!RST_RST_N)
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cfg_wait_cnt <= 6'd0;
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cfg_wait_cnt <= 6'd0;
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else
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else
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//---------- Increment Configuration Reset Wait Counter
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//---------- Increment Configuration Reset Wait Counter
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if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt < CFG_WAIT_MAX))
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if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt < CFG_WAIT_MAX))
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cfg_wait_cnt <= cfg_wait_cnt + 6'd1;
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cfg_wait_cnt <= cfg_wait_cnt + 6'd1;
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//---------- Hold Configuration Reset Wait Counter -
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//---------- Hold Configuration Reset Wait Counter -
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else if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt == CFG_WAIT_MAX))
|
else if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt == CFG_WAIT_MAX))
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cfg_wait_cnt <= cfg_wait_cnt;
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cfg_wait_cnt <= cfg_wait_cnt;
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|
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//---------- Reset Configuration Reset Wait Counter
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//---------- Reset Configuration Reset Wait Counter
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else
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else
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cfg_wait_cnt <= 6'd0;
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cfg_wait_cnt <= 6'd0;
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|
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end
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end
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|
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//---------- PIPE Reset FSM ----------------------------------------------------
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//---------- PIPE Reset FSM ----------------------------------------------------
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always @ (posedge RST_CLK)
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always @ (posedge RST_CLK)
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begin
|
begin
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|
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if (!RST_RST_N)
|
if (!RST_RST_N)
|
begin
|
begin
|
fsm <= FSM_CFG_WAIT;
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fsm <= FSM_CFG_WAIT;
|
pllreset <= 1'd0;
|
pllreset <= 1'd0;
|
pllpd <= 1'd0;
|
pllpd <= 1'd0;
|
gtreset <= 1'd0;
|
gtreset <= 1'd0;
|
userrdy <= 1'd0;
|
userrdy <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
case (fsm)
|
case (fsm)
|
|
|
//---------- Idle State ----------------------------
|
//---------- Idle State ----------------------------
|
FSM_IDLE :
|
FSM_IDLE :
|
|
|
begin
|
begin
|
if (!RST_RST_N)
|
if (!RST_RST_N)
|
begin
|
begin
|
fsm <= FSM_CFG_WAIT;
|
fsm <= FSM_CFG_WAIT;
|
pllreset <= 1'd0;
|
pllreset <= 1'd0;
|
pllpd <= 1'd0;
|
pllpd <= 1'd0;
|
gtreset <= 1'd0;
|
gtreset <= 1'd0;
|
userrdy <= 1'd0;
|
userrdy <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
fsm <= FSM_IDLE;
|
fsm <= FSM_IDLE;
|
pllreset <= pllreset;
|
pllreset <= pllreset;
|
pllpd <= pllpd;
|
pllpd <= pllpd;
|
gtreset <= gtreset;
|
gtreset <= gtreset;
|
userrdy <= userrdy;
|
userrdy <= userrdy;
|
end
|
end
|
end
|
end
|
|
|
//---------- Wait for Configuration Reset Delay ---
|
//---------- Wait for Configuration Reset Delay ---
|
FSM_CFG_WAIT :
|
FSM_CFG_WAIT :
|
|
|
begin
|
begin
|
fsm <= ((cfg_wait_cnt == CFG_WAIT_MAX) ? FSM_PLLRESET : FSM_CFG_WAIT);
|
fsm <= ((cfg_wait_cnt == CFG_WAIT_MAX) ? FSM_PLLRESET : FSM_CFG_WAIT);
|
pllreset <= pllreset;
|
pllreset <= pllreset;
|
pllpd <= pllpd;
|
pllpd <= pllpd;
|
gtreset <= gtreset;
|
gtreset <= gtreset;
|
userrdy <= userrdy;
|
userrdy <= userrdy;
|
end
|
end
|
|
|
//---------- Hold PLL and GTP Channel in Reset ----
|
//---------- Hold PLL and GTP Channel in Reset ----
|
FSM_PLLRESET :
|
FSM_PLLRESET :
|
|
|
begin
|
begin
|
fsm <= (((~plllock_reg2) && (&(~resetdone_reg2))) ? FSM_DRP_X16_START : FSM_PLLRESET);
|
fsm <= (((~plllock_reg2) && (&(~resetdone_reg2))) ? FSM_DRP_X16_START : FSM_PLLRESET);
|
pllreset <= 1'd1;
|
pllreset <= 1'd1;
|
pllpd <= pllpd;
|
pllpd <= pllpd;
|
gtreset <= 1'd1;
|
gtreset <= 1'd1;
|
userrdy <= userrdy;
|
userrdy <= userrdy;
|
end
|
end
|
|
|
//---------- Start DRP x16 -------------------------
|
//---------- Start DRP x16 -------------------------
|
FSM_DRP_X16_START :
|
FSM_DRP_X16_START :
|
|
|
begin
|
begin
|
fsm <= &(~drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
|
fsm <= &(~drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
|
pllreset <= pllreset;
|
pllreset <= pllreset;
|
pllpd <= pllpd;
|
pllpd <= pllpd;
|
gtreset <= gtreset;
|
gtreset <= gtreset;
|
userrdy <= userrdy;
|
userrdy <= userrdy;
|
end
|
end
|
|
|
//---------- Wait for DRP x16 Done -----------------
|
//---------- Wait for DRP x16 Done -----------------
|
FSM_DRP_X16_DONE :
|
FSM_DRP_X16_DONE :
|
|
|
begin
|
begin
|
fsm <= (&drp_done_reg2) ? FSM_PLLLOCK : FSM_DRP_X16_DONE;
|
fsm <= (&drp_done_reg2) ? FSM_PLLLOCK : FSM_DRP_X16_DONE;
|
pllreset <= pllreset;
|
pllreset <= pllreset;
|
pllpd <= pllpd;
|
pllpd <= pllpd;
|
gtreset <= gtreset;
|
gtreset <= gtreset;
|
userrdy <= userrdy;
|
userrdy <= userrdy;
|
end
|
end
|
|
|
//---------- Wait for PLL Lock --------------------
|
//---------- Wait for PLL Lock --------------------
|
FSM_PLLLOCK :
|
FSM_PLLLOCK :
|
|
|
begin
|
begin
|
fsm <= (plllock_reg2 ? FSM_GTRESET : FSM_PLLLOCK);
|
fsm <= (plllock_reg2 ? FSM_GTRESET : FSM_PLLLOCK);
|
pllreset <= 1'd0;
|
pllreset <= 1'd0;
|
pllpd <= pllpd;
|
pllpd <= pllpd;
|
gtreset <= gtreset;
|
gtreset <= gtreset;
|
userrdy <= userrdy;
|
userrdy <= userrdy;
|
end
|
end
|
|
|
//---------- Release GTRESET -----------------------
|
//---------- Release GTRESET -----------------------
|
FSM_GTRESET :
|
FSM_GTRESET :
|
|
|
begin
|
begin
|
fsm <= FSM_RXPMARESETDONE_1;
|
fsm <= FSM_RXPMARESETDONE_1;
|
pllreset <= pllreset;
|
pllreset <= pllreset;
|
pllpd <= pllpd;
|
pllpd <= pllpd;
|
gtreset <= 1'b0;
|
gtreset <= 1'b0;
|
userrdy <= userrdy;
|
userrdy <= userrdy;
|
end
|
end
|
|
|
//---------- Wait for RXPMARESETDONE Assertion -----
|
//---------- Wait for RXPMARESETDONE Assertion -----
|
FSM_RXPMARESETDONE_1 :
|
FSM_RXPMARESETDONE_1 :
|
|
|
begin
|
begin
|
fsm <= (&rxpmaresetdone_reg2 || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_RXPMARESETDONE_2 : FSM_RXPMARESETDONE_1;
|
fsm <= (&rxpmaresetdone_reg2 || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_RXPMARESETDONE_2 : FSM_RXPMARESETDONE_1;
|
pllreset <= pllreset;
|
pllreset <= pllreset;
|
pllpd <= pllpd;
|
pllpd <= pllpd;
|
gtreset <= gtreset;
|
gtreset <= gtreset;
|
userrdy <= userrdy;
|
userrdy <= userrdy;
|
end
|
end
|
|
|
//---------- Wait for RXPMARESETDONE De-assertion --
|
//---------- Wait for RXPMARESETDONE De-assertion --
|
FSM_RXPMARESETDONE_2 :
|
FSM_RXPMARESETDONE_2 :
|
|
|
begin
|
begin
|
fsm <= (&(~rxpmaresetdone_reg2) || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE_2;
|
fsm <= (&(~rxpmaresetdone_reg2) || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE_2;
|
pllreset <= pllreset;
|
pllreset <= pllreset;
|
pllpd <= pllpd;
|
pllpd <= pllpd;
|
gtreset <= gtreset;
|
gtreset <= gtreset;
|
userrdy <= userrdy;
|
userrdy <= userrdy;
|
end
|
end
|
|
|
//---------- Start DRP x20 -------------------------
|
//---------- Start DRP x20 -------------------------
|
FSM_DRP_X20_START :
|
FSM_DRP_X20_START :
|
|
|
begin
|
begin
|
fsm <= &(~drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
|
fsm <= &(~drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
|
pllreset <= pllreset;
|
pllreset <= pllreset;
|
pllpd <= pllpd;
|
pllpd <= pllpd;
|
gtreset <= gtreset;
|
gtreset <= gtreset;
|
userrdy <= userrdy;
|
userrdy <= userrdy;
|
end
|
end
|
|
|
//---------- Wait for DRP x20 Done -----------------
|
//---------- Wait for DRP x20 Done -----------------
|
FSM_DRP_X20_DONE :
|
FSM_DRP_X20_DONE :
|
|
|
begin
|
begin
|
fsm <= (&drp_done_reg2) ? FSM_MMCM_LOCK : FSM_DRP_X20_DONE;
|
fsm <= (&drp_done_reg2) ? FSM_MMCM_LOCK : FSM_DRP_X20_DONE;
|
pllreset <= pllreset;
|
pllreset <= pllreset;
|
pllpd <= pllpd;
|
pllpd <= pllpd;
|
gtreset <= gtreset;
|
gtreset <= gtreset;
|
userrdy <= userrdy;
|
userrdy <= userrdy;
|
end
|
end
|
|
|
//---------- Wait for MMCM and RX CDR Lock ---------
|
//---------- Wait for MMCM and RX CDR Lock ---------
|
FSM_MMCM_LOCK :
|
FSM_MMCM_LOCK :
|
|
|
begin
|
begin
|
if (mmcm_lock_reg2 && (&rxcdrlock_reg2 || (BYPASS_RXCDRLOCK == 1)))
|
if (mmcm_lock_reg2 && (&rxcdrlock_reg2 || (BYPASS_RXCDRLOCK == 1)))
|
begin
|
begin
|
fsm <= FSM_RESETDONE;
|
fsm <= FSM_RESETDONE;
|
pllreset <= pllreset;
|
pllreset <= pllreset;
|
pllpd <= pllpd;
|
pllpd <= pllpd;
|
gtreset <= gtreset;
|
gtreset <= gtreset;
|
userrdy <= 1'd1;
|
userrdy <= 1'd1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
fsm <= FSM_MMCM_LOCK;
|
fsm <= FSM_MMCM_LOCK;
|
pllreset <= pllreset;
|
pllreset <= pllreset;
|
pllpd <= pllpd;
|
pllpd <= pllpd;
|
gtreset <= gtreset;
|
gtreset <= gtreset;
|
userrdy <= 1'd0;
|
userrdy <= 1'd0;
|
end
|
end
|
end
|
end
|
|
|
//---------- Wait for [TX/RX]RESETDONE and PHYSTATUS
|
//---------- Wait for [TX/RX]RESETDONE and PHYSTATUS
|
FSM_RESETDONE :
|
FSM_RESETDONE :
|
|
|
begin
|
begin
|
fsm <= (&resetdone_reg2 && (&(~phystatus_reg2)) ? FSM_TXSYNC_START : FSM_RESETDONE);
|
fsm <= (&resetdone_reg2 && (&(~phystatus_reg2)) ? FSM_TXSYNC_START : FSM_RESETDONE);
|
pllreset <= pllreset;
|
pllreset <= pllreset;
|
pllpd <= pllpd;
|
pllpd <= pllpd;
|
gtreset <= gtreset;
|
gtreset <= gtreset;
|
userrdy <= userrdy;
|
userrdy <= userrdy;
|
end
|
end
|
|
|
//---------- Start TX Sync -------------------------
|
//---------- Start TX Sync -------------------------
|
FSM_TXSYNC_START :
|
FSM_TXSYNC_START :
|
|
|
begin
|
begin
|
fsm <= (&(~txsync_done_reg2) ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
|
fsm <= (&(~txsync_done_reg2) ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
|
pllreset <= pllreset;
|
pllreset <= pllreset;
|
pllpd <= pllpd;
|
pllpd <= pllpd;
|
gtreset <= gtreset;
|
gtreset <= gtreset;
|
userrdy <= userrdy;
|
userrdy <= userrdy;
|
end
|
end
|
|
|
//---------- Wait for TX Sync Done -----------------
|
//---------- Wait for TX Sync Done -----------------
|
FSM_TXSYNC_DONE :
|
FSM_TXSYNC_DONE :
|
|
|
begin
|
begin
|
fsm <= (&txsync_done_reg2 ? FSM_IDLE : FSM_TXSYNC_DONE);
|
fsm <= (&txsync_done_reg2 ? FSM_IDLE : FSM_TXSYNC_DONE);
|
pllreset <= pllreset;
|
pllreset <= pllreset;
|
pllpd <= pllpd;
|
pllpd <= pllpd;
|
gtreset <= gtreset;
|
gtreset <= gtreset;
|
userrdy <= userrdy;
|
userrdy <= userrdy;
|
end
|
end
|
|
|
//---------- Default State -------------------------
|
//---------- Default State -------------------------
|
default :
|
default :
|
|
|
begin
|
begin
|
fsm <= FSM_CFG_WAIT;
|
fsm <= FSM_CFG_WAIT;
|
pllreset <= 1'd0;
|
pllreset <= 1'd0;
|
pllpd <= 1'd0;
|
pllpd <= 1'd0;
|
gtreset <= 1'd0;
|
gtreset <= 1'd0;
|
userrdy <= 1'd0;
|
userrdy <= 1'd0;
|
end
|
end
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- RXUSRCLK Reset Synchronizer ---------------------------------------
|
//---------- RXUSRCLK Reset Synchronizer ---------------------------------------
|
always @ (posedge RST_RXUSRCLK)
|
always @ (posedge RST_RXUSRCLK)
|
begin
|
begin
|
|
|
if (pllreset)
|
if (pllreset)
|
begin
|
begin
|
rxusrclk_rst_reg1 <= 1'd1;
|
rxusrclk_rst_reg1 <= 1'd1;
|
rxusrclk_rst_reg2 <= 1'd1;
|
rxusrclk_rst_reg2 <= 1'd1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rxusrclk_rst_reg1 <= 1'd0;
|
rxusrclk_rst_reg1 <= 1'd0;
|
rxusrclk_rst_reg2 <= rxusrclk_rst_reg1;
|
rxusrclk_rst_reg2 <= rxusrclk_rst_reg1;
|
end
|
end
|
|
|
end
|
end
|
|
|
//---------- DCLK Reset Synchronizer -------------------------------------------
|
//---------- DCLK Reset Synchronizer -------------------------------------------
|
always @ (posedge RST_DCLK)
|
always @ (posedge RST_DCLK)
|
begin
|
begin
|
|
|
if (fsm == FSM_CFG_WAIT)
|
if (fsm == FSM_CFG_WAIT)
|
begin
|
begin
|
dclk_rst_reg1 <= 1'd1;
|
dclk_rst_reg1 <= 1'd1;
|
dclk_rst_reg2 <= dclk_rst_reg1;
|
dclk_rst_reg2 <= dclk_rst_reg1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
dclk_rst_reg1 <= 1'd0;
|
dclk_rst_reg1 <= 1'd0;
|
dclk_rst_reg2 <= dclk_rst_reg1;
|
dclk_rst_reg2 <= dclk_rst_reg1;
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- PIPE Reset Output -------------------------------------------------
|
//---------- PIPE Reset Output -------------------------------------------------
|
assign RST_CPLLRESET = pllreset;
|
assign RST_CPLLRESET = pllreset;
|
assign RST_CPLLPD = pllpd;
|
assign RST_CPLLPD = pllpd;
|
assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2;
|
assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2;
|
assign RST_DCLK_RESET = dclk_rst_reg2;
|
assign RST_DCLK_RESET = dclk_rst_reg2;
|
assign RST_GTRESET = gtreset;
|
assign RST_GTRESET = gtreset;
|
assign RST_USERRDY = userrdy;
|
assign RST_USERRDY = userrdy;
|
assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START);
|
assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START);
|
assign RST_IDLE = (fsm == FSM_IDLE);
|
assign RST_IDLE = (fsm == FSM_IDLE);
|
assign RST_FSM = fsm;
|
assign RST_FSM = fsm;
|
|
|
|
|
|
|
//--------------------------------------------------------------------------------------------------
|
//--------------------------------------------------------------------------------------------------
|
// Register Output
|
// Register Output
|
//--------------------------------------------------------------------------------------------------
|
//--------------------------------------------------------------------------------------------------
|
always @ (posedge RST_CLK)
|
always @ (posedge RST_CLK)
|
begin
|
begin
|
|
|
if (!RST_RST_N)
|
if (!RST_RST_N)
|
begin
|
begin
|
RST_DRP_START <= 1'd0;
|
RST_DRP_START <= 1'd0;
|
RST_DRP_X16 <= 1'd0;
|
RST_DRP_X16 <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RST_DRP_START <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
|
RST_DRP_START <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
|
RST_DRP_X16 <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
|
RST_DRP_X16 <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
