-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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--
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--
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-- This file contains confidential and proprietary information
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- international copyright and other intellectual property
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-- laws.
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-- laws.
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--
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--
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-- DISCLAIMER
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Project : Series-7 Integrated Block for PCI Express
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-- Project : Series-7 Integrated Block for PCI Express
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-- File : cl_a7pcie_x4_pcie_pipe_lane.vhd
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-- File : cl_a7pcie_x4_pcie_pipe_lane.vhd
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-- Version : 1.10
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-- Version : 1.11
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--
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--
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-- Description: PIPE per lane module for 7-Series PCIe Block
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-- Description: PIPE per lane module for 7-Series PCIe Block
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--
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--
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--
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--
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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|
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entity cl_a7pcie_x4_pcie_pipe_lane is
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entity cl_a7pcie_x4_pcie_pipe_lane is
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generic
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generic
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(
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(
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PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
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PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
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);
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);
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port
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port
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(
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(
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pipe_rx_char_is_k_o : out std_logic_vector( 1 downto 0); -- Pipelined PIPE Rx Char Is K
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pipe_rx_char_is_k_o : out std_logic_vector( 1 downto 0); -- Pipelined PIPE Rx Char Is K
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pipe_rx_data_o : out std_logic_vector(15 downto 0); -- Pipelined PIPE Rx Data
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pipe_rx_data_o : out std_logic_vector(15 downto 0); -- Pipelined PIPE Rx Data
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pipe_rx_valid_o : out std_logic; -- Pipelined PIPE Rx Data Valid
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pipe_rx_valid_o : out std_logic; -- Pipelined PIPE Rx Data Valid
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pipe_rx_chanisaligned_o : out std_logic; -- Pipelined PIPE Rx Chan Is Aligned
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pipe_rx_chanisaligned_o : out std_logic; -- Pipelined PIPE Rx Chan Is Aligned
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pipe_rx_status_o : out std_logic_vector( 2 downto 0); -- Pipelined PIPE Rx Status
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pipe_rx_status_o : out std_logic_vector( 2 downto 0); -- Pipelined PIPE Rx Status
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pipe_rx_phy_status_o : out std_logic; -- Pipelined PIPE Rx Phy Status
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pipe_rx_phy_status_o : out std_logic; -- Pipelined PIPE Rx Phy Status
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pipe_rx_elec_idle_o : out std_logic; -- Pipelined PIPE Rx Electrical Idle
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pipe_rx_elec_idle_o : out std_logic; -- Pipelined PIPE Rx Electrical Idle
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pipe_rx_polarity_i : in std_logic; -- PIPE Rx Polarity
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pipe_rx_polarity_i : in std_logic; -- PIPE Rx Polarity
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pipe_tx_compliance_i : in std_logic; -- PIPE Tx Compliance
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pipe_tx_compliance_i : in std_logic; -- PIPE Tx Compliance
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pipe_tx_char_is_k_i : in std_logic_vector( 1 downto 0); -- PIPE Tx Char Is K
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pipe_tx_char_is_k_i : in std_logic_vector( 1 downto 0); -- PIPE Tx Char Is K
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pipe_tx_data_i : in std_logic_vector(15 downto 0); -- PIPE Tx Data
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pipe_tx_data_i : in std_logic_vector(15 downto 0); -- PIPE Tx Data
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pipe_tx_elec_idle_i : in std_logic; -- PIPE Tx Electrical Idle
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pipe_tx_elec_idle_i : in std_logic; -- PIPE Tx Electrical Idle
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pipe_tx_powerdown_i : in std_logic_vector( 1 downto 0); -- PIPE Tx Powerdown
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pipe_tx_powerdown_i : in std_logic_vector( 1 downto 0); -- PIPE Tx Powerdown
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pipe_rx_char_is_k_i : in std_logic_vector( 1 downto 0); -- PIPE Rx Char Is K
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pipe_rx_char_is_k_i : in std_logic_vector( 1 downto 0); -- PIPE Rx Char Is K
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pipe_rx_data_i : in std_logic_vector(15 downto 0); -- PIPE Rx Data
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pipe_rx_data_i : in std_logic_vector(15 downto 0); -- PIPE Rx Data
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pipe_rx_valid_i : in std_logic; -- PIPE Rx Data Valid
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pipe_rx_valid_i : in std_logic; -- PIPE Rx Data Valid
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pipe_rx_chanisaligned_i : in std_logic; -- PIPE Rx Chan Is Aligned
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pipe_rx_chanisaligned_i : in std_logic; -- PIPE Rx Chan Is Aligned
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pipe_rx_status_i : in std_logic_vector( 2 downto 0); -- PIPE Rx Status
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pipe_rx_status_i : in std_logic_vector( 2 downto 0); -- PIPE Rx Status
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pipe_rx_phy_status_i : in std_logic; -- PIPE Rx Phy Status
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pipe_rx_phy_status_i : in std_logic; -- PIPE Rx Phy Status
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pipe_rx_elec_idle_i : in std_logic; -- PIPE Rx Electrical Idle
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pipe_rx_elec_idle_i : in std_logic; -- PIPE Rx Electrical Idle
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pipe_rx_polarity_o : out std_logic; -- Pipelined PIPE Rx Polarity
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pipe_rx_polarity_o : out std_logic; -- Pipelined PIPE Rx Polarity
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pipe_tx_compliance_o : out std_logic; -- Pipelined PIPE Tx Compliance
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pipe_tx_compliance_o : out std_logic; -- Pipelined PIPE Tx Compliance
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pipe_tx_char_is_k_o : out std_logic_vector( 1 downto 0); -- Pipelined PIPE Tx Char Is K
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pipe_tx_char_is_k_o : out std_logic_vector( 1 downto 0); -- Pipelined PIPE Tx Char Is K
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pipe_tx_data_o : out std_logic_vector(15 downto 0); -- Pipelined PIPE Tx Data
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pipe_tx_data_o : out std_logic_vector(15 downto 0); -- Pipelined PIPE Tx Data
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pipe_tx_elec_idle_o : out std_logic; -- Pipelined PIPE Tx Electrical
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pipe_tx_elec_idle_o : out std_logic; -- Pipelined PIPE Tx Electrical
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pipe_tx_powerdown_o : out std_logic_vector( 1 downto 0); -- Pipelined PIPE Tx Powerdown
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pipe_tx_powerdown_o : out std_logic_vector( 1 downto 0); -- Pipelined PIPE Tx Powerdown
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|
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pipe_clk : in std_logic; -- PIPE Clock
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pipe_clk : in std_logic; -- PIPE Clock
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rst_n : in std_logic -- Reset
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rst_n : in std_logic -- Reset
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);
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);
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end cl_a7pcie_x4_pcie_pipe_lane;
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end cl_a7pcie_x4_pcie_pipe_lane;
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|
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architecture rtl of cl_a7pcie_x4_pcie_pipe_lane is
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architecture rtl of cl_a7pcie_x4_pcie_pipe_lane is
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|
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--******************************************************************--
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--******************************************************************--
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-- Reality check. --
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-- Reality check. --
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--******************************************************************--
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--******************************************************************--
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constant TCQ : integer := 1;
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constant TCQ : integer := 1;
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signal pipe_rx_char_is_k_q : std_logic_vector(1 downto 0);
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signal pipe_rx_char_is_k_q : std_logic_vector(1 downto 0);
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signal pipe_rx_data_q : std_logic_vector(15 downto 0);
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signal pipe_rx_data_q : std_logic_vector(15 downto 0);
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signal pipe_rx_valid_q : std_logic;
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signal pipe_rx_valid_q : std_logic;
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signal pipe_rx_chanisaligned_q : std_logic;
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signal pipe_rx_chanisaligned_q : std_logic;
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signal pipe_rx_status_q : std_logic_vector(2 downto 0);
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signal pipe_rx_status_q : std_logic_vector(2 downto 0);
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signal pipe_rx_phy_status_q : std_logic;
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signal pipe_rx_phy_status_q : std_logic;
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signal pipe_rx_elec_idle_q : std_logic;
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signal pipe_rx_elec_idle_q : std_logic;
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|
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signal pipe_rx_polarity_q : std_logic;
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signal pipe_rx_polarity_q : std_logic;
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signal pipe_tx_compliance_q : std_logic;
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signal pipe_tx_compliance_q : std_logic;
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signal pipe_tx_char_is_k_q : std_logic_vector(1 downto 0);
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signal pipe_tx_char_is_k_q : std_logic_vector(1 downto 0);
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signal pipe_tx_data_q : std_logic_vector(15 downto 0);
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signal pipe_tx_data_q : std_logic_vector(15 downto 0);
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signal pipe_tx_elec_idle_q : std_logic;
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signal pipe_tx_elec_idle_q : std_logic;
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signal pipe_tx_powerdown_q : std_logic_vector(1 downto 0);
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signal pipe_tx_powerdown_q : std_logic_vector(1 downto 0);
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|
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signal pipe_rx_char_is_k_qq : std_logic_vector(1 downto 0);
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signal pipe_rx_char_is_k_qq : std_logic_vector(1 downto 0);
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signal pipe_rx_data_qq : std_logic_vector(15 downto 0);
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signal pipe_rx_data_qq : std_logic_vector(15 downto 0);
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signal pipe_rx_valid_qq : std_logic;
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signal pipe_rx_valid_qq : std_logic;
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signal pipe_rx_chanisaligned_qq : std_logic;
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signal pipe_rx_chanisaligned_qq : std_logic;
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signal pipe_rx_status_qq : std_logic_vector(2 downto 0);
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signal pipe_rx_status_qq : std_logic_vector(2 downto 0);
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signal pipe_rx_phy_status_qq : std_logic;
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signal pipe_rx_phy_status_qq : std_logic;
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signal pipe_rx_elec_idle_qq : std_logic;
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signal pipe_rx_elec_idle_qq : std_logic;
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|
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signal pipe_rx_polarity_qq : std_logic;
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signal pipe_rx_polarity_qq : std_logic;
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signal pipe_tx_compliance_qq : std_logic;
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signal pipe_tx_compliance_qq : std_logic;
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signal pipe_tx_char_is_k_qq : std_logic_vector(1 downto 0);
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signal pipe_tx_char_is_k_qq : std_logic_vector(1 downto 0);
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signal pipe_tx_data_qq : std_logic_vector(15 downto 0);
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signal pipe_tx_data_qq : std_logic_vector(15 downto 0);
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signal pipe_tx_elec_idle_qq : std_logic;
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signal pipe_tx_elec_idle_qq : std_logic;
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signal pipe_tx_powerdown_qq : std_logic_vector(1 downto 0);
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signal pipe_tx_powerdown_qq : std_logic_vector(1 downto 0);
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|
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begin -- rtl
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begin -- rtl
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|
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pipe_stages_0 : if (PIPE_PIPELINE_STAGES = 0) generate
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pipe_stages_0 : if (PIPE_PIPELINE_STAGES = 0) generate
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|
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pipe_rx_char_is_k_o <= pipe_rx_char_is_k_i;
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pipe_rx_char_is_k_o <= pipe_rx_char_is_k_i;
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pipe_rx_data_o <= pipe_rx_data_i;
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pipe_rx_data_o <= pipe_rx_data_i;
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pipe_rx_valid_o <= pipe_rx_valid_i;
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pipe_rx_valid_o <= pipe_rx_valid_i;
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pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_i;
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pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_i;
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pipe_rx_status_o <= pipe_rx_status_i;
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pipe_rx_status_o <= pipe_rx_status_i;
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pipe_rx_phy_status_o <= pipe_rx_phy_status_i;
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pipe_rx_phy_status_o <= pipe_rx_phy_status_i;
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pipe_rx_elec_idle_o <= pipe_rx_elec_idle_i;
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pipe_rx_elec_idle_o <= pipe_rx_elec_idle_i;
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|
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pipe_rx_polarity_o <= pipe_rx_polarity_i;
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pipe_rx_polarity_o <= pipe_rx_polarity_i;
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pipe_tx_compliance_o <= pipe_tx_compliance_i;
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pipe_tx_compliance_o <= pipe_tx_compliance_i;
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pipe_tx_char_is_k_o <= pipe_tx_char_is_k_i;
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pipe_tx_char_is_k_o <= pipe_tx_char_is_k_i;
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pipe_tx_data_o <= pipe_tx_data_i;
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pipe_tx_data_o <= pipe_tx_data_i;
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pipe_tx_elec_idle_o <= pipe_tx_elec_idle_i;
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pipe_tx_elec_idle_o <= pipe_tx_elec_idle_i;
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pipe_tx_powerdown_o <= pipe_tx_powerdown_i;
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pipe_tx_powerdown_o <= pipe_tx_powerdown_i;
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end generate; -- pipe_stages_0
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end generate; -- pipe_stages_0
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pipe_stages_1 : if (PIPE_PIPELINE_STAGES = 1) generate
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pipe_stages_1 : if (PIPE_PIPELINE_STAGES = 1) generate
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|
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process (pipe_clk)
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process (pipe_clk)
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begin
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begin
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if (pipe_clk'event and pipe_clk = '1') then
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if (pipe_clk'event and pipe_clk = '1') then
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|
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if (rst_n = '1') then
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if (rst_n = '1') then
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pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps;
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pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps;
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pipe_rx_data_q <= (others => '0') after (TCQ)*1 ps;
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pipe_rx_data_q <= (others => '0') after (TCQ)*1 ps;
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pipe_rx_valid_q <= '0' after (TCQ)*1 ps;
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pipe_rx_valid_q <= '0' after (TCQ)*1 ps;
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pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps;
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pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps;
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pipe_rx_status_q <= "000" after (TCQ)*1 ps;
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pipe_rx_status_q <= "000" after (TCQ)*1 ps;
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pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps;
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pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps;
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|
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pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps;
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pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps;
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pipe_rx_polarity_q <= '0' after (TCQ)*1 ps;
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pipe_rx_polarity_q <= '0' after (TCQ)*1 ps;
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pipe_tx_compliance_q <= '0' after (TCQ)*1 ps;
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pipe_tx_compliance_q <= '0' after (TCQ)*1 ps;
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pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps;
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pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps;
|
pipe_tx_data_q <= (others => '0') after (TCQ)*1 ps;
|
pipe_tx_data_q <= (others => '0') after (TCQ)*1 ps;
|
pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps;
|
pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps;
|
pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps;
|
pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps;
|
|
|
else
|
else
|
|
|
pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps;
|
pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps;
|
pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps;
|
pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps;
|
pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps;
|
pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps;
|
pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps;
|
pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps;
|
pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps;
|
pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps;
|
pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps;
|
pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps;
|
|
|
pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps;
|
pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps;
|
pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps;
|
pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps;
|
pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps;
|
pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps;
|
pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps;
|
pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps;
|
pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps;
|
pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps;
|
pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps;
|
pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps;
|
pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps;
|
pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
pipe_rx_char_is_k_o <= pipe_rx_char_is_k_q;
|
pipe_rx_char_is_k_o <= pipe_rx_char_is_k_q;
|
pipe_rx_data_o <= pipe_rx_data_q;
|
pipe_rx_data_o <= pipe_rx_data_q;
|
pipe_rx_valid_o <= pipe_rx_valid_q;
|
pipe_rx_valid_o <= pipe_rx_valid_q;
|
pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_q;
|
pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_q;
|
pipe_rx_status_o <= pipe_rx_status_q;
|
pipe_rx_status_o <= pipe_rx_status_q;
|
pipe_rx_phy_status_o <= pipe_rx_phy_status_q;
|
pipe_rx_phy_status_o <= pipe_rx_phy_status_q;
|
pipe_rx_elec_idle_o <= pipe_rx_elec_idle_q;
|
pipe_rx_elec_idle_o <= pipe_rx_elec_idle_q;
|
|
|
pipe_rx_polarity_o <= pipe_rx_polarity_q;
|
pipe_rx_polarity_o <= pipe_rx_polarity_q;
|
pipe_tx_compliance_o <= pipe_tx_compliance_q;
|
pipe_tx_compliance_o <= pipe_tx_compliance_q;
|
pipe_tx_char_is_k_o <= pipe_tx_char_is_k_q;
|
pipe_tx_char_is_k_o <= pipe_tx_char_is_k_q;
|
pipe_tx_data_o <= pipe_tx_data_q;
|
pipe_tx_data_o <= pipe_tx_data_q;
|
pipe_tx_elec_idle_o <= pipe_tx_elec_idle_q;
|
pipe_tx_elec_idle_o <= pipe_tx_elec_idle_q;
|
pipe_tx_powerdown_o <= pipe_tx_powerdown_q;
|
pipe_tx_powerdown_o <= pipe_tx_powerdown_q;
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|
|
end generate; -- pipe_stages_1
|
end generate; -- pipe_stages_1
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|
|
pipe_stages_2 : if (PIPE_PIPELINE_STAGES = 2) generate
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pipe_stages_2 : if (PIPE_PIPELINE_STAGES = 2) generate
|
|
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process (pipe_clk)
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process (pipe_clk)
|
begin
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begin
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if (pipe_clk'event and pipe_clk = '1') then
|
if (pipe_clk'event and pipe_clk = '1') then
|
|
|
if (rst_n = '1') then
|
if (rst_n = '1') then
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pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps;
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pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps;
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pipe_rx_data_q <= (others => '0') after (TCQ)*1 ps;
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pipe_rx_data_q <= (others => '0') after (TCQ)*1 ps;
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pipe_rx_valid_q <= '0' after (TCQ)*1 ps;
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pipe_rx_valid_q <= '0' after (TCQ)*1 ps;
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pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps;
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pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps;
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pipe_rx_status_q <= "000" after (TCQ)*1 ps;
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pipe_rx_status_q <= "000" after (TCQ)*1 ps;
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pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps;
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pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps;
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|
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pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps;
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pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps;
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pipe_rx_polarity_q <= '0' after (TCQ)*1 ps;
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pipe_rx_polarity_q <= '0' after (TCQ)*1 ps;
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pipe_tx_compliance_q <= '0' after (TCQ)*1 ps;
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pipe_tx_compliance_q <= '0' after (TCQ)*1 ps;
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pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps;
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pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps;
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pipe_tx_data_q <= (others => '0') after (TCQ)*1 ps;
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pipe_tx_data_q <= (others => '0') after (TCQ)*1 ps;
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pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps;
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pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps;
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pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps;
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pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps;
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|
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pipe_rx_char_is_k_qq <= "00" after (TCQ)*1 ps;
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pipe_rx_char_is_k_qq <= "00" after (TCQ)*1 ps;
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pipe_rx_data_qq <= (others => '0') after (TCQ)*1 ps;
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pipe_rx_data_qq <= (others => '0') after (TCQ)*1 ps;
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pipe_rx_valid_qq <= '0' after (TCQ)*1 ps;
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pipe_rx_valid_qq <= '0' after (TCQ)*1 ps;
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pipe_rx_chanisaligned_qq <= '0' after (TCQ)*1 ps;
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pipe_rx_chanisaligned_qq <= '0' after (TCQ)*1 ps;
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pipe_rx_status_qq <= "000" after (TCQ)*1 ps;
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pipe_rx_status_qq <= "000" after (TCQ)*1 ps;
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pipe_rx_phy_status_qq <= '0' after (TCQ)*1 ps;
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pipe_rx_phy_status_qq <= '0' after (TCQ)*1 ps;
|
|
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pipe_rx_elec_idle_qq <= '0' after (TCQ)*1 ps;
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pipe_rx_elec_idle_qq <= '0' after (TCQ)*1 ps;
|
pipe_rx_polarity_qq <= '0' after (TCQ)*1 ps;
|
pipe_rx_polarity_qq <= '0' after (TCQ)*1 ps;
|
pipe_tx_compliance_qq <= '0' after (TCQ)*1 ps;
|
pipe_tx_compliance_qq <= '0' after (TCQ)*1 ps;
|
pipe_tx_char_is_k_qq <= "00" after (TCQ)*1 ps;
|
pipe_tx_char_is_k_qq <= "00" after (TCQ)*1 ps;
|
pipe_tx_data_qq <= (others => '0') after (TCQ)*1 ps;
|
pipe_tx_data_qq <= (others => '0') after (TCQ)*1 ps;
|
pipe_tx_elec_idle_qq <= '1' after (TCQ)*1 ps;
|
pipe_tx_elec_idle_qq <= '1' after (TCQ)*1 ps;
|
pipe_tx_powerdown_qq <= "10" after (TCQ)*1 ps;
|
pipe_tx_powerdown_qq <= "10" after (TCQ)*1 ps;
|
else
|
else
|
|
|
pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps;
|
pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps;
|
pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps;
|
pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps;
|
pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps;
|
pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps;
|
pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps;
|
pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps;
|
pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps;
|
pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps;
|
pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps;
|
pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps;
|
|
|
pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps;
|
pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps;
|
pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps;
|
pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps;
|
pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps;
|
pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps;
|
pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps;
|
pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps;
|
pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps;
|
pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps;
|
pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps;
|
pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps;
|
pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps;
|
pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps;
|
|
|
pipe_rx_char_is_k_qq <= pipe_rx_char_is_k_q after (TCQ)*1 ps;
|
pipe_rx_char_is_k_qq <= pipe_rx_char_is_k_q after (TCQ)*1 ps;
|
pipe_rx_data_qq <= pipe_rx_data_q after (TCQ)*1 ps;
|
pipe_rx_data_qq <= pipe_rx_data_q after (TCQ)*1 ps;
|
pipe_rx_valid_qq <= pipe_rx_valid_q after (TCQ)*1 ps;
|
pipe_rx_valid_qq <= pipe_rx_valid_q after (TCQ)*1 ps;
|
pipe_rx_chanisaligned_qq <= pipe_rx_chanisaligned_q after (TCQ)*1 ps;
|
pipe_rx_chanisaligned_qq <= pipe_rx_chanisaligned_q after (TCQ)*1 ps;
|
pipe_rx_status_qq <= pipe_rx_status_q after (TCQ)*1 ps;
|
pipe_rx_status_qq <= pipe_rx_status_q after (TCQ)*1 ps;
|
pipe_rx_phy_status_qq <= pipe_rx_phy_status_q after (TCQ)*1 ps;
|
pipe_rx_phy_status_qq <= pipe_rx_phy_status_q after (TCQ)*1 ps;
|
|
|
pipe_rx_elec_idle_qq <= pipe_rx_elec_idle_q after (TCQ)*1 ps;
|
pipe_rx_elec_idle_qq <= pipe_rx_elec_idle_q after (TCQ)*1 ps;
|
pipe_rx_polarity_qq <= pipe_rx_polarity_q after (TCQ)*1 ps;
|
pipe_rx_polarity_qq <= pipe_rx_polarity_q after (TCQ)*1 ps;
|
pipe_tx_compliance_qq <= pipe_tx_compliance_q after (TCQ)*1 ps;
|
pipe_tx_compliance_qq <= pipe_tx_compliance_q after (TCQ)*1 ps;
|
pipe_tx_char_is_k_qq <= pipe_tx_char_is_k_q after (TCQ)*1 ps;
|
pipe_tx_char_is_k_qq <= pipe_tx_char_is_k_q after (TCQ)*1 ps;
|
pipe_tx_data_qq <= pipe_tx_data_q after (TCQ)*1 ps;
|
pipe_tx_data_qq <= pipe_tx_data_q after (TCQ)*1 ps;
|
pipe_tx_elec_idle_qq <= pipe_tx_elec_idle_q after (TCQ)*1 ps;
|
pipe_tx_elec_idle_qq <= pipe_tx_elec_idle_q after (TCQ)*1 ps;
|
pipe_tx_powerdown_qq <= pipe_tx_powerdown_q after (TCQ)*1 ps;
|
pipe_tx_powerdown_qq <= pipe_tx_powerdown_q after (TCQ)*1 ps;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
pipe_rx_char_is_k_o <= pipe_rx_char_is_k_qq;
|
pipe_rx_char_is_k_o <= pipe_rx_char_is_k_qq;
|
pipe_rx_data_o <= pipe_rx_data_qq;
|
pipe_rx_data_o <= pipe_rx_data_qq;
|
pipe_rx_valid_o <= pipe_rx_valid_qq;
|
pipe_rx_valid_o <= pipe_rx_valid_qq;
|
pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_qq;
|
pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_qq;
|
pipe_rx_status_o <= pipe_rx_status_qq;
|
pipe_rx_status_o <= pipe_rx_status_qq;
|
pipe_rx_phy_status_o <= pipe_rx_phy_status_qq;
|
pipe_rx_phy_status_o <= pipe_rx_phy_status_qq;
|
pipe_rx_elec_idle_o <= pipe_rx_elec_idle_qq;
|
pipe_rx_elec_idle_o <= pipe_rx_elec_idle_qq;
|
|
|
pipe_rx_polarity_o <= pipe_rx_polarity_qq;
|
pipe_rx_polarity_o <= pipe_rx_polarity_qq;
|
pipe_tx_compliance_o <= pipe_tx_compliance_qq;
|
pipe_tx_compliance_o <= pipe_tx_compliance_qq;
|
pipe_tx_char_is_k_o <= pipe_tx_char_is_k_qq;
|
pipe_tx_char_is_k_o <= pipe_tx_char_is_k_qq;
|
pipe_tx_data_o <= pipe_tx_data_qq;
|
pipe_tx_data_o <= pipe_tx_data_qq;
|
pipe_tx_elec_idle_o <= pipe_tx_elec_idle_qq;
|
pipe_tx_elec_idle_o <= pipe_tx_elec_idle_qq;
|
pipe_tx_powerdown_o <= pipe_tx_powerdown_qq;
|
pipe_tx_powerdown_o <= pipe_tx_powerdown_qq;
|
|
|
end generate; -- pipe_stages_2
|
end generate; -- pipe_stages_2
|
|
|
end rtl;
|
end rtl;
|
|
|
|
|