//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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//
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// This file contains confidential and proprietary information
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// international copyright and other intellectual property
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// laws.
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// laws.
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//
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//
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// DISCLAIMER
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// CRITICAL APPLICATIONS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_pipe_rate.v
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// File : cl_a7pcie_x4_pipe_rate.v
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// Version : 1.10
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// Version : 1.11
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Filename : pipe_rate.v
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// Filename : pipe_rate.v
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// Description : PIPE Rate Module for 7 Series Transceiver
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// Description : PIPE Rate Module for 7 Series Transceiver
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// Version : 20.1
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// Version : 20.1
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//---------- PIPE Rate Module --------------------------------------------------
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//---------- PIPE Rate Module --------------------------------------------------
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module cl_a7pcie_x4_pipe_rate #
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module cl_a7pcie_x4_pipe_rate #
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(
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(
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parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
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parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
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parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
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parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
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parameter PCIE_USE_MODE = "3.0", // PCIe use mode
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parameter PCIE_USE_MODE = "3.0", // PCIe use mode
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parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
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parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
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parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
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parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
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parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
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parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
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parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
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parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
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parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
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parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
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parameter TXDATA_WAIT_MAX = 4'd15 // TXDATA wait max
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parameter TXDATA_WAIT_MAX = 4'd15 // TXDATA wait max
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)
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)
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(
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(
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//---------- Input -------------------------------------
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//---------- Input -------------------------------------
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input RATE_CLK,
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input RATE_CLK,
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input RATE_RST_N,
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input RATE_RST_N,
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input RATE_RST_IDLE,
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input RATE_RST_IDLE,
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input RATE_ACTIVE_LANE,
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input RATE_ACTIVE_LANE,
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input [ 1:0] RATE_RATE_IN,
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input [ 1:0] RATE_RATE_IN,
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input RATE_CPLLLOCK,
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input RATE_CPLLLOCK,
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input RATE_QPLLLOCK,
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input RATE_QPLLLOCK,
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input RATE_MMCM_LOCK,
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input RATE_MMCM_LOCK,
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input RATE_DRP_DONE,
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input RATE_DRP_DONE,
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input RATE_RXPMARESETDONE,
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input RATE_RXPMARESETDONE,
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input RATE_TXRESETDONE,
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input RATE_TXRESETDONE,
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input RATE_RXRESETDONE,
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input RATE_RXRESETDONE,
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input RATE_TXRATEDONE,
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input RATE_TXRATEDONE,
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input RATE_RXRATEDONE,
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input RATE_RXRATEDONE,
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input RATE_PHYSTATUS,
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input RATE_PHYSTATUS,
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input RATE_RESETOVRD_DONE,
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input RATE_RESETOVRD_DONE,
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input RATE_TXSYNC_DONE,
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input RATE_TXSYNC_DONE,
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input RATE_RXSYNC_DONE,
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input RATE_RXSYNC_DONE,
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//---------- Output ------------------------------------
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//---------- Output ------------------------------------
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output RATE_CPLLPD,
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output RATE_CPLLPD,
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output RATE_QPLLPD,
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output RATE_QPLLPD,
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output RATE_CPLLRESET,
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output RATE_CPLLRESET,
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output RATE_QPLLRESET,
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output RATE_QPLLRESET,
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output RATE_TXPMARESET,
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output RATE_TXPMARESET,
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output RATE_RXPMARESET,
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output RATE_RXPMARESET,
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output RATE_DRP_START,
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output RATE_DRP_START,
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output [ 1:0] RATE_SYSCLKSEL,
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output [ 1:0] RATE_SYSCLKSEL,
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output RATE_PCLK_SEL,
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output RATE_PCLK_SEL,
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output RATE_GEN3,
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output RATE_GEN3,
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output RATE_DRP_X16X20_MODE,
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output RATE_DRP_X16X20_MODE,
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output RATE_DRP_X16,
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output RATE_DRP_X16,
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output [ 2:0] RATE_RATE_OUT,
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output [ 2:0] RATE_RATE_OUT,
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output RATE_RESETOVRD_START,
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output RATE_RESETOVRD_START,
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output RATE_TXSYNC_START,
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output RATE_TXSYNC_START,
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output RATE_DONE,
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output RATE_DONE,
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output RATE_RXSYNC_START,
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output RATE_RXSYNC_START,
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output RATE_RXSYNC,
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output RATE_RXSYNC,
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output RATE_IDLE,
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output RATE_IDLE,
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output [ 4:0] RATE_FSM
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output [ 4:0] RATE_FSM
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);
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);
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//---------- Input FF or Buffer ------------------------
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//---------- Input FF or Buffer ------------------------
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg2;
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//---------- Internal Signals --------------------------
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//---------- Internal Signals --------------------------
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wire pll_lock;
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wire pll_lock;
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wire [ 2:0] rate;
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wire [ 2:0] rate;
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reg [ 3:0] txdata_wait_cnt = 4'd0;
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reg [ 3:0] txdata_wait_cnt = 4'd0;
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reg txratedone = 1'd0;
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reg txratedone = 1'd0;
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reg rxratedone = 1'd0;
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reg rxratedone = 1'd0;
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reg phystatus = 1'd0;
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reg phystatus = 1'd0;
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reg ratedone = 1'd0;
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reg ratedone = 1'd0;
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reg gen3_exit = 1'd0;
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reg gen3_exit = 1'd0;
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//---------- Output FF or Buffer -----------------------
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//---------- Output FF or Buffer -----------------------
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reg cpllpd = 1'd0;
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reg cpllpd = 1'd0;
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reg qpllpd = 1'd0;
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reg qpllpd = 1'd0;
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reg cpllreset = 1'd0;
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reg cpllreset = 1'd0;
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reg qpllreset = 1'd0;
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reg qpllreset = 1'd0;
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reg txpmareset = 1'd0;
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reg txpmareset = 1'd0;
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reg rxpmareset = 1'd0;
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reg rxpmareset = 1'd0;
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reg [ 1:0] sysclksel = (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
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reg [ 1:0] sysclksel = (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
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reg gen3 = 1'd0;
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reg gen3 = 1'd0;
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reg pclk_sel = 1'd0;
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reg pclk_sel = 1'd0;
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reg [ 2:0] rate_out = 3'd0;
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reg [ 2:0] rate_out = 3'd0;
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reg drp_start = 1'd0;
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reg drp_start = 1'd0;
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reg drp_x16x20_mode = 1'd0;
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reg drp_x16x20_mode = 1'd0;
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reg drp_x16 = 1'd0;
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reg drp_x16 = 1'd0;
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reg [ 4:0] fsm = 0;
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reg [ 4:0] fsm = 0;
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//---------- FSM ---------------------------------------
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//---------- FSM ---------------------------------------
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localparam FSM_IDLE = 0;
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localparam FSM_IDLE = 0;
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localparam FSM_PLL_PU = 1; // Gen 3 only
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localparam FSM_PLL_PU = 1; // Gen 3 only
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localparam FSM_PLL_PURESET = 2; // Gen 3 only
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localparam FSM_PLL_PURESET = 2; // Gen 3 only
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localparam FSM_PLL_LOCK = 3; // Gen 3 or reset only
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localparam FSM_PLL_LOCK = 3; // Gen 3 or reset only
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localparam FSM_DRP_X16_GEN3_START = 4;
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localparam FSM_DRP_X16_GEN3_START = 4;
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localparam FSM_DRP_X16_GEN3_DONE = 5;
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localparam FSM_DRP_X16_GEN3_DONE = 5;
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localparam FSM_PMARESET_HOLD = 6; // Gen 3 or reset only
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localparam FSM_PMARESET_HOLD = 6; // Gen 3 or reset only
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localparam FSM_PLL_SEL = 7; // Gen 3 or reset only
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localparam FSM_PLL_SEL = 7; // Gen 3 or reset only
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localparam FSM_MMCM_LOCK = 8; // Gen 3 or reset only
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localparam FSM_MMCM_LOCK = 8; // Gen 3 or reset only
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localparam FSM_DRP_START = 9; // Gen 3 or reset only
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localparam FSM_DRP_START = 9; // Gen 3 or reset only
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localparam FSM_DRP_DONE = 10; // Gen 3 or reset only
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localparam FSM_DRP_DONE = 10; // Gen 3 or reset only
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localparam FSM_PMARESET_RELEASE = 11; // Gen 3 only
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localparam FSM_PMARESET_RELEASE = 11; // Gen 3 only
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localparam FSM_PMARESET_DONE = 12; // Gen 3 only
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localparam FSM_PMARESET_DONE = 12; // Gen 3 only
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localparam FSM_TXDATA_WAIT = 13;
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localparam FSM_TXDATA_WAIT = 13;
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localparam FSM_PCLK_SEL = 14;
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localparam FSM_PCLK_SEL = 14;
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localparam FSM_DRP_X16_START = 15;
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localparam FSM_DRP_X16_START = 15;
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localparam FSM_DRP_X16_DONE = 16;
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localparam FSM_DRP_X16_DONE = 16;
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localparam FSM_RATE_SEL = 17;
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localparam FSM_RATE_SEL = 17;
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localparam FSM_RXPMARESETDONE = 18;
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localparam FSM_RXPMARESETDONE = 18;
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localparam FSM_DRP_X20_START = 19;
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localparam FSM_DRP_X20_START = 19;
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localparam FSM_DRP_X20_DONE = 20;
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localparam FSM_DRP_X20_DONE = 20;
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localparam FSM_RATE_DONE = 21;
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localparam FSM_RATE_DONE = 21;
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localparam FSM_RESETOVRD_START = 22; // PCIe use mode 1.0 only
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localparam FSM_RESETOVRD_START = 22; // PCIe use mode 1.0 only
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localparam FSM_RESETOVRD_DONE = 23; // PCIe use mode 1.0 only
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localparam FSM_RESETOVRD_DONE = 23; // PCIe use mode 1.0 only
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localparam FSM_PLL_PDRESET = 24;
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localparam FSM_PLL_PDRESET = 24;
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localparam FSM_PLL_PD = 25;
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localparam FSM_PLL_PD = 25;
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localparam FSM_TXSYNC_START = 26;
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localparam FSM_TXSYNC_START = 26;
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localparam FSM_TXSYNC_DONE = 27;
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localparam FSM_TXSYNC_DONE = 27;
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localparam FSM_DONE = 28; // Must sync value to pipe_user.v
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localparam FSM_DONE = 28; // Must sync value to pipe_user.v
|
localparam FSM_RXSYNC_START = 29; // Gen 3 only
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localparam FSM_RXSYNC_START = 29; // Gen 3 only
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localparam FSM_RXSYNC_DONE = 30; // Gen 3 only
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localparam FSM_RXSYNC_DONE = 30; // Gen 3 only
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|
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//---------- Input FF ----------------------------------------------------------
|
//---------- Input FF ----------------------------------------------------------
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always @ (posedge RATE_CLK)
|
always @ (posedge RATE_CLK)
|
begin
|
begin
|
|
|
if (!RATE_RST_N)
|
if (!RATE_RST_N)
|
begin
|
begin
|
//---------- 1st Stage FF --------------------------
|
//---------- 1st Stage FF --------------------------
|
rst_idle_reg1 <= 1'd0;
|
rst_idle_reg1 <= 1'd0;
|
rate_in_reg1 <= 2'd0;
|
rate_in_reg1 <= 2'd0;
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cplllock_reg1 <= 1'd0;
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cplllock_reg1 <= 1'd0;
|
qplllock_reg1 <= 1'd0;
|
qplllock_reg1 <= 1'd0;
|
mmcm_lock_reg1 <= 1'd0;
|
mmcm_lock_reg1 <= 1'd0;
|
drp_done_reg1 <= 1'd0;
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drp_done_reg1 <= 1'd0;
|
rxpmaresetdone_reg1 <= 1'd0;
|
rxpmaresetdone_reg1 <= 1'd0;
|
txresetdone_reg1 <= 1'd0;
|
txresetdone_reg1 <= 1'd0;
|
rxresetdone_reg1 <= 1'd0;
|
rxresetdone_reg1 <= 1'd0;
|
txratedone_reg1 <= 1'd0;
|
txratedone_reg1 <= 1'd0;
|
rxratedone_reg1 <= 1'd0;
|
rxratedone_reg1 <= 1'd0;
|
phystatus_reg1 <= 1'd0;
|
phystatus_reg1 <= 1'd0;
|
resetovrd_done_reg1 <= 1'd0;
|
resetovrd_done_reg1 <= 1'd0;
|
txsync_done_reg1 <= 1'd0;
|
txsync_done_reg1 <= 1'd0;
|
rxsync_done_reg1 <= 1'd0;
|
rxsync_done_reg1 <= 1'd0;
|
//---------- 2nd Stage FF --------------------------
|
//---------- 2nd Stage FF --------------------------
|
rst_idle_reg2 <= 1'd0;
|
rst_idle_reg2 <= 1'd0;
|
rate_in_reg2 <= 2'd0;
|
rate_in_reg2 <= 2'd0;
|
cplllock_reg2 <= 1'd0;
|
cplllock_reg2 <= 1'd0;
|
qplllock_reg2 <= 1'd0;
|
qplllock_reg2 <= 1'd0;
|
mmcm_lock_reg2 <= 1'd0;
|
mmcm_lock_reg2 <= 1'd0;
|
drp_done_reg2 <= 1'd0;
|
drp_done_reg2 <= 1'd0;
|
rxpmaresetdone_reg2 <= 1'd0;
|
rxpmaresetdone_reg2 <= 1'd0;
|
txresetdone_reg2 <= 1'd0;
|
txresetdone_reg2 <= 1'd0;
|
rxresetdone_reg2 <= 1'd0;
|
rxresetdone_reg2 <= 1'd0;
|
txratedone_reg2 <= 1'd0;
|
txratedone_reg2 <= 1'd0;
|
rxratedone_reg2 <= 1'd0;
|
rxratedone_reg2 <= 1'd0;
|
phystatus_reg2 <= 1'd0;
|
phystatus_reg2 <= 1'd0;
|
resetovrd_done_reg2 <= 1'd0;
|
resetovrd_done_reg2 <= 1'd0;
|
txsync_done_reg2 <= 1'd0;
|
txsync_done_reg2 <= 1'd0;
|
rxsync_done_reg2 <= 1'd0;
|
rxsync_done_reg2 <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
//---------- 1st Stage FF --------------------------
|
//---------- 1st Stage FF --------------------------
|
rst_idle_reg1 <= RATE_RST_IDLE;
|
rst_idle_reg1 <= RATE_RST_IDLE;
|
rate_in_reg1 <= RATE_RATE_IN;
|
rate_in_reg1 <= RATE_RATE_IN;
|
cplllock_reg1 <= RATE_CPLLLOCK;
|
cplllock_reg1 <= RATE_CPLLLOCK;
|
qplllock_reg1 <= RATE_QPLLLOCK;
|
qplllock_reg1 <= RATE_QPLLLOCK;
|
mmcm_lock_reg1 <= RATE_MMCM_LOCK;
|
mmcm_lock_reg1 <= RATE_MMCM_LOCK;
|
drp_done_reg1 <= RATE_DRP_DONE;
|
drp_done_reg1 <= RATE_DRP_DONE;
|
rxpmaresetdone_reg1 <= RATE_RXPMARESETDONE;
|
rxpmaresetdone_reg1 <= RATE_RXPMARESETDONE;
|
txresetdone_reg1 <= RATE_TXRESETDONE;
|
txresetdone_reg1 <= RATE_TXRESETDONE;
|
rxresetdone_reg1 <= RATE_RXRESETDONE;
|
rxresetdone_reg1 <= RATE_RXRESETDONE;
|
txratedone_reg1 <= RATE_TXRATEDONE;
|
txratedone_reg1 <= RATE_TXRATEDONE;
|
rxratedone_reg1 <= RATE_RXRATEDONE;
|
rxratedone_reg1 <= RATE_RXRATEDONE;
|
phystatus_reg1 <= RATE_PHYSTATUS;
|
phystatus_reg1 <= RATE_PHYSTATUS;
|
resetovrd_done_reg1 <= RATE_RESETOVRD_DONE;
|
resetovrd_done_reg1 <= RATE_RESETOVRD_DONE;
|
txsync_done_reg1 <= RATE_TXSYNC_DONE;
|
txsync_done_reg1 <= RATE_TXSYNC_DONE;
|
rxsync_done_reg1 <= RATE_RXSYNC_DONE;
|
rxsync_done_reg1 <= RATE_RXSYNC_DONE;
|
//---------- 2nd Stage FF --------------------------
|
//---------- 2nd Stage FF --------------------------
|
rst_idle_reg2 <= rst_idle_reg1;
|
rst_idle_reg2 <= rst_idle_reg1;
|
rate_in_reg2 <= rate_in_reg1;
|
rate_in_reg2 <= rate_in_reg1;
|
cplllock_reg2 <= cplllock_reg1;
|
cplllock_reg2 <= cplllock_reg1;
|
qplllock_reg2 <= qplllock_reg1;
|
qplllock_reg2 <= qplllock_reg1;
|
mmcm_lock_reg2 <= mmcm_lock_reg1;
|
mmcm_lock_reg2 <= mmcm_lock_reg1;
|
drp_done_reg2 <= drp_done_reg1;
|
drp_done_reg2 <= drp_done_reg1;
|
rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
|
rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
|
txresetdone_reg2 <= txresetdone_reg1;
|
txresetdone_reg2 <= txresetdone_reg1;
|
rxresetdone_reg2 <= rxresetdone_reg1;
|
rxresetdone_reg2 <= rxresetdone_reg1;
|
txratedone_reg2 <= txratedone_reg1;
|
txratedone_reg2 <= txratedone_reg1;
|
rxratedone_reg2 <= rxratedone_reg1;
|
rxratedone_reg2 <= rxratedone_reg1;
|
phystatus_reg2 <= phystatus_reg1;
|
phystatus_reg2 <= phystatus_reg1;
|
resetovrd_done_reg2 <= resetovrd_done_reg1;
|
resetovrd_done_reg2 <= resetovrd_done_reg1;
|
txsync_done_reg2 <= txsync_done_reg1;
|
txsync_done_reg2 <= txsync_done_reg1;
|
rxsync_done_reg2 <= rxsync_done_reg1;
|
rxsync_done_reg2 <= rxsync_done_reg1;
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- Select CPLL or QPLL Lock ------------------------------------------
|
//---------- Select CPLL or QPLL Lock ------------------------------------------
|
// Gen1 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock
|
// Gen1 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock
|
// Gen2 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock
|
// Gen2 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock
|
// Gen3 : Wait for QPLL lock
|
// Gen3 : Wait for QPLL lock
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
assign pll_lock = (rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL") ? qplllock_reg2 : cplllock_reg2;
|
assign pll_lock = (rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL") ? qplllock_reg2 : cplllock_reg2;
|
|
|
|
|
|
|
//---------- Select Rate -------------------------------------------------------
|
//---------- Select Rate -------------------------------------------------------
|
// Gen1 : Div 4 using [TX/RX]OUT_DIV = 4 if QPLL is used for Gen1/Gen2, else div 2 using [TX/RX]OUT_DIV = 2
|
// Gen1 : Div 4 using [TX/RX]OUT_DIV = 4 if QPLL is used for Gen1/Gen2, else div 2 using [TX/RX]OUT_DIV = 2
|
// Gen2 : Div 2 using [TX/RX]RATE = 3'd2 if QPLL is used for Gen1/Gen2, else div 1 using [TX/RX]RATE = 3'd1
|
// Gen2 : Div 2 using [TX/RX]RATE = 3'd2 if QPLL is used for Gen1/Gen2, else div 1 using [TX/RX]RATE = 3'd1
|
// Gen3 : Div 1 using [TX/RX]OUT_DIV = 1
|
// Gen3 : Div 1 using [TX/RX]OUT_DIV = 1
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
assign rate = (rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "QPLL") ? 3'd2 :
|
assign rate = (rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "QPLL") ? 3'd2 :
|
(rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "CPLL") ? 3'd1 : 3'd0;
|
(rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "CPLL") ? 3'd1 : 3'd0;
|
|
|
|
|
|
|
//---------- TXDATA Wait Counter -----------------------------------------------
|
//---------- TXDATA Wait Counter -----------------------------------------------
|
always @ (posedge RATE_CLK)
|
always @ (posedge RATE_CLK)
|
begin
|
begin
|
|
|
if (!RATE_RST_N)
|
if (!RATE_RST_N)
|
txdata_wait_cnt <= 4'd0;
|
txdata_wait_cnt <= 4'd0;
|
else
|
else
|
|
|
//---------- Increment Wait Counter ----------------
|
//---------- Increment Wait Counter ----------------
|
if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX))
|
if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX))
|
txdata_wait_cnt <= txdata_wait_cnt + 4'd1;
|
txdata_wait_cnt <= txdata_wait_cnt + 4'd1;
|
|
|
//---------- Hold Wait Counter ---------------------
|
//---------- Hold Wait Counter ---------------------
|
else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX))
|
else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX))
|
txdata_wait_cnt <= txdata_wait_cnt;
|
txdata_wait_cnt <= txdata_wait_cnt;
|
|
|
//---------- Reset Wait Counter --------------------
|
//---------- Reset Wait Counter --------------------
|
else
|
else
|
txdata_wait_cnt <= 4'd0;
|
txdata_wait_cnt <= 4'd0;
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS -----------------------
|
//---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS -----------------------
|
always @ (posedge RATE_CLK)
|
always @ (posedge RATE_CLK)
|
begin
|
begin
|
|
|
if (!RATE_RST_N)
|
if (!RATE_RST_N)
|
begin
|
begin
|
txratedone <= 1'd0;
|
txratedone <= 1'd0;
|
rxratedone <= 1'd0;
|
rxratedone <= 1'd0;
|
phystatus <= 1'd0;
|
phystatus <= 1'd0;
|
ratedone <= 1'd0;
|
ratedone <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
if (fsm == FSM_RATE_DONE)
|
if (fsm == FSM_RATE_DONE)
|
|
|
begin
|
begin
|
|
|
//---------- Latch TXRATEDONE ------------------
|
//---------- Latch TXRATEDONE ------------------
|
if (txratedone_reg2)
|
if (txratedone_reg2)
|
txratedone <= 1'd1;
|
txratedone <= 1'd1;
|
else
|
else
|
txratedone <= txratedone;
|
txratedone <= txratedone;
|
|
|
//---------- Latch RXRATEDONE ------------------
|
//---------- Latch RXRATEDONE ------------------
|
if (rxratedone_reg2)
|
if (rxratedone_reg2)
|
rxratedone <= 1'd1;
|
rxratedone <= 1'd1;
|
else
|
else
|
rxratedone <= rxratedone;
|
rxratedone <= rxratedone;
|
|
|
//---------- Latch PHYSTATUS -------------------
|
//---------- Latch PHYSTATUS -------------------
|
if (phystatus_reg2)
|
if (phystatus_reg2)
|
phystatus <= 1'd1;
|
phystatus <= 1'd1;
|
else
|
else
|
phystatus <= phystatus;
|
phystatus <= phystatus;
|
|
|
//---------- Latch Rate Done -------------------
|
//---------- Latch Rate Done -------------------
|
if (rxratedone && txratedone && phystatus)
|
if (rxratedone && txratedone && phystatus)
|
ratedone <= 1'd1;
|
ratedone <= 1'd1;
|
else
|
else
|
ratedone <= ratedone;
|
ratedone <= ratedone;
|
|
|
end
|
end
|
|
|
else
|
else
|
|
|
begin
|
begin
|
txratedone <= 1'd0;
|
txratedone <= 1'd0;
|
rxratedone <= 1'd0;
|
rxratedone <= 1'd0;
|
phystatus <= 1'd0;
|
phystatus <= 1'd0;
|
ratedone <= 1'd0;
|
ratedone <= 1'd0;
|
end
|
end
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- PIPE Rate FSM -----------------------------------------------------
|
//---------- PIPE Rate FSM -----------------------------------------------------
|
always @ (posedge RATE_CLK)
|
always @ (posedge RATE_CLK)
|
begin
|
begin
|
|
|
if (!RATE_RST_N)
|
if (!RATE_RST_N)
|
begin
|
begin
|
fsm <= FSM_PLL_LOCK;
|
fsm <= FSM_PLL_LOCK;
|
gen3_exit <= 1'd0;
|
gen3_exit <= 1'd0;
|
cpllpd <= 1'd0;
|
cpllpd <= 1'd0;
|
qpllpd <= 1'd0;
|
qpllpd <= 1'd0;
|
cpllreset <= 1'd0;
|
cpllreset <= 1'd0;
|
qpllreset <= 1'd0;
|
qpllreset <= 1'd0;
|
txpmareset <= 1'd0;
|
txpmareset <= 1'd0;
|
rxpmareset <= 1'd0;
|
rxpmareset <= 1'd0;
|
sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
|
sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
|
pclk_sel <= 1'd0;
|
pclk_sel <= 1'd0;
|
gen3 <= 1'd0;
|
gen3 <= 1'd0;
|
rate_out <= 3'd0;
|
rate_out <= 3'd0;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
case (fsm)
|
case (fsm)
|
|
|
//---------- Idle State ----------------------------
|
//---------- Idle State ----------------------------
|
FSM_IDLE :
|
FSM_IDLE :
|
|
|
begin
|
begin
|
//---------- Detect Rate Change ----------------
|
//---------- Detect Rate Change ----------------
|
if (rate_in_reg2 != rate_in_reg1)
|
if (rate_in_reg2 != rate_in_reg1)
|
begin
|
begin
|
fsm <= ((rate_in_reg2 == 2'd2) || (rate_in_reg1 == 2'd2)) ? FSM_PLL_PU : FSM_TXDATA_WAIT;
|
fsm <= ((rate_in_reg2 == 2'd2) || (rate_in_reg1 == 2'd2)) ? FSM_PLL_PU : FSM_TXDATA_WAIT;
|
gen3_exit <= (rate_in_reg2 == 2'd2);
|
gen3_exit <= (rate_in_reg2 == 2'd2);
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
fsm <= FSM_IDLE;
|
fsm <= FSM_IDLE;
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
end
|
end
|
|
|
//---------- Power-up PLL --------------------------
|
//---------- Power-up PLL --------------------------
|
FSM_PLL_PU :
|
FSM_PLL_PU :
|
|
|
begin
|
begin
|
fsm <= FSM_PLL_PURESET;
|
fsm <= FSM_PLL_PURESET;
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= (PCIE_PLL_SEL == "QPLL");
|
cpllpd <= (PCIE_PLL_SEL == "QPLL");
|
qpllpd <= 1'd0;
|
qpllpd <= 1'd0;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Release PLL Resets --------------------
|
//---------- Release PLL Resets --------------------
|
FSM_PLL_PURESET :
|
FSM_PLL_PURESET :
|
|
|
begin
|
begin
|
fsm <= FSM_PLL_LOCK;
|
fsm <= FSM_PLL_LOCK;
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= (PCIE_PLL_SEL == "QPLL");
|
cpllreset <= (PCIE_PLL_SEL == "QPLL");
|
qpllreset <= 1'd0;
|
qpllreset <= 1'd0;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Wait for PLL Lock ---------------------
|
//---------- Wait for PLL Lock ---------------------
|
FSM_PLL_LOCK :
|
FSM_PLL_LOCK :
|
|
|
begin
|
begin
|
fsm <= (pll_lock ? ((!rst_idle_reg2 || (rate_in_reg2 == 2'd1)) ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_START) : FSM_PLL_LOCK);
|
fsm <= (pll_lock ? ((!rst_idle_reg2 || (rate_in_reg2 == 2'd1)) ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_START) : FSM_PLL_LOCK);
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Start DRP x16 -------------------------
|
//---------- Start DRP x16 -------------------------
|
FSM_DRP_X16_GEN3_START :
|
FSM_DRP_X16_GEN3_START :
|
|
|
begin
|
begin
|
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_GEN3_DONE : FSM_DRP_X16_GEN3_START;
|
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_GEN3_DONE : FSM_DRP_X16_GEN3_START;
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd1;
|
drp_start <= 1'd1;
|
drp_x16x20_mode <= 1'd1;
|
drp_x16x20_mode <= 1'd1;
|
drp_x16 <= 1'd1;
|
drp_x16 <= 1'd1;
|
end
|
end
|
|
|
//---------- Wait for DRP x16 Done -----------------
|
//---------- Wait for DRP x16 Done -----------------
|
FSM_DRP_X16_GEN3_DONE :
|
FSM_DRP_X16_GEN3_DONE :
|
|
|
begin
|
begin
|
fsm <= drp_done_reg2 ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_DONE;
|
fsm <= drp_done_reg2 ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_DONE;
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd1;
|
drp_x16x20_mode <= 1'd1;
|
drp_x16 <= 1'd1;
|
drp_x16 <= 1'd1;
|
end
|
end
|
|
|
//---------- Hold both PMA in Reset ----------------
|
//---------- Hold both PMA in Reset ----------------
|
// Gen1 : Release PMA Reset
|
// Gen1 : Release PMA Reset
|
// Gen2 : Release PMA Reset
|
// Gen2 : Release PMA Reset
|
// Gen3 : Hold PMA Reset
|
// Gen3 : Hold PMA Reset
|
//--------------------------------------------------
|
//--------------------------------------------------
|
FSM_PMARESET_HOLD :
|
FSM_PMARESET_HOLD :
|
|
|
begin
|
begin
|
fsm <= FSM_PLL_SEL;
|
fsm <= FSM_PLL_SEL;
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit);
|
txpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit);
|
rxpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit);
|
rxpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit);
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Select PLL ----------------------------
|
//---------- Select PLL ----------------------------
|
// Gen1 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL
|
// Gen1 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL
|
// Gen2 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL
|
// Gen2 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL
|
// Gen3 : QPLL
|
// Gen3 : QPLL
|
//--------------------------------------------------
|
//--------------------------------------------------
|
FSM_PLL_SEL :
|
FSM_PLL_SEL :
|
|
|
begin
|
begin
|
fsm <= FSM_MMCM_LOCK;
|
fsm <= FSM_MMCM_LOCK;
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= ((rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL")) ? 2'd1 : 2'd0;
|
sysclksel <= ((rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL")) ? 2'd1 : 2'd0;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Check for MMCM Lock -------------------
|
//---------- Check for MMCM Lock -------------------
|
FSM_MMCM_LOCK :
|
FSM_MMCM_LOCK :
|
|
|
begin
|
begin
|
fsm <= (mmcm_lock_reg2 && !rxpmaresetdone_reg2 ? FSM_DRP_START : FSM_MMCM_LOCK);
|
fsm <= (mmcm_lock_reg2 && !rxpmaresetdone_reg2 ? FSM_DRP_START : FSM_MMCM_LOCK);
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Start DRP -----------------------------
|
//---------- Start DRP -----------------------------
|
FSM_DRP_START:
|
FSM_DRP_START:
|
|
|
begin
|
begin
|
fsm <= (!drp_done_reg2 ? FSM_DRP_DONE : FSM_DRP_START);
|
fsm <= (!drp_done_reg2 ? FSM_DRP_DONE : FSM_DRP_START);
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2));
|
pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2));
|
gen3 <= (rate_in_reg2 == 2'd2);
|
gen3 <= (rate_in_reg2 == 2'd2);
|
rate_out <= (((rate_in_reg2 == 2'd2) || gen3_exit) ? rate : rate_out);
|
rate_out <= (((rate_in_reg2 == 2'd2) || gen3_exit) ? rate : rate_out);
|
drp_start <= 1'd1;
|
drp_start <= 1'd1;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Wait for DRP Done ---------------------
|
//---------- Wait for DRP Done ---------------------
|
FSM_DRP_DONE :
|
FSM_DRP_DONE :
|
|
|
begin
|
begin
|
fsm <= ((drp_done_reg2 && pll_lock) ? (rst_idle_reg2 ? FSM_PMARESET_RELEASE : FSM_IDLE): FSM_DRP_DONE);
|
fsm <= ((drp_done_reg2 && pll_lock) ? (rst_idle_reg2 ? FSM_PMARESET_RELEASE : FSM_IDLE): FSM_DRP_DONE);
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Release PMA Resets --------------------
|
//---------- Release PMA Resets --------------------
|
FSM_PMARESET_RELEASE :
|
FSM_PMARESET_RELEASE :
|
|
|
begin
|
begin
|
fsm <= FSM_PMARESET_DONE;
|
fsm <= FSM_PMARESET_DONE;
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= 1'd0;
|
txpmareset <= 1'd0;
|
rxpmareset <= 1'd0;
|
rxpmareset <= 1'd0;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Wait for both TX/RX PMA Reset Dones and PHYSTATUS Deassertion
|
//---------- Wait for both TX/RX PMA Reset Dones and PHYSTATUS Deassertion
|
FSM_PMARESET_DONE :
|
FSM_PMARESET_DONE :
|
|
|
begin
|
begin
|
fsm <= (((rxresetdone_reg2 && txresetdone_reg2 && !phystatus_reg2) || !RATE_ACTIVE_LANE) ? FSM_TXDATA_WAIT : FSM_PMARESET_DONE);
|
fsm <= (((rxresetdone_reg2 && txresetdone_reg2 && !phystatus_reg2) || !RATE_ACTIVE_LANE) ? FSM_TXDATA_WAIT : FSM_PMARESET_DONE);
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Wait for TXDATA to TX[P/N] Latency ----
|
//---------- Wait for TXDATA to TX[P/N] Latency ----
|
FSM_TXDATA_WAIT :
|
FSM_TXDATA_WAIT :
|
|
|
begin
|
begin
|
fsm <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT;
|
fsm <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT;
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Select PCLK Frequency -----------------
|
//---------- Select PCLK Frequency -----------------
|
// Gen1 : PCLK = 125 MHz
|
// Gen1 : PCLK = 125 MHz
|
// Gen2 : PCLK = 250 MHz
|
// Gen2 : PCLK = 250 MHz
|
// Gen3 : PCLK = 250 MHz
|
// Gen3 : PCLK = 250 MHz
|
//--------------------------------------------------
|
//--------------------------------------------------
|
FSM_PCLK_SEL :
|
FSM_PCLK_SEL :
|
|
|
begin
|
begin
|
fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_DRP_X16_START : FSM_RATE_SEL;
|
fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_DRP_X16_START : FSM_RATE_SEL;
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2));
|
pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2));
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Start DRP x16 -------------------------
|
//---------- Start DRP x16 -------------------------
|
FSM_DRP_X16_START :
|
FSM_DRP_X16_START :
|
|
|
begin
|
begin
|
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
|
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd1;
|
drp_start <= 1'd1;
|
drp_x16x20_mode <= 1'd1;
|
drp_x16x20_mode <= 1'd1;
|
drp_x16 <= 1'd1;
|
drp_x16 <= 1'd1;
|
end
|
end
|
|
|
//---------- Wait for DRP x16 Done -----------------
|
//---------- Wait for DRP x16 Done -----------------
|
FSM_DRP_X16_DONE :
|
FSM_DRP_X16_DONE :
|
|
|
begin
|
begin
|
fsm <= drp_done_reg2 ? FSM_RATE_SEL : FSM_DRP_X16_DONE;
|
fsm <= drp_done_reg2 ? FSM_RATE_SEL : FSM_DRP_X16_DONE;
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd1;
|
drp_x16x20_mode <= 1'd1;
|
drp_x16 <= 1'd1;
|
drp_x16 <= 1'd1;
|
end
|
end
|
|
|
//---------- Select Rate ---------------------------
|
//---------- Select Rate ---------------------------
|
FSM_RATE_SEL :
|
FSM_RATE_SEL :
|
|
|
begin
|
begin
|
fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_RXPMARESETDONE : FSM_RATE_DONE;
|
fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_RXPMARESETDONE : FSM_RATE_DONE;
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate; // Update [TX/RX]RATE
|
rate_out <= rate; // Update [TX/RX]RATE
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Wait for RXPMARESETDONE De-assertion --
|
//---------- Wait for RXPMARESETDONE De-assertion --
|
FSM_RXPMARESETDONE :
|
FSM_RXPMARESETDONE :
|
|
|
begin
|
begin
|
fsm <= (!rxpmaresetdone_reg2) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE;
|
fsm <= (!rxpmaresetdone_reg2) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE;
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Start DRP x20 -------------------------
|
//---------- Start DRP x20 -------------------------
|
FSM_DRP_X20_START :
|
FSM_DRP_X20_START :
|
|
|
begin
|
begin
|
fsm <= (!drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
|
fsm <= (!drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd1;
|
drp_start <= 1'd1;
|
drp_x16x20_mode <= 1'd1;
|
drp_x16x20_mode <= 1'd1;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Wait for DRP x20 Done -----------------
|
//---------- Wait for DRP x20 Done -----------------
|
FSM_DRP_X20_DONE :
|
FSM_DRP_X20_DONE :
|
|
|
begin
|
begin
|
fsm <= drp_done_reg2 ? FSM_RATE_DONE : FSM_DRP_X20_DONE;
|
fsm <= drp_done_reg2 ? FSM_RATE_DONE : FSM_DRP_X20_DONE;
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd1;
|
drp_x16x20_mode <= 1'd1;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Wait for Rate Change Done -------------
|
//---------- Wait for Rate Change Done -------------
|
FSM_RATE_DONE :
|
FSM_RATE_DONE :
|
|
|
begin
|
begin
|
if (ratedone || (rate_in_reg2 == 2'd2) || (gen3_exit) || !RATE_ACTIVE_LANE)
|
if (ratedone || (rate_in_reg2 == 2'd2) || (gen3_exit) || !RATE_ACTIVE_LANE)
|
if ((PCIE_USE_MODE == "1.0") && (rate_in_reg2 != 2'd2) && (!gen3_exit))
|
if ((PCIE_USE_MODE == "1.0") && (rate_in_reg2 != 2'd2) && (!gen3_exit))
|
fsm <= FSM_RESETOVRD_START;
|
fsm <= FSM_RESETOVRD_START;
|
else
|
else
|
fsm <= FSM_PLL_PDRESET;
|
fsm <= FSM_PLL_PDRESET;
|
else
|
else
|
fsm <= FSM_RATE_DONE;
|
fsm <= FSM_RATE_DONE;
|
|
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Reset Override Start ------------------
|
//---------- Reset Override Start ------------------
|
FSM_RESETOVRD_START:
|
FSM_RESETOVRD_START:
|
|
|
begin
|
begin
|
fsm <= (!resetovrd_done_reg2 ? FSM_RESETOVRD_DONE : FSM_RESETOVRD_START);
|
fsm <= (!resetovrd_done_reg2 ? FSM_RESETOVRD_DONE : FSM_RESETOVRD_START);
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Reset Override Done -------------------
|
//---------- Reset Override Done -------------------
|
FSM_RESETOVRD_DONE :
|
FSM_RESETOVRD_DONE :
|
|
|
begin
|
begin
|
fsm <= (resetovrd_done_reg2 ? FSM_PLL_PDRESET : FSM_RESETOVRD_DONE);
|
fsm <= (resetovrd_done_reg2 ? FSM_PLL_PDRESET : FSM_RESETOVRD_DONE);
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Hold PLL Not Used in Reset ------------
|
//---------- Hold PLL Not Used in Reset ------------
|
FSM_PLL_PDRESET :
|
FSM_PLL_PDRESET :
|
|
|
begin
|
begin
|
fsm <= FSM_PLL_PD;
|
fsm <= FSM_PLL_PD;
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2);
|
cpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2);
|
qpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2);
|
qpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2);
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Power-Down PLL Not Used ---------------
|
//---------- Power-Down PLL Not Used ---------------
|
FSM_PLL_PD :
|
FSM_PLL_PD :
|
|
|
begin
|
begin
|
fsm <= (((rate_in_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? FSM_TXSYNC_START : FSM_DONE);
|
fsm <= (((rate_in_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? FSM_TXSYNC_START : FSM_DONE);
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2);
|
cpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2);
|
qpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2);
|
qpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2);
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Start TX Sync -------------------------
|
//---------- Start TX Sync -------------------------
|
FSM_TXSYNC_START:
|
FSM_TXSYNC_START:
|
|
|
begin
|
begin
|
fsm <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
|
fsm <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Wait for TX Sync Done -----------------
|
//---------- Wait for TX Sync Done -----------------
|
FSM_TXSYNC_DONE:
|
FSM_TXSYNC_DONE:
|
|
|
begin
|
begin
|
fsm <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE);
|
fsm <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE);
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Rate Change Done ----------------------
|
//---------- Rate Change Done ----------------------
|
FSM_DONE :
|
FSM_DONE :
|
|
|
begin
|
begin
|
fsm <= (((rate_in_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE") && (PCIE_ASYNC_EN == "TRUE")) ? FSM_RXSYNC_START : FSM_IDLE);
|
fsm <= (((rate_in_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE") && (PCIE_ASYNC_EN == "TRUE")) ? FSM_RXSYNC_START : FSM_IDLE);
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Start RX Sync -------------------------
|
//---------- Start RX Sync -------------------------
|
FSM_RXSYNC_START:
|
FSM_RXSYNC_START:
|
|
|
begin
|
begin
|
fsm <= (!rxsync_done_reg2 ? FSM_RXSYNC_DONE : FSM_RXSYNC_START);
|
fsm <= (!rxsync_done_reg2 ? FSM_RXSYNC_DONE : FSM_RXSYNC_START);
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Wait for RX Sync Done -----------------
|
//---------- Wait for RX Sync Done -----------------
|
FSM_RXSYNC_DONE:
|
FSM_RXSYNC_DONE:
|
|
|
begin
|
begin
|
fsm <= (rxsync_done_reg2 ? FSM_IDLE : FSM_RXSYNC_DONE);
|
fsm <= (rxsync_done_reg2 ? FSM_IDLE : FSM_RXSYNC_DONE);
|
gen3_exit <= gen3_exit;
|
gen3_exit <= gen3_exit;
|
cpllpd <= cpllpd;
|
cpllpd <= cpllpd;
|
qpllpd <= qpllpd;
|
qpllpd <= qpllpd;
|
cpllreset <= cpllreset;
|
cpllreset <= cpllreset;
|
qpllreset <= qpllreset;
|
qpllreset <= qpllreset;
|
txpmareset <= txpmareset;
|
txpmareset <= txpmareset;
|
rxpmareset <= rxpmareset;
|
rxpmareset <= rxpmareset;
|
sysclksel <= sysclksel;
|
sysclksel <= sysclksel;
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
gen3 <= gen3;
|
gen3 <= gen3;
|
rate_out <= rate_out;
|
rate_out <= rate_out;
|
drp_start <= 1'd0;
|
drp_start <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16x20_mode <= 1'd0;
|
drp_x16 <= 1'd0;
|
drp_x16 <= 1'd0;
|
end
|
end
|
|
|
//---------- Default State -------------------------
|
//---------- Default State -------------------------
|
default :
|
default :
|
|
|
begin
|
begin
|
fsm <= FSM_IDLE;
|
fsm <= FSM_IDLE;
|
gen3_exit <= 1'd0;
|
gen3_exit <= 1'd0;
|
cpllpd <= 1'd0;
|
cpllpd <= 1'd0;
|
qpllpd <= 1'd0;
|
qpllpd <= 1'd0;
|
cpllreset <= 1'd0;
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cpllreset <= 1'd0;
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qpllreset <= 1'd0;
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qpllreset <= 1'd0;
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txpmareset <= 1'd0;
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txpmareset <= 1'd0;
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rxpmareset <= 1'd0;
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rxpmareset <= 1'd0;
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sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
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sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
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pclk_sel <= 1'd0;
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pclk_sel <= 1'd0;
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gen3 <= 1'd0;
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gen3 <= 1'd0;
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rate_out <= 3'd0;
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rate_out <= 3'd0;
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drp_start <= 1'd0;
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drp_start <= 1'd0;
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drp_x16x20_mode <= 1'd0;
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drp_x16x20_mode <= 1'd0;
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drp_x16 <= 1'd0;
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drp_x16 <= 1'd0;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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//---------- PIPE Rate Output --------------------------------------------------
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//---------- PIPE Rate Output --------------------------------------------------
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assign RATE_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd);
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assign RATE_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd);
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assign RATE_QPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd);
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assign RATE_QPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd);
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assign RATE_CPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllreset);
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assign RATE_CPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllreset);
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assign RATE_QPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllreset);
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assign RATE_QPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllreset);
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assign RATE_TXPMARESET = txpmareset;
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assign RATE_TXPMARESET = txpmareset;
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assign RATE_RXPMARESET = rxpmareset;
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assign RATE_RXPMARESET = rxpmareset;
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assign RATE_SYSCLKSEL = sysclksel;
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assign RATE_SYSCLKSEL = sysclksel;
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//assign RATE_DRP_START = (fsm == FSM_DRP_START) || (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
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//assign RATE_DRP_START = (fsm == FSM_DRP_START) || (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
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assign RATE_DRP_START = drp_start;
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assign RATE_DRP_START = drp_start;
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//assign RATE_DRP_X16X20_MODE = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) ||
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//assign RATE_DRP_X16X20_MODE = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) ||
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// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) ||
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// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) ||
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// (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE);
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// (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE);
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assign RATE_DRP_X16X20_MODE = drp_x16x20_mode;
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assign RATE_DRP_X16X20_MODE = drp_x16x20_mode;
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|
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//assign RATE_DRP_X16 = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) ||
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//assign RATE_DRP_X16 = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) ||
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// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
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// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
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assign RATE_DRP_X16 = drp_x16;
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assign RATE_DRP_X16 = drp_x16;
|
|
|
assign RATE_PCLK_SEL = pclk_sel;
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assign RATE_PCLK_SEL = pclk_sel;
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assign RATE_GEN3 = gen3;
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assign RATE_GEN3 = gen3;
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assign RATE_RATE_OUT = rate_out;
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assign RATE_RATE_OUT = rate_out;
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assign RATE_RESETOVRD_START = (fsm == FSM_RESETOVRD_START);
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assign RATE_RESETOVRD_START = (fsm == FSM_RESETOVRD_START);
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assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START);
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assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START);
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assign RATE_DONE = (fsm == FSM_DONE);
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assign RATE_DONE = (fsm == FSM_DONE);
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assign RATE_RXSYNC_START = (fsm == FSM_RXSYNC_START);
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assign RATE_RXSYNC_START = (fsm == FSM_RXSYNC_START);
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assign RATE_RXSYNC = ((fsm == FSM_RXSYNC_START) || (fsm == FSM_RXSYNC_DONE));
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assign RATE_RXSYNC = ((fsm == FSM_RXSYNC_START) || (fsm == FSM_RXSYNC_DONE));
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assign RATE_IDLE = (fsm == FSM_IDLE);
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assign RATE_IDLE = (fsm == FSM_IDLE);
|
assign RATE_FSM = fsm;
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assign RATE_FSM = fsm;
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|
|
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endmodule
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endmodule
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