//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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//
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// This file contains confidential and proprietary information
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// international copyright and other intellectual property
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// laws.
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// laws.
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//
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//
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// DISCLAIMER
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// CRITICAL APPLICATIONS
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_pipe_sync.v
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// File : cl_a7pcie_x4_pipe_sync.v
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// Version : 1.10
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// Version : 1.11
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Filename : pipe_sync.v
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// Filename : pipe_sync.v
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// Description : PIPE Sync Module for 7 Series Transceiver
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// Description : PIPE Sync Module for 7 Series Transceiver
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// Version : 20.1
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// Version : 20.1
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default).
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// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default).
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// : 1 = Auto TX sync.
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// : 1 = Auto TX sync.
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// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default).
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// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default).
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// : 1 = Auto RX sync.
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// : 1 = Auto RX sync.
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//---------- PIPE Sync Module --------------------------------------------------
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//---------- PIPE Sync Module --------------------------------------------------
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module cl_a7pcie_x4_pipe_sync #
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module cl_a7pcie_x4_pipe_sync #
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(
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(
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parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
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parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
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parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
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parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
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parameter PCIE_RXBUF_EN = "TRUE", // PCIe TX buffer enable for Gen3 only
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parameter PCIE_RXBUF_EN = "TRUE", // PCIe TX buffer enable for Gen3 only
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parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
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parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
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parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
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parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
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parameter PCIE_LANE = 1, // PCIe lane
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parameter PCIE_LANE = 1, // PCIe lane
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parameter PCIE_LINK_SPEED = 3, // PCIe link speed
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parameter PCIE_LINK_SPEED = 3, // PCIe link speed
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parameter BYPASS_TXDELAY_ALIGN = 0, // Bypass TX delay align
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parameter BYPASS_TXDELAY_ALIGN = 0, // Bypass TX delay align
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parameter BYPASS_RXDELAY_ALIGN = 0 // Bypass RX delay align
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parameter BYPASS_RXDELAY_ALIGN = 0 // Bypass RX delay align
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)
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)
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(
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(
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//---------- Input -------------------------------------
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//---------- Input -------------------------------------
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input SYNC_CLK,
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input SYNC_CLK,
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input SYNC_RST_N,
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input SYNC_RST_N,
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input SYNC_SLAVE,
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input SYNC_SLAVE,
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input SYNC_GEN3,
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input SYNC_GEN3,
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input SYNC_RATE_IDLE,
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input SYNC_RATE_IDLE,
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input SYNC_MMCM_LOCK,
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input SYNC_MMCM_LOCK,
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input SYNC_RXELECIDLE,
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input SYNC_RXELECIDLE,
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input SYNC_RXCDRLOCK,
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input SYNC_RXCDRLOCK,
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input SYNC_ACTIVE_LANE,
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input SYNC_ACTIVE_LANE,
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input SYNC_TXSYNC_START,
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input SYNC_TXSYNC_START,
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input SYNC_TXPHINITDONE,
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input SYNC_TXPHINITDONE,
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input SYNC_TXDLYSRESETDONE,
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input SYNC_TXDLYSRESETDONE,
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input SYNC_TXPHALIGNDONE,
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input SYNC_TXPHALIGNDONE,
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input SYNC_TXSYNCDONE,
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input SYNC_TXSYNCDONE,
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input SYNC_RXSYNC_START,
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input SYNC_RXSYNC_START,
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input SYNC_RXDLYSRESETDONE,
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input SYNC_RXDLYSRESETDONE,
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input SYNC_RXPHALIGNDONE_M,
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input SYNC_RXPHALIGNDONE_M,
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input SYNC_RXPHALIGNDONE_S,
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input SYNC_RXPHALIGNDONE_S,
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input SYNC_RXSYNC_DONEM_IN,
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input SYNC_RXSYNC_DONEM_IN,
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input SYNC_RXSYNCDONE,
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input SYNC_RXSYNCDONE,
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//---------- Output ------------------------------------
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//---------- Output ------------------------------------
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output SYNC_TXPHDLYRESET,
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output SYNC_TXPHDLYRESET,
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output SYNC_TXPHALIGN,
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output SYNC_TXPHALIGN,
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output SYNC_TXPHALIGNEN,
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output SYNC_TXPHALIGNEN,
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output SYNC_TXPHINIT,
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output SYNC_TXPHINIT,
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output SYNC_TXDLYBYPASS,
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output SYNC_TXDLYBYPASS,
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output SYNC_TXDLYSRESET,
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output SYNC_TXDLYSRESET,
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output SYNC_TXDLYEN,
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output SYNC_TXDLYEN,
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output SYNC_TXSYNC_DONE,
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output SYNC_TXSYNC_DONE,
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output [ 5:0] SYNC_FSM_TX,
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output [ 5:0] SYNC_FSM_TX,
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output SYNC_RXPHALIGN,
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output SYNC_RXPHALIGN,
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output SYNC_RXPHALIGNEN,
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output SYNC_RXPHALIGNEN,
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output SYNC_RXDLYBYPASS,
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output SYNC_RXDLYBYPASS,
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output SYNC_RXDLYSRESET,
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output SYNC_RXDLYSRESET,
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output SYNC_RXDLYEN,
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output SYNC_RXDLYEN,
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output SYNC_RXDDIEN,
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output SYNC_RXDDIEN,
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output SYNC_RXSYNC_DONEM_OUT,
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output SYNC_RXSYNC_DONEM_OUT,
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output SYNC_RXSYNC_DONE,
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output SYNC_RXSYNC_DONE,
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output [ 6:0] SYNC_FSM_RX
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output [ 6:0] SYNC_FSM_RX
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);
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);
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//---------- Input Register ----------------------------
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//---------- Input Register ----------------------------
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg3;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg3;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg3;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg3;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg3;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg3;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg3;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg3;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg3;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg3;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg2;
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//---------- Output Register ---------------------------
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//---------- Output Register ---------------------------
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reg txdlyen = 1'd0;
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reg txdlyen = 1'd0;
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reg txsync_done = 1'd0;
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reg txsync_done = 1'd0;
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reg [ 5:0] fsm_tx = 6'd0;
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reg [ 5:0] fsm_tx = 6'd0;
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reg rxdlyen = 1'd0;
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reg rxdlyen = 1'd0;
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reg rxsync_done = 1'd0;
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reg rxsync_done = 1'd0;
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reg [ 6:0] fsm_rx = 7'd0;
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reg [ 6:0] fsm_rx = 7'd0;
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//---------- FSM ---------------------------------------
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//---------- FSM ---------------------------------------
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localparam FSM_TXSYNC_IDLE = 6'b000001;
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localparam FSM_TXSYNC_IDLE = 6'b000001;
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localparam FSM_MMCM_LOCK = 6'b000010;
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localparam FSM_MMCM_LOCK = 6'b000010;
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localparam FSM_TXSYNC_START = 6'b000100;
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localparam FSM_TXSYNC_START = 6'b000100;
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localparam FSM_TXPHINITDONE = 6'b001000; // Manual TX sync only
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localparam FSM_TXPHINITDONE = 6'b001000; // Manual TX sync only
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localparam FSM_TXSYNC_DONE1 = 6'b010000;
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localparam FSM_TXSYNC_DONE1 = 6'b010000;
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localparam FSM_TXSYNC_DONE2 = 6'b100000;
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localparam FSM_TXSYNC_DONE2 = 6'b100000;
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localparam FSM_RXSYNC_IDLE = 7'b0000001;
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localparam FSM_RXSYNC_IDLE = 7'b0000001;
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localparam FSM_RXCDRLOCK = 7'b0000010;
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localparam FSM_RXCDRLOCK = 7'b0000010;
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localparam FSM_RXSYNC_START = 7'b0000100;
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localparam FSM_RXSYNC_START = 7'b0000100;
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localparam FSM_RXSYNC_DONE1 = 7'b0001000;
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localparam FSM_RXSYNC_DONE1 = 7'b0001000;
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localparam FSM_RXSYNC_DONE2 = 7'b0010000;
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localparam FSM_RXSYNC_DONE2 = 7'b0010000;
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localparam FSM_RXSYNC_DONES = 7'b0100000;
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localparam FSM_RXSYNC_DONES = 7'b0100000;
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localparam FSM_RXSYNC_DONEM = 7'b1000000;
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localparam FSM_RXSYNC_DONEM = 7'b1000000;
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//---------- Input FF ----------------------------------------------------------
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//---------- Input FF ----------------------------------------------------------
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always @ (posedge SYNC_CLK)
|
always @ (posedge SYNC_CLK)
|
begin
|
begin
|
|
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if (!SYNC_RST_N)
|
if (!SYNC_RST_N)
|
begin
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begin
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//---------- 1st Stage FF --------------------------
|
//---------- 1st Stage FF --------------------------
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gen3_reg1 <= 1'd0;
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gen3_reg1 <= 1'd0;
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rate_idle_reg1 <= 1'd0;
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rate_idle_reg1 <= 1'd0;
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mmcm_lock_reg1 <= 1'd0;
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mmcm_lock_reg1 <= 1'd0;
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rxelecidle_reg1 <= 1'd0;
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rxelecidle_reg1 <= 1'd0;
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rxcdrlock_reg1 <= 1'd0;
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rxcdrlock_reg1 <= 1'd0;
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|
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txsync_start_reg1 <= 1'd0;
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txsync_start_reg1 <= 1'd0;
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txphinitdone_reg1 <= 1'd0;
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txphinitdone_reg1 <= 1'd0;
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txdlysresetdone_reg1 <= 1'd0;
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txdlysresetdone_reg1 <= 1'd0;
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txphaligndone_reg1 <= 1'd0;
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txphaligndone_reg1 <= 1'd0;
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txsyncdone_reg1 <= 1'd0;
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txsyncdone_reg1 <= 1'd0;
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|
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rxsync_start_reg1 <= 1'd0;
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rxsync_start_reg1 <= 1'd0;
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rxdlysresetdone_reg1 <= 1'd0;
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rxdlysresetdone_reg1 <= 1'd0;
|
rxphaligndone_m_reg1 <= 1'd0;
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rxphaligndone_m_reg1 <= 1'd0;
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rxphaligndone_s_reg1 <= 1'd0;
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rxphaligndone_s_reg1 <= 1'd0;
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rxsync_donem_reg1 <= 1'd0;
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rxsync_donem_reg1 <= 1'd0;
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rxsyncdone_reg1 <= 1'd0;
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rxsyncdone_reg1 <= 1'd0;
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//---------- 2nd Stage FF --------------------------
|
//---------- 2nd Stage FF --------------------------
|
gen3_reg2 <= 1'd0;
|
gen3_reg2 <= 1'd0;
|
rate_idle_reg2 <= 1'd0;
|
rate_idle_reg2 <= 1'd0;
|
mmcm_lock_reg2 <= 1'd0;
|
mmcm_lock_reg2 <= 1'd0;
|
rxelecidle_reg2 <= 1'd0;
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rxelecidle_reg2 <= 1'd0;
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rxcdrlock_reg2 <= 1'd0;
|
rxcdrlock_reg2 <= 1'd0;
|
|
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txsync_start_reg2 <= 1'd0;
|
txsync_start_reg2 <= 1'd0;
|
txphinitdone_reg2 <= 1'd0;
|
txphinitdone_reg2 <= 1'd0;
|
txdlysresetdone_reg2 <= 1'd0;
|
txdlysresetdone_reg2 <= 1'd0;
|
txphaligndone_reg2 <= 1'd0;
|
txphaligndone_reg2 <= 1'd0;
|
txsyncdone_reg2 <= 1'd0;
|
txsyncdone_reg2 <= 1'd0;
|
|
|
rxsync_start_reg2 <= 1'd0;
|
rxsync_start_reg2 <= 1'd0;
|
rxdlysresetdone_reg2 <= 1'd0;
|
rxdlysresetdone_reg2 <= 1'd0;
|
rxphaligndone_m_reg2 <= 1'd0;
|
rxphaligndone_m_reg2 <= 1'd0;
|
rxphaligndone_s_reg2 <= 1'd0;
|
rxphaligndone_s_reg2 <= 1'd0;
|
rxsync_donem_reg2 <= 1'd0;
|
rxsync_donem_reg2 <= 1'd0;
|
rxsyncdone_reg2 <= 1'd0;
|
rxsyncdone_reg2 <= 1'd0;
|
//---------- 3rd Stage FF --------------------------
|
//---------- 3rd Stage FF --------------------------
|
txsync_start_reg3 <= 1'd0;
|
txsync_start_reg3 <= 1'd0;
|
txphinitdone_reg3 <= 1'd0;
|
txphinitdone_reg3 <= 1'd0;
|
txdlysresetdone_reg3 <= 1'd0;
|
txdlysresetdone_reg3 <= 1'd0;
|
txphaligndone_reg3 <= 1'd0;
|
txphaligndone_reg3 <= 1'd0;
|
txsyncdone_reg3 <= 1'd0;
|
txsyncdone_reg3 <= 1'd0;
|
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
//---------- 1st Stage FF --------------------------
|
//---------- 1st Stage FF --------------------------
|
gen3_reg1 <= SYNC_GEN3;
|
gen3_reg1 <= SYNC_GEN3;
|
rate_idle_reg1 <= SYNC_RATE_IDLE;
|
rate_idle_reg1 <= SYNC_RATE_IDLE;
|
mmcm_lock_reg1 <= SYNC_MMCM_LOCK;
|
mmcm_lock_reg1 <= SYNC_MMCM_LOCK;
|
rxelecidle_reg1 <= SYNC_RXELECIDLE;
|
rxelecidle_reg1 <= SYNC_RXELECIDLE;
|
rxcdrlock_reg1 <= SYNC_RXCDRLOCK;
|
rxcdrlock_reg1 <= SYNC_RXCDRLOCK;
|
|
|
txsync_start_reg1 <= SYNC_TXSYNC_START;
|
txsync_start_reg1 <= SYNC_TXSYNC_START;
|
txphinitdone_reg1 <= SYNC_TXPHINITDONE;
|
txphinitdone_reg1 <= SYNC_TXPHINITDONE;
|
txdlysresetdone_reg1 <= SYNC_TXDLYSRESETDONE;
|
txdlysresetdone_reg1 <= SYNC_TXDLYSRESETDONE;
|
txphaligndone_reg1 <= SYNC_TXPHALIGNDONE;
|
txphaligndone_reg1 <= SYNC_TXPHALIGNDONE;
|
txsyncdone_reg1 <= SYNC_TXSYNCDONE;
|
txsyncdone_reg1 <= SYNC_TXSYNCDONE;
|
|
|
rxsync_start_reg1 <= SYNC_RXSYNC_START;
|
rxsync_start_reg1 <= SYNC_RXSYNC_START;
|
rxdlysresetdone_reg1 <= SYNC_RXDLYSRESETDONE;
|
rxdlysresetdone_reg1 <= SYNC_RXDLYSRESETDONE;
|
rxphaligndone_m_reg1 <= SYNC_RXPHALIGNDONE_M;
|
rxphaligndone_m_reg1 <= SYNC_RXPHALIGNDONE_M;
|
rxphaligndone_s_reg1 <= SYNC_RXPHALIGNDONE_S;
|
rxphaligndone_s_reg1 <= SYNC_RXPHALIGNDONE_S;
|
rxsync_donem_reg1 <= SYNC_RXSYNC_DONEM_IN;
|
rxsync_donem_reg1 <= SYNC_RXSYNC_DONEM_IN;
|
rxsyncdone_reg1 <= SYNC_RXSYNCDONE;
|
rxsyncdone_reg1 <= SYNC_RXSYNCDONE;
|
//---------- 2nd Stage FF --------------------------
|
//---------- 2nd Stage FF --------------------------
|
gen3_reg2 <= gen3_reg1;
|
gen3_reg2 <= gen3_reg1;
|
rate_idle_reg2 <= rate_idle_reg1;
|
rate_idle_reg2 <= rate_idle_reg1;
|
mmcm_lock_reg2 <= mmcm_lock_reg1;
|
mmcm_lock_reg2 <= mmcm_lock_reg1;
|
rxelecidle_reg2 <= rxelecidle_reg1;
|
rxelecidle_reg2 <= rxelecidle_reg1;
|
rxcdrlock_reg2 <= rxcdrlock_reg1;
|
rxcdrlock_reg2 <= rxcdrlock_reg1;
|
|
|
txsync_start_reg2 <= txsync_start_reg1;
|
txsync_start_reg2 <= txsync_start_reg1;
|
txphinitdone_reg2 <= txphinitdone_reg1;
|
txphinitdone_reg2 <= txphinitdone_reg1;
|
txdlysresetdone_reg2 <= txdlysresetdone_reg1;
|
txdlysresetdone_reg2 <= txdlysresetdone_reg1;
|
txphaligndone_reg2 <= txphaligndone_reg1;
|
txphaligndone_reg2 <= txphaligndone_reg1;
|
txsyncdone_reg2 <= txsyncdone_reg1;
|
txsyncdone_reg2 <= txsyncdone_reg1;
|
|
|
rxsync_start_reg2 <= rxsync_start_reg1;
|
rxsync_start_reg2 <= rxsync_start_reg1;
|
rxdlysresetdone_reg2 <= rxdlysresetdone_reg1;
|
rxdlysresetdone_reg2 <= rxdlysresetdone_reg1;
|
rxphaligndone_m_reg2 <= rxphaligndone_m_reg1;
|
rxphaligndone_m_reg2 <= rxphaligndone_m_reg1;
|
rxphaligndone_s_reg2 <= rxphaligndone_s_reg1;
|
rxphaligndone_s_reg2 <= rxphaligndone_s_reg1;
|
rxsync_donem_reg2 <= rxsync_donem_reg1;
|
rxsync_donem_reg2 <= rxsync_donem_reg1;
|
rxsyncdone_reg2 <= rxsyncdone_reg1;
|
rxsyncdone_reg2 <= rxsyncdone_reg1;
|
//---------- 3rd Stage FF --------------------------
|
//---------- 3rd Stage FF --------------------------
|
txsync_start_reg3 <= txsync_start_reg2;
|
txsync_start_reg3 <= txsync_start_reg2;
|
txphinitdone_reg3 <= txphinitdone_reg2;
|
txphinitdone_reg3 <= txphinitdone_reg2;
|
txdlysresetdone_reg3 <= txdlysresetdone_reg2;
|
txdlysresetdone_reg3 <= txdlysresetdone_reg2;
|
txphaligndone_reg3 <= txphaligndone_reg2;
|
txphaligndone_reg3 <= txphaligndone_reg2;
|
txsyncdone_reg3 <= txsyncdone_reg2;
|
txsyncdone_reg3 <= txsyncdone_reg2;
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- Generate TX Sync FSM ----------------------------------------------
|
//---------- Generate TX Sync FSM ----------------------------------------------
|
generate if ((PCIE_LINK_SPEED == 3) || (PCIE_TXBUF_EN == "FALSE"))
|
generate if ((PCIE_LINK_SPEED == 3) || (PCIE_TXBUF_EN == "FALSE"))
|
|
|
begin : txsync_fsm
|
begin : txsync_fsm
|
|
|
//---------- PIPE TX Sync FSM ----------------------------------------------
|
//---------- PIPE TX Sync FSM ----------------------------------------------
|
always @ (posedge SYNC_CLK)
|
always @ (posedge SYNC_CLK)
|
begin
|
begin
|
|
|
if (!SYNC_RST_N)
|
if (!SYNC_RST_N)
|
begin
|
begin
|
fsm_tx <= FSM_TXSYNC_IDLE;
|
fsm_tx <= FSM_TXSYNC_IDLE;
|
txdlyen <= 1'd0;
|
txdlyen <= 1'd0;
|
txsync_done <= 1'd0;
|
txsync_done <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
case (fsm_tx)
|
case (fsm_tx)
|
|
|
//---------- Idle State ------------------------
|
//---------- Idle State ------------------------
|
FSM_TXSYNC_IDLE :
|
FSM_TXSYNC_IDLE :
|
|
|
begin
|
begin
|
//---------- Exiting Reset or Rate Change --
|
//---------- Exiting Reset or Rate Change --
|
if (txsync_start_reg2)
|
if (txsync_start_reg2)
|
begin
|
begin
|
fsm_tx <= FSM_MMCM_LOCK;
|
fsm_tx <= FSM_MMCM_LOCK;
|
txdlyen <= 1'd0;
|
txdlyen <= 1'd0;
|
txsync_done <= 1'd0;
|
txsync_done <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
fsm_tx <= FSM_TXSYNC_IDLE;
|
fsm_tx <= FSM_TXSYNC_IDLE;
|
txdlyen <= txdlyen;
|
txdlyen <= txdlyen;
|
txsync_done <= txsync_done;
|
txsync_done <= txsync_done;
|
end
|
end
|
end
|
end
|
|
|
//---------- Check MMCM Lock -------------------
|
//---------- Check MMCM Lock -------------------
|
FSM_MMCM_LOCK :
|
FSM_MMCM_LOCK :
|
|
|
begin
|
begin
|
fsm_tx <= (mmcm_lock_reg2 ? FSM_TXSYNC_START : FSM_MMCM_LOCK);
|
fsm_tx <= (mmcm_lock_reg2 ? FSM_TXSYNC_START : FSM_MMCM_LOCK);
|
txdlyen <= 1'd0;
|
txdlyen <= 1'd0;
|
txsync_done <= 1'd0;
|
txsync_done <= 1'd0;
|
end
|
end
|
|
|
//---------- TX Delay Soft Reset ---------------
|
//---------- TX Delay Soft Reset ---------------
|
FSM_TXSYNC_START :
|
FSM_TXSYNC_START :
|
|
|
begin
|
begin
|
fsm_tx <= (((!txdlysresetdone_reg3 && txdlysresetdone_reg2) || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE)) ? FSM_TXPHINITDONE : FSM_TXSYNC_START);
|
fsm_tx <= (((!txdlysresetdone_reg3 && txdlysresetdone_reg2) || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE)) ? FSM_TXPHINITDONE : FSM_TXSYNC_START);
|
txdlyen <= 1'd0;
|
txdlyen <= 1'd0;
|
txsync_done <= 1'd0;
|
txsync_done <= 1'd0;
|
end
|
end
|
|
|
//---------- Wait for TX Phase Init Done (Manual Mode Only)
|
//---------- Wait for TX Phase Init Done (Manual Mode Only)
|
FSM_TXPHINITDONE :
|
FSM_TXPHINITDONE :
|
|
|
begin
|
begin
|
fsm_tx <= (((!txphinitdone_reg3 && txphinitdone_reg2) || (PCIE_TXSYNC_MODE == 1) || (!SYNC_ACTIVE_LANE)) ? FSM_TXSYNC_DONE1 : FSM_TXPHINITDONE);
|
fsm_tx <= (((!txphinitdone_reg3 && txphinitdone_reg2) || (PCIE_TXSYNC_MODE == 1) || (!SYNC_ACTIVE_LANE)) ? FSM_TXSYNC_DONE1 : FSM_TXPHINITDONE);
|
txdlyen <= 1'd0;
|
txdlyen <= 1'd0;
|
txsync_done <= 1'd0;
|
txsync_done <= 1'd0;
|
end
|
end
|
|
|
//---------- Wait for TX Phase Alignment Done --
|
//---------- Wait for TX Phase Alignment Done --
|
FSM_TXSYNC_DONE1 :
|
FSM_TXSYNC_DONE1 :
|
|
|
begin
|
begin
|
if (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && !SYNC_SLAVE)
|
if (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && !SYNC_SLAVE)
|
fsm_tx <= ((!txsyncdone_reg3 && txsyncdone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
|
fsm_tx <= ((!txsyncdone_reg3 && txsyncdone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
|
else
|
else
|
fsm_tx <= ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
|
fsm_tx <= ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
|
|
|
txdlyen <= 1'd0;
|
txdlyen <= 1'd0;
|
txsync_done <= 1'd0;
|
txsync_done <= 1'd0;
|
end
|
end
|
|
|
//---------- Wait for Master TX Delay Alignment Done
|
//---------- Wait for Master TX Delay Alignment Done
|
FSM_TXSYNC_DONE2 :
|
FSM_TXSYNC_DONE2 :
|
|
|
begin
|
begin
|
if ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) || SYNC_SLAVE || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1)) || (BYPASS_TXDELAY_ALIGN == 1))
|
if ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) || SYNC_SLAVE || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1)) || (BYPASS_TXDELAY_ALIGN == 1))
|
begin
|
begin
|
fsm_tx <= FSM_TXSYNC_IDLE;
|
fsm_tx <= FSM_TXSYNC_IDLE;
|
txdlyen <= !SYNC_SLAVE;
|
txdlyen <= !SYNC_SLAVE;
|
txsync_done <= 1'd1;
|
txsync_done <= 1'd1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
fsm_tx <= FSM_TXSYNC_DONE2;
|
fsm_tx <= FSM_TXSYNC_DONE2;
|
txdlyen <= !SYNC_SLAVE;
|
txdlyen <= !SYNC_SLAVE;
|
txsync_done <= 1'd0;
|
txsync_done <= 1'd0;
|
end
|
end
|
end
|
end
|
|
|
//---------- Default State ---------------------
|
//---------- Default State ---------------------
|
default :
|
default :
|
begin
|
begin
|
fsm_tx <= FSM_TXSYNC_IDLE;
|
fsm_tx <= FSM_TXSYNC_IDLE;
|
txdlyen <= 1'd0;
|
txdlyen <= 1'd0;
|
txsync_done <= 1'd0;
|
txsync_done <= 1'd0;
|
end
|
end
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
//---------- TX Sync FSM Default------------------------------------------------
|
//---------- TX Sync FSM Default------------------------------------------------
|
else
|
else
|
|
|
begin : txsync_fsm_disable
|
begin : txsync_fsm_disable
|
|
|
//---------- Default -------------------------------------------------------
|
//---------- Default -------------------------------------------------------
|
always @ (posedge SYNC_CLK)
|
always @ (posedge SYNC_CLK)
|
begin
|
begin
|
fsm_tx <= FSM_TXSYNC_IDLE;
|
fsm_tx <= FSM_TXSYNC_IDLE;
|
txdlyen <= 1'd0;
|
txdlyen <= 1'd0;
|
txsync_done <= 1'd0;
|
txsync_done <= 1'd0;
|
end
|
end
|
|
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
//---------- Generate RX Sync FSM ----------------------------------------------
|
//---------- Generate RX Sync FSM ----------------------------------------------
|
generate if ((PCIE_LINK_SPEED == 3) && (PCIE_RXBUF_EN == "FALSE"))
|
generate if ((PCIE_LINK_SPEED == 3) && (PCIE_RXBUF_EN == "FALSE"))
|
|
|
begin : rxsync_fsm
|
begin : rxsync_fsm
|
|
|
//---------- PIPE RX Sync FSM ----------------------------------------------
|
//---------- PIPE RX Sync FSM ----------------------------------------------
|
always @ (posedge SYNC_CLK)
|
always @ (posedge SYNC_CLK)
|
begin
|
begin
|
|
|
if (!SYNC_RST_N)
|
if (!SYNC_RST_N)
|
begin
|
begin
|
fsm_rx <= FSM_RXSYNC_IDLE;
|
fsm_rx <= FSM_RXSYNC_IDLE;
|
rxdlyen <= 1'd0;
|
rxdlyen <= 1'd0;
|
rxsync_done <= 1'd0;
|
rxsync_done <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
case (fsm_rx)
|
case (fsm_rx)
|
|
|
//---------- Idle State ------------------------
|
//---------- Idle State ------------------------
|
FSM_RXSYNC_IDLE :
|
FSM_RXSYNC_IDLE :
|
|
|
begin
|
begin
|
//---------- Exiting Rate Change -----------
|
//---------- Exiting Rate Change -----------
|
if (rxsync_start_reg2)
|
if (rxsync_start_reg2)
|
begin
|
begin
|
fsm_rx <= FSM_RXCDRLOCK;
|
fsm_rx <= FSM_RXCDRLOCK;
|
rxdlyen <= 1'd0;
|
rxdlyen <= 1'd0;
|
rxsync_done <= 1'd0;
|
rxsync_done <= 1'd0;
|
end
|
end
|
//---------- Exiting Electrical Idle without Rate Change
|
//---------- Exiting Electrical Idle without Rate Change
|
else if (gen3_reg2 && rate_idle_reg2 && ((rxelecidle_reg2 == 1'd1) && (rxelecidle_reg1 == 1'd0)))
|
else if (gen3_reg2 && rate_idle_reg2 && ((rxelecidle_reg2 == 1'd1) && (rxelecidle_reg1 == 1'd0)))
|
begin
|
begin
|
fsm_rx <= FSM_RXCDRLOCK;
|
fsm_rx <= FSM_RXCDRLOCK;
|
rxdlyen <= 1'd0;
|
rxdlyen <= 1'd0;
|
rxsync_done <= 1'd0;
|
rxsync_done <= 1'd0;
|
end
|
end
|
//---------- Idle --------------------------
|
//---------- Idle --------------------------
|
else
|
else
|
begin
|
begin
|
fsm_rx <= FSM_RXSYNC_IDLE;
|
fsm_rx <= FSM_RXSYNC_IDLE;
|
rxdlyen <= rxelecidle_reg2 ? 1'd0 : rxdlyen;
|
rxdlyen <= rxelecidle_reg2 ? 1'd0 : rxdlyen;
|
rxsync_done <= rxelecidle_reg2 ? 1'd0 : rxsync_done;
|
rxsync_done <= rxelecidle_reg2 ? 1'd0 : rxsync_done;
|
end
|
end
|
end
|
end
|
|
|
//---------- Wait for RX Electrical Idle Exit and RX CDR Lock
|
//---------- Wait for RX Electrical Idle Exit and RX CDR Lock
|
FSM_RXCDRLOCK :
|
FSM_RXCDRLOCK :
|
|
|
begin
|
begin
|
fsm_rx <= ((!rxelecidle_reg2 && rxcdrlock_reg2) ? FSM_RXSYNC_START : FSM_RXCDRLOCK);
|
fsm_rx <= ((!rxelecidle_reg2 && rxcdrlock_reg2) ? FSM_RXSYNC_START : FSM_RXCDRLOCK);
|
rxdlyen <= 1'd0;
|
rxdlyen <= 1'd0;
|
rxsync_done <= 1'd0;
|
rxsync_done <= 1'd0;
|
end
|
end
|
|
|
//---------- Start RX Sync with RX Delay Soft Reset
|
//---------- Start RX Sync with RX Delay Soft Reset
|
FSM_RXSYNC_START :
|
FSM_RXSYNC_START :
|
|
|
begin
|
begin
|
fsm_rx <= ((!rxdlysresetdone_reg2 && rxdlysresetdone_reg1) ? FSM_RXSYNC_DONE1 : FSM_RXSYNC_START);
|
fsm_rx <= ((!rxdlysresetdone_reg2 && rxdlysresetdone_reg1) ? FSM_RXSYNC_DONE1 : FSM_RXSYNC_START);
|
rxdlyen <= 1'd0;
|
rxdlyen <= 1'd0;
|
rxsync_done <= 1'd0;
|
rxsync_done <= 1'd0;
|
end
|
end
|
|
|
//---------- Wait for RX Phase Alignment Done --
|
//---------- Wait for RX Phase Alignment Done --
|
FSM_RXSYNC_DONE1 :
|
FSM_RXSYNC_DONE1 :
|
|
|
begin
|
begin
|
if (SYNC_SLAVE)
|
if (SYNC_SLAVE)
|
begin
|
begin
|
fsm_rx <= ((!rxphaligndone_s_reg2 && rxphaligndone_s_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
|
fsm_rx <= ((!rxphaligndone_s_reg2 && rxphaligndone_s_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
|
rxdlyen <= 1'd0;
|
rxdlyen <= 1'd0;
|
rxsync_done <= 1'd0;
|
rxsync_done <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
fsm_rx <= ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
|
fsm_rx <= ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
|
rxdlyen <= 1'd0;
|
rxdlyen <= 1'd0;
|
rxsync_done <= 1'd0;
|
rxsync_done <= 1'd0;
|
end
|
end
|
end
|
end
|
|
|
//---------- Wait for Master RX Delay Alignment Done
|
//---------- Wait for Master RX Delay Alignment Done
|
FSM_RXSYNC_DONE2 :
|
FSM_RXSYNC_DONE2 :
|
|
|
begin
|
begin
|
if (SYNC_SLAVE)
|
if (SYNC_SLAVE)
|
begin
|
begin
|
fsm_rx <= FSM_RXSYNC_IDLE;
|
fsm_rx <= FSM_RXSYNC_IDLE;
|
rxdlyen <= 1'd0;
|
rxdlyen <= 1'd0;
|
rxsync_done <= 1'd1;
|
rxsync_done <= 1'd1;
|
end
|
end
|
else if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
|
else if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
|
begin
|
begin
|
fsm_rx <= ((PCIE_LANE == 1) ? FSM_RXSYNC_IDLE : FSM_RXSYNC_DONES);
|
fsm_rx <= ((PCIE_LANE == 1) ? FSM_RXSYNC_IDLE : FSM_RXSYNC_DONES);
|
rxdlyen <= (PCIE_LANE == 1);
|
rxdlyen <= (PCIE_LANE == 1);
|
rxsync_done <= (PCIE_LANE == 1);
|
rxsync_done <= (PCIE_LANE == 1);
|
end
|
end
|
else
|
else
|
begin
|
begin
|
fsm_rx <= FSM_RXSYNC_DONE2;
|
fsm_rx <= FSM_RXSYNC_DONE2;
|
rxdlyen <= 1'd1;
|
rxdlyen <= 1'd1;
|
rxsync_done <= 1'd0;
|
rxsync_done <= 1'd0;
|
end
|
end
|
end
|
end
|
|
|
//---------- Wait for Slave RX Phase Alignment Done
|
//---------- Wait for Slave RX Phase Alignment Done
|
FSM_RXSYNC_DONES :
|
FSM_RXSYNC_DONES :
|
|
|
begin
|
begin
|
if (!rxphaligndone_s_reg2 && rxphaligndone_s_reg1)
|
if (!rxphaligndone_s_reg2 && rxphaligndone_s_reg1)
|
begin
|
begin
|
fsm_rx <= FSM_RXSYNC_DONEM;
|
fsm_rx <= FSM_RXSYNC_DONEM;
|
rxdlyen <= 1'd1;
|
rxdlyen <= 1'd1;
|
rxsync_done <= 1'd0;
|
rxsync_done <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
fsm_rx <= FSM_RXSYNC_DONES;
|
fsm_rx <= FSM_RXSYNC_DONES;
|
rxdlyen <= 1'd0;
|
rxdlyen <= 1'd0;
|
rxsync_done <= 1'd0;
|
rxsync_done <= 1'd0;
|
end
|
end
|
end
|
end
|
|
|
//---------- Wait for Master RX Delay Alignment Done
|
//---------- Wait for Master RX Delay Alignment Done
|
FSM_RXSYNC_DONEM :
|
FSM_RXSYNC_DONEM :
|
|
|
begin
|
begin
|
if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
|
if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
|
begin
|
begin
|
fsm_rx <= FSM_RXSYNC_IDLE;
|
fsm_rx <= FSM_RXSYNC_IDLE;
|
rxdlyen <= 1'd1;
|
rxdlyen <= 1'd1;
|
rxsync_done <= 1'd1;
|
rxsync_done <= 1'd1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
fsm_rx <= FSM_RXSYNC_DONEM;
|
fsm_rx <= FSM_RXSYNC_DONEM;
|
rxdlyen <= 1'd1;
|
rxdlyen <= 1'd1;
|
rxsync_done <= 1'd0;
|
rxsync_done <= 1'd0;
|
end
|
end
|
end
|
end
|
|
|
//---------- Default State ---------------------
|
//---------- Default State ---------------------
|
default :
|
default :
|
begin
|
begin
|
fsm_rx <= FSM_RXSYNC_IDLE;
|
fsm_rx <= FSM_RXSYNC_IDLE;
|
rxdlyen <= 1'd0;
|
rxdlyen <= 1'd0;
|
rxsync_done <= 1'd0;
|
rxsync_done <= 1'd0;
|
end
|
end
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
//---------- RX Sync FSM Default -----------------------------------------------
|
//---------- RX Sync FSM Default -----------------------------------------------
|
else
|
else
|
|
|
begin : rxsync_fsm_disable
|
begin : rxsync_fsm_disable
|
|
|
//---------- Default -------------------------------------------------------
|
//---------- Default -------------------------------------------------------
|
always @ (posedge SYNC_CLK)
|
always @ (posedge SYNC_CLK)
|
begin
|
begin
|
fsm_rx <= FSM_RXSYNC_IDLE;
|
fsm_rx <= FSM_RXSYNC_IDLE;
|
rxdlyen <= 1'd0;
|
rxdlyen <= 1'd0;
|
rxsync_done <= 1'd0;
|
rxsync_done <= 1'd0;
|
end
|
end
|
|
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
//---------- PIPE Sync Output --------------------------------------------------
|
//---------- PIPE Sync Output --------------------------------------------------
|
assign SYNC_TXPHALIGNEN = ((PCIE_TXSYNC_MODE == 1) || (!gen3_reg2 && (PCIE_TXBUF_EN == "TRUE"))) ? 1'd0 : 1'd1;
|
assign SYNC_TXPHALIGNEN = ((PCIE_TXSYNC_MODE == 1) || (!gen3_reg2 && (PCIE_TXBUF_EN == "TRUE"))) ? 1'd0 : 1'd1;
|
assign SYNC_TXDLYBYPASS = 1'd0;
|
assign SYNC_TXDLYBYPASS = 1'd0;
|
//assign SYNC_TXDLYSRESET = !(((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;
|
//assign SYNC_TXDLYSRESET = !(((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;
|
assign SYNC_TXDLYSRESET = (fsm_tx == FSM_TXSYNC_START);
|
assign SYNC_TXDLYSRESET = (fsm_tx == FSM_TXSYNC_START);
|
assign SYNC_TXPHDLYRESET = (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;
|
assign SYNC_TXPHDLYRESET = (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;
|
assign SYNC_TXPHINIT = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXPHINITDONE);
|
assign SYNC_TXPHINIT = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXPHINITDONE);
|
assign SYNC_TXPHALIGN = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXSYNC_DONE1);
|
assign SYNC_TXPHALIGN = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXSYNC_DONE1);
|
assign SYNC_TXDLYEN = PCIE_TXSYNC_MODE ? 1'd0 : txdlyen;
|
assign SYNC_TXDLYEN = PCIE_TXSYNC_MODE ? 1'd0 : txdlyen;
|
assign SYNC_TXSYNC_DONE = txsync_done;
|
assign SYNC_TXSYNC_DONE = txsync_done;
|
assign SYNC_FSM_TX = fsm_tx;
|
assign SYNC_FSM_TX = fsm_tx;
|
|
|
assign SYNC_RXPHALIGNEN = ((PCIE_RXSYNC_MODE == 1) || (!gen3_reg2) || (PCIE_RXBUF_EN == "TRUE")) ? 1'd0 : 1'd1;
|
assign SYNC_RXPHALIGNEN = ((PCIE_RXSYNC_MODE == 1) || (!gen3_reg2) || (PCIE_RXBUF_EN == "TRUE")) ? 1'd0 : 1'd1;
|
assign SYNC_RXDLYBYPASS = !gen3_reg2 || (PCIE_RXBUF_EN == "TRUE");
|
assign SYNC_RXDLYBYPASS = !gen3_reg2 || (PCIE_RXBUF_EN == "TRUE");
|
assign SYNC_RXDLYSRESET = (fsm_rx == FSM_RXSYNC_START);
|
assign SYNC_RXDLYSRESET = (fsm_rx == FSM_RXSYNC_START);
|
assign SYNC_RXPHALIGN = PCIE_RXSYNC_MODE ? 1'd0 : (!SYNC_SLAVE ? (fsm_rx == FSM_RXSYNC_DONE1) : (rxsync_donem_reg2 && (fsm_rx == FSM_RXSYNC_DONE1)));
|
assign SYNC_RXPHALIGN = PCIE_RXSYNC_MODE ? 1'd0 : (!SYNC_SLAVE ? (fsm_rx == FSM_RXSYNC_DONE1) : (rxsync_donem_reg2 && (fsm_rx == FSM_RXSYNC_DONE1)));
|
assign SYNC_RXDLYEN = PCIE_RXSYNC_MODE ? 1'd0 : rxdlyen;
|
assign SYNC_RXDLYEN = PCIE_RXSYNC_MODE ? 1'd0 : rxdlyen;
|
assign SYNC_RXDDIEN = gen3_reg2 && (PCIE_RXBUF_EN == "FALSE");
|
assign SYNC_RXDDIEN = gen3_reg2 && (PCIE_RXBUF_EN == "FALSE");
|
assign SYNC_RXSYNC_DONE = rxsync_done;
|
assign SYNC_RXSYNC_DONE = rxsync_done;
|
assign SYNC_RXSYNC_DONEM_OUT = (fsm_rx == FSM_RXSYNC_DONES);
|
assign SYNC_RXSYNC_DONEM_OUT = (fsm_rx == FSM_RXSYNC_DONES);
|
assign SYNC_FSM_RX = fsm_rx;
|
assign SYNC_FSM_RX = fsm_rx;
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
