----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
-- Company: ;)
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-- Company: ;)
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-- Engineer: Kuzmi4
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-- Engineer: Kuzmi4
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--
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--
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-- Create Date: 17:40:25 05/21/2010
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-- Create Date: 17:40:25 05/21/2010
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-- Design Name:
|
-- Design Name:
|
-- Module Name: block_generate_wb_config_slave - rtl
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-- Module Name: block_generate_wb_config_slave - rtl
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-- Project Name: DS_DMA
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-- Project Name: DS_DMA
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-- Target Devices: any
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-- Target Devices: any
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-- Tool versions:
|
-- Tool versions:
|
-- Description:
|
-- Description:
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--
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--
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-- For now we have such restrictions for WB component:
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-- For now we have such restrictions for WB component:
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-- 1) no WB_RTY support
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-- 1) no WB_RTY support
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-- 2) WB_ERR arize only at event detection and fall after it goes.
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-- 2) WB_ERR arize only at event detection and fall after it goes.
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-- 3) Operate with Single 64bit WB Transfers. NO WB BURSTs.
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-- 3) Operate with Single 64bit WB Transfers. NO WB BURSTs.
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-- 4) (TBD)...
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-- 4) (TBD)...
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--
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--
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-- WB_SLAVE MM (ONLY 256B range):
|
-- WB_SLAVE MM (ONLY 256B range):
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-- 1) CONSTANTs:
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-- 1) CONSTANTs:
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-- ADDR=x00 - BLOCK_ID
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-- ADDR=x00 - BLOCK_ID
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-- ADDR=x08 - BLOCK_VER
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-- ADDR=x08 - BLOCK_VER
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-- ADDR=x10 - RSVD (CONSTANTs)
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-- ADDR=x10 - RSVD (CONSTANTs)
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-- ADDR=x18 - RSVD (CONSTANTs)
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-- ADDR=x18 - RSVD (CONSTANTs)
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-- ADDR=x20 - RSVD (CONSTANTs)
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-- ADDR=x20 - RSVD (CONSTANTs)
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-- ADDR=x28 - RSVD (CONSTANTs)
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-- ADDR=x28 - RSVD (CONSTANTs)
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-- ADDR=x30 - RSVD (CONSTANTs)
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-- ADDR=x30 - RSVD (CONSTANTs)
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-- ADDR=x38 - RSVD (CONSTANTs)
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-- ADDR=x38 - RSVD (CONSTANTs)
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-- 2) COMMAND REGs:
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-- 2) COMMAND REGs:
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-- ADDR=x40 - TEST_GEN_CTRL
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-- ADDR=x40 - TEST_GEN_CTRL
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-- ADDR=x48 - TEST_GEN_SIZE
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-- ADDR=x48 - TEST_GEN_SIZE
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-- ADDR=x50 - TEST_GEN_CNT1
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-- ADDR=x50 - TEST_GEN_CNT1
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-- ADDR=x58 - TEST_GEN_CNT2
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-- ADDR=x58 - TEST_GEN_CNT2
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-- ADDR=x60 - RSVD (COMMAND REGs)
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-- ADDR=x60 - RSVD (COMMAND REGs)
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-- ADDR=x68 - RSVD (COMMAND REGs)
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-- ADDR=x68 - RSVD (COMMAND REGs)
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-- ADDR=x70 - RSVD (COMMAND REGs)
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-- ADDR=x70 - RSVD (COMMAND REGs)
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-- ADDR=x78 - RSVD (COMMAND REGs)
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-- ADDR=x78 - RSVD (COMMAND REGs)
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-- 3) STS REGs, etc:
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-- 3) STS REGs, etc:
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-- ADDR=x80 - TEST_GEN_BL_WR
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-- ADDR=x80 - TEST_GEN_STATUS
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-- ADDR=x88 - RSVD (STS REGs, etc)
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-- ADDR=x88 - TEST_GEN_BL_WR
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-- ADDR=x90 - 0xAAAAAAAA
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-- ADDR=x98 - RSVD (STS REGs, etc)
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-- ....
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-- ....
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-- ADDR=xFF - RSVD (STS REGs, etc)
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-- ADDR=xFF - RSVD (STS REGs, etc)
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--
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--
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--
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--
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created,
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-- Revision 0.01 - File Created,
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-- 2do: for now ADD MemoryMap looks good, but maybe its quite diff from REAL SITUATION --> CHECK/FIX MM later!!!
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-- 2do: for now ADD MemoryMap looks good, but maybe its quite diff from REAL SITUATION --> CHECK/FIX MM later!!!
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-- Revision 0.02 - upd WB_ERR func.
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-- Revision 0.02 - upd WB_ERR func.
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-- Revision 0.03 - fix MM (8cell allign).
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-- Revision 0.03 - fix MM (8cell allign).
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
|
library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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|
|
package block_generate_wb_config_slave_pkg is
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package block_generate_wb_config_slave_pkg is
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|
|
component block_generate_wb_config_slave is
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component block_generate_wb_config_slave is
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generic
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generic
|
(
|
(
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BLOCK_ID : in std_logic_vector( 15 downto 0 ):=x"0000"; -- идентификатор модуля
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BLOCK_ID : in std_logic_vector( 15 downto 0 ):=x"0000"; -- идентификатор модуля
|
BLOCK_VER : in std_logic_vector( 15 downto 0 ):=x"0000" -- версия модуля
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BLOCK_VER : in std_logic_vector( 15 downto 0 ):=x"0000" -- версия модуля
|
);
|
);
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port
|
port
|
(
|
(
|
--
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--
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-- SYS_CON
|
-- SYS_CON
|
i_clk : in STD_LOGIC;
|
i_clk : in STD_LOGIC;
|
i_rst : in STD_LOGIC;
|
i_rst : in STD_LOGIC;
|
--
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--
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-- WB CFG SLAVE
|
-- WB CFG SLAVE
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iv_wbs_cfg_addr : in std_logic_vector( 7 downto 0 );
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iv_wbs_cfg_addr : in std_logic_vector( 7 downto 0 );
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iv_wbs_cfg_data : in std_logic_vector( 63 downto 0 );
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iv_wbs_cfg_data : in std_logic_vector( 63 downto 0 );
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iv_wbs_cfg_sel : in std_logic_vector( 7 downto 0 ); -- wor now, we NC this wires
|
iv_wbs_cfg_sel : in std_logic_vector( 7 downto 0 ); -- wor now, we NC this wires
|
i_wbs_cfg_we : in std_logic;
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i_wbs_cfg_we : in std_logic;
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i_wbs_cfg_cyc : in std_logic;
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i_wbs_cfg_cyc : in std_logic;
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i_wbs_cfg_stb : in std_logic;
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i_wbs_cfg_stb : in std_logic;
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iv_wbs_cfg_cti : in std_logic_vector( 2 downto 0 );
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iv_wbs_cfg_cti : in std_logic_vector( 2 downto 0 );
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iv_wbs_cfg_bte : in std_logic_vector( 1 downto 0 );
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iv_wbs_cfg_bte : in std_logic_vector( 1 downto 0 );
|
|
|
ov_wbs_cfg_data : out std_logic_vector( 63 downto 0 );
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ov_wbs_cfg_data : out std_logic_vector( 63 downto 0 );
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o_wbs_cfg_ack : out std_logic;
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o_wbs_cfg_ack : out std_logic;
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o_wbs_cfg_err : out std_logic;
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o_wbs_cfg_err : out std_logic;
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o_wbs_cfg_rty : out std_logic;
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o_wbs_cfg_rty : out std_logic;
|
--
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--
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-- CONTROL Outputs
|
-- CONTROL Outputs
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ov_test_gen_ctrl : out std_logic_vector( 15 downto 0 );
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ov_test_gen_ctrl : out std_logic_vector( 15 downto 0 );
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ov_test_gen_size : out std_logic_vector( 15 downto 0 );
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ov_test_gen_size : out std_logic_vector( 15 downto 0 );
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ov_test_gen_cnt1 : out std_logic_vector( 15 downto 0 );
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ov_test_gen_cnt1 : out std_logic_vector( 15 downto 0 );
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ov_test_gen_cnt2 : out std_logic_vector( 15 downto 0 );
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ov_test_gen_cnt2 : out std_logic_vector( 15 downto 0 );
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--
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--
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-- STATUS Input
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-- STATUS Input
|
|
iv_test_gen_status : in std_logic_vector( 31 downto 0 );
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iv_test_gen_bl_wr : in std_logic_vector( 31 downto 0 )
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iv_test_gen_bl_wr : in std_logic_vector( 31 downto 0 )
|
);
|
);
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end component block_generate_wb_config_slave;
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end component block_generate_wb_config_slave;
|
|
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end package block_generate_wb_config_slave_pkg;
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end package block_generate_wb_config_slave_pkg;
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
|
library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
|
|
library work;
|
library work;
|
use work.ctrl_ram16_v1_pkg.all;
|
use work.ctrl_ram16_v1_pkg.all;
|
use work.host_pkg.all;
|
use work.host_pkg.all;
|
|
|
entity block_generate_wb_config_slave is
|
entity block_generate_wb_config_slave is
|
generic
|
generic
|
(
|
(
|
BLOCK_ID : in std_logic_vector( 15 downto 0 ):=x"0000"; -- идентификатор модуля
|
BLOCK_ID : in std_logic_vector( 15 downto 0 ):=x"0000"; -- идентификатор модуля
|
BLOCK_VER : in std_logic_vector( 15 downto 0 ):=x"0000" -- версия модуля
|
BLOCK_VER : in std_logic_vector( 15 downto 0 ):=x"0000" -- версия модуля
|
);
|
);
|
port
|
port
|
(
|
(
|
--
|
--
|
-- SYS_CON
|
-- SYS_CON
|
i_clk : in STD_LOGIC;
|
i_clk : in STD_LOGIC;
|
i_rst : in STD_LOGIC;
|
i_rst : in STD_LOGIC;
|
--
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--
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-- WB CFG SLAVE
|
-- WB CFG SLAVE
|
iv_wbs_cfg_addr : in std_logic_vector( 7 downto 0 );
|
iv_wbs_cfg_addr : in std_logic_vector( 7 downto 0 );
|
iv_wbs_cfg_data : in std_logic_vector( 63 downto 0 );
|
iv_wbs_cfg_data : in std_logic_vector( 63 downto 0 );
|
iv_wbs_cfg_sel : in std_logic_vector( 7 downto 0 ); -- wor now, we NC this wires
|
iv_wbs_cfg_sel : in std_logic_vector( 7 downto 0 ); -- wor now, we NC this wires
|
i_wbs_cfg_we : in std_logic;
|
i_wbs_cfg_we : in std_logic;
|
i_wbs_cfg_cyc : in std_logic;
|
i_wbs_cfg_cyc : in std_logic;
|
i_wbs_cfg_stb : in std_logic;
|
i_wbs_cfg_stb : in std_logic;
|
iv_wbs_cfg_cti : in std_logic_vector( 2 downto 0 );
|
iv_wbs_cfg_cti : in std_logic_vector( 2 downto 0 );
|
iv_wbs_cfg_bte : in std_logic_vector( 1 downto 0 );
|
iv_wbs_cfg_bte : in std_logic_vector( 1 downto 0 );
|
|
|
ov_wbs_cfg_data : out std_logic_vector( 63 downto 0 );
|
ov_wbs_cfg_data : out std_logic_vector( 63 downto 0 );
|
o_wbs_cfg_ack : out std_logic;
|
o_wbs_cfg_ack : out std_logic;
|
o_wbs_cfg_err : out std_logic;
|
o_wbs_cfg_err : out std_logic;
|
o_wbs_cfg_rty : out std_logic;
|
o_wbs_cfg_rty : out std_logic;
|
--
|
--
|
-- CONTROL Outputs
|
-- CONTROL Outputs
|
ov_test_gen_ctrl : out std_logic_vector( 15 downto 0 );
|
ov_test_gen_ctrl : out std_logic_vector( 15 downto 0 );
|
ov_test_gen_size : out std_logic_vector( 15 downto 0 );
|
ov_test_gen_size : out std_logic_vector( 15 downto 0 );
|
ov_test_gen_cnt1 : out std_logic_vector( 15 downto 0 );
|
ov_test_gen_cnt1 : out std_logic_vector( 15 downto 0 );
|
ov_test_gen_cnt2 : out std_logic_vector( 15 downto 0 );
|
ov_test_gen_cnt2 : out std_logic_vector( 15 downto 0 );
|
--
|
--
|
-- STATUS Input
|
-- STATUS Input
|
|
iv_test_gen_status : in std_logic_vector( 31 downto 0 );
|
iv_test_gen_bl_wr : in std_logic_vector( 31 downto 0 )
|
iv_test_gen_bl_wr : in std_logic_vector( 31 downto 0 )
|
);
|
);
|
end block_generate_wb_config_slave;
|
end block_generate_wb_config_slave;
|
|
|
architecture rtl of block_generate_wb_config_slave is
|
architecture rtl of block_generate_wb_config_slave is
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
--
|
--
|
-- Define CONSTANTs
|
-- Define CONSTANTs
|
constant ct_bl_rom : bh_rom:=(
|
constant ct_bl_rom : bh_rom:=(
|
0=> BLOCK_ID, --
|
0=> BLOCK_ID, --
|
1=> BLOCK_VER, --
|
1=> BLOCK_VER, --
|
2=> x"5504", -- 2=> Device_ID,
|
2=> x"5504", -- 2=> Device_ID,
|
3=> x"0210", -- 3=> Revision,
|
3=> x"0210", -- 3=> Revision,
|
4=> x"0104", -- 4=> PLD_VER,
|
4=> x"0104", -- 4=> PLD_VER,
|
5=> x"0000",
|
5=> x"0000",
|
6=> x"0000",
|
6=> x"0000",
|
7=> x"0000"
|
7=> x"0000"
|
);
|
);
|
--
|
--
|
-- Define BL_RAM stuff:
|
-- Define BL_RAM stuff:
|
signal sv_bl_ram_adr : std_logic_vector( 4 downto 0):= (others => '0');
|
signal sv_bl_ram_adr : std_logic_vector( 4 downto 0):= (others => '0');
|
signal sv_bl_ram_data_in : std_logic_vector(15 downto 0):= (others => '0');
|
signal sv_bl_ram_data_in : std_logic_vector(15 downto 0):= (others => '0');
|
signal sv_bl_ram_data_out : std_logic_vector(15 downto 0):= (others => '0');
|
signal sv_bl_ram_data_out : std_logic_vector(15 downto 0):= (others => '0');
|
signal s_bl_ram_data_we : std_logic:= '0';
|
signal s_bl_ram_data_we : std_logic:= '0';
|
--
|
--
|
-- DEFINE WB_FSM (required for build correct WB_ACK) stuff:
|
-- DEFINE WB_FSM (required for build correct WB_ACK) stuff:
|
signal sv_wbs_cfg_ack_counter : std_logic:='0';
|
signal sv_wbs_cfg_ack_counter : std_logic:='0';
|
--
|
--
|
-- Define additional WB signals:
|
-- Define additional WB signals:
|
signal s_wbs_active_wr : std_logic;
|
signal s_wbs_active_wr : std_logic;
|
signal s_wbs_active_rd : std_logic;
|
signal s_wbs_active_rd : std_logic;
|
signal s_wbs_active : std_logic;
|
signal s_wbs_active : std_logic;
|
signal s_wbs_wr_ena : std_logic;
|
signal s_wbs_wr_ena : std_logic;
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
begin
|
begin
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
--
|
--
|
-- WB ACTIVE/ENA flag (for RD/WR and for any WB activity)
|
-- WB ACTIVE/ENA flag (for RD/WR and for any WB activity)
|
--
|
--
|
s_wbs_active_wr <= '1' when (
|
s_wbs_active_wr <= '1' when (
|
i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' and i_wbs_cfg_we='1' and -- all strobes OK
|
i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' and i_wbs_cfg_we='1' and -- all strobes OK
|
(iv_wbs_cfg_cti="000") and (iv_wbs_cfg_bte="00") -- type of transfer OK
|
(iv_wbs_cfg_cti="000") and (iv_wbs_cfg_bte="00") -- type of transfer OK
|
) else '0';
|
) else '0';
|
|
|
s_wbs_active_rd <= '1' when (
|
s_wbs_active_rd <= '1' when (
|
i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' and i_wbs_cfg_we='0' and
|
i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' and i_wbs_cfg_we='0' and
|
(iv_wbs_cfg_cti="000") and (iv_wbs_cfg_bte="00")
|
(iv_wbs_cfg_cti="000") and (iv_wbs_cfg_bte="00")
|
) else '0';
|
) else '0';
|
|
|
s_wbs_active <= '1' when (
|
s_wbs_active <= '1' when (
|
i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' and
|
i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' and
|
(iv_wbs_cfg_cti="000") and (iv_wbs_cfg_bte="00")
|
(iv_wbs_cfg_cti="000") and (iv_wbs_cfg_bte="00")
|
) else '0';
|
) else '0';
|
|
|
s_wbs_wr_ena <= '1' when (
|
s_wbs_wr_ena <= '1' when (
|
s_wbs_active_wr='1' and -- have ACTIVE WR flag
|
s_wbs_active_wr='1' and -- have ACTIVE WR flag
|
(sv_wbs_cfg_ack_counter='1') -- present WB_ACK source
|
(sv_wbs_cfg_ack_counter='1') -- present WB_ACK source
|
) else '0';
|
) else '0';
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
--
|
--
|
-- WB Write process
|
-- WB Write process
|
--
|
--
|
WB_WRITE : process (i_clk, i_rst)
|
WB_WRITE : process (i_clk, i_rst)
|
begin
|
begin
|
if (i_rst='1') then -- RST
|
if (i_rst='1') then -- RST
|
ov_test_gen_ctrl <= (others => '0');
|
ov_test_gen_ctrl <= (others => '0');
|
ov_test_gen_size <= (others => '0');
|
ov_test_gen_size <= (others => '0');
|
ov_test_gen_cnt1 <= (others => '0');
|
ov_test_gen_cnt1 <= (others => '0');
|
ov_test_gen_cnt2 <= (others => '0');
|
ov_test_gen_cnt2 <= (others => '0');
|
elsif (rising_edge(i_clk)) then -- WRK
|
elsif (rising_edge(i_clk)) then -- WRK
|
if (s_wbs_wr_ena='1') then
|
if (s_wbs_wr_ena='1') then
|
case(iv_wbs_cfg_addr(7 downto 0)) is
|
case(iv_wbs_cfg_addr(7 downto 0)) is
|
when x"40" => ov_test_gen_ctrl <= iv_wbs_cfg_data( 15 downto 0);
|
when x"40" => ov_test_gen_ctrl <= iv_wbs_cfg_data( 15 downto 0);
|
when x"48" => ov_test_gen_size <= iv_wbs_cfg_data( 15 downto 0);
|
when x"48" => ov_test_gen_size <= iv_wbs_cfg_data( 15 downto 0);
|
when x"50" => ov_test_gen_cnt1 <= iv_wbs_cfg_data( 15 downto 0);
|
when x"50" => ov_test_gen_cnt1 <= iv_wbs_cfg_data( 15 downto 0);
|
when x"58" => ov_test_gen_cnt2 <= iv_wbs_cfg_data( 15 downto 0);
|
when x"58" => ov_test_gen_cnt2 <= iv_wbs_cfg_data( 15 downto 0);
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process WB_WRITE;
|
end process WB_WRITE;
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
--
|
--
|
-- WB Read process
|
-- WB Read process
|
--
|
--
|
WB_READ : process (i_clk, i_rst)
|
--WB_READ : process (i_clk, i_rst)
|
begin
|
-- begin
|
if (i_rst='1') then -- RST
|
-- if (i_rst='1') then -- RST
|
ov_wbs_cfg_data <= (others => '0');
|
-- ov_wbs_cfg_data <= (others => '0');
|
elsif (rising_edge(i_clk)) then -- WRK
|
-- elsif (rising_edge(i_clk)) then -- WRK
|
if (s_wbs_active_rd='1') then
|
-- if (s_wbs_active_rd='1') then
|
case(iv_wbs_cfg_addr(7 downto 0)) is
|
-- case(iv_wbs_cfg_addr(7 downto 0)) is
|
-- STS MM region
|
-- -- STS MM region
|
when x"80" => ov_wbs_cfg_data(31 downto 0) <= iv_test_gen_bl_wr;
|
-- when x"80" => ov_wbs_cfg_data(31 downto 0) <= iv_test_gen_status;
|
-- BL_RAM MM region
|
-- when x"88" => ov_wbs_cfg_data(31 downto 0) <= iv_test_gen_bl_wr;
|
when others => ov_wbs_cfg_data(15 downto 0) <= sv_bl_ram_data_out;
|
-- when x"90" | x"98" | x"A0" | x"A" | x"86" | x"87" | x"88"
|
|
-- when x"89" | x"8A" | x"8B" | x"8C" | x"8D" | x"8E" | x"8F"
|
|
-- -- BL_RAM MM region
|
|
-- when others => ov_wbs_cfg_data(15 downto 0) <= sv_bl_ram_data_out;
|
|
-- end case;
|
|
-- end if;
|
|
-- end if;
|
|
--end process WB_READ;
|
|
|
|
WB_READ: process( iv_test_gen_status, iv_test_gen_bl_wr, iv_wbs_cfg_addr ) begin
|
|
if( iv_wbs_cfg_addr(7)='0' ) then
|
|
ov_wbs_cfg_data <= x"000000000000" & sv_bl_ram_data_out;
|
|
else
|
|
case( iv_wbs_cfg_addr( 6 downto 3 ) ) is
|
|
when "0000" => ov_wbs_cfg_data <= x"00000000" & iv_test_gen_status;
|
|
when "0001" => ov_wbs_cfg_data <= x"00000000" & iv_test_gen_bl_wr;
|
|
when "0010" => ov_wbs_cfg_data <= x"00000000" & x"AAAAAAAA";
|
|
when others => ov_wbs_cfg_data <= (others=>'0');
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end case;
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end case;
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end if;
|
end if;
|
end if;
|
end process;
|
end process WB_READ;
|
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
--
|
--
|
-- WB ACK process
|
-- WB ACK process
|
--
|
--
|
WB_ACK_CNT : process (i_clk, i_rst)
|
WB_ACK_CNT : process (i_clk, i_rst)
|
begin
|
begin
|
if (i_rst='1') then -- RST
|
if (i_rst='1') then -- RST
|
sv_wbs_cfg_ack_counter <= '0';
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sv_wbs_cfg_ack_counter <= '0';
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elsif (rising_edge(i_clk)) then -- WRK:
|
elsif (rising_edge(i_clk)) then -- WRK:
|
if (s_wbs_active='1') then -- WB Transfer in progress
|
if (s_wbs_active='1') then -- WB Transfer in progress
|
--sv_wbs_cfg_ack_counter <= sv_wbs_cfg_ack_counter + '1';
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--sv_wbs_cfg_ack_counter <= sv_wbs_cfg_ack_counter + '1';
|
if (sv_wbs_cfg_ack_counter='0') then
|
if (sv_wbs_cfg_ack_counter='0') then
|
sv_wbs_cfg_ack_counter <= '1';
|
sv_wbs_cfg_ack_counter <= '1';
|
else
|
else
|
sv_wbs_cfg_ack_counter <= '0';
|
sv_wbs_cfg_ack_counter <= '0';
|
end if;
|
end if;
|
else -- no WB Transfer
|
else -- no WB Transfer
|
sv_wbs_cfg_ack_counter <= '0';
|
sv_wbs_cfg_ack_counter <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process WB_ACK_CNT;
|
end process WB_ACK_CNT;
|
-- Define WB_ACK
|
-- Define WB_ACK
|
o_wbs_cfg_ack <= '1' when (
|
o_wbs_cfg_ack <= '1' when (
|
sv_wbs_cfg_ack_counter='1' and
|
sv_wbs_cfg_ack_counter='1' and
|
i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' -- add controls for avoid problems in anarranged transfers
|
i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' -- add controls for avoid problems in anarranged transfers
|
) else '0';
|
) else '0';
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
--
|
--
|
-- Instaniate BL_RAM (contain CONSTANTs and RD values for COMMAND registers)
|
-- Instaniate BL_RAM (contain CONSTANTs and RD values for COMMAND registers)
|
--
|
--
|
BL_RAM : ctrl_ram16_v1
|
BL_RAM : ctrl_ram16_v1
|
generic map
|
generic map
|
(
|
(
|
rom => ct_bl_rom -- значения констант
|
rom => ct_bl_rom -- значения констант
|
)
|
)
|
port map
|
port map
|
(
|
(
|
clk => i_clk, -- Тактовая частота
|
clk => i_clk, -- Тактовая частота
|
|
|
adr => sv_bl_ram_adr, -- адрес
|
adr => sv_bl_ram_adr, -- адрес
|
data_in => sv_bl_ram_data_in, -- вход данных
|
data_in => sv_bl_ram_data_in, -- вход данных
|
data_out => sv_bl_ram_data_out, -- выход данных
|
data_out => sv_bl_ram_data_out, -- выход данных
|
|
|
data_we => s_bl_ram_data_we -- 1 - запись данных
|
data_we => s_bl_ram_data_we -- 1 - запись данных
|
);
|
);
|
-- Define BL_RAM ADDR
|
-- Define BL_RAM ADDR
|
sv_bl_ram_adr <= iv_wbs_cfg_addr( 7 downto 3); -- 8B granularity Transfers (cut [2:0] addr bits)
|
sv_bl_ram_adr <= iv_wbs_cfg_addr( 7 downto 3); -- 8B granularity Transfers (cut [2:0] addr bits)
|
-- DEFINE BL_RAM DATA_IN
|
-- DEFINE BL_RAM DATA_IN
|
sv_bl_ram_data_in <= iv_wbs_cfg_data(15 downto 0); -- Cut only LS 16bit
|
sv_bl_ram_data_in <= iv_wbs_cfg_data(15 downto 0); -- Cut only LS 16bit
|
-- DEFINE BL_RAM DATA_WRITE
|
-- DEFINE BL_RAM DATA_WRITE
|
s_bl_ram_data_we <= s_wbs_wr_ena; -- WB_WE signal is OK
|
s_bl_ram_data_we <= s_wbs_wr_ena; -- WB_WE signal is OK
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
--
|
--
|
-- MODULE OUTPUTs routing:
|
-- MODULE OUTPUTs routing:
|
--
|
--
|
-- WB_ERR deal
|
-- WB_ERR deal
|
o_wbs_cfg_err <= '1' when (
|
o_wbs_cfg_err <= '1' when (
|
i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' and -- all strobes OK
|
i_wbs_cfg_cyc='1' and i_wbs_cfg_stb='1' and -- all strobes OK
|
( (iv_wbs_cfg_cti/="000") or (iv_wbs_cfg_bte/="00") ) -- BUT type of transfer is NOT OK
|
( (iv_wbs_cfg_cti/="000") or (iv_wbs_cfg_bte/="00") ) -- BUT type of transfer is NOT OK
|
) else '0';
|
) else '0';
|
-- WB_RTY deal
|
-- WB_RTY deal
|
o_wbs_cfg_rty <= '0'; -- nothing to report for now
|
o_wbs_cfg_rty <= '0'; -- nothing to report for now
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
end rtl;
|
end rtl;
|
|
|
|
|