--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
|
-- This file is owned and controlled by Xilinx and must be used solely --
|
|
-- for design, simulation, implementation and creation of design files --
|
|
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
|
|
-- devices or technologies is expressly prohibited and immediately --
|
|
-- terminates your license. --
|
|
-- --
|
|
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
|
|
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
|
|
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
|
|
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
|
|
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
|
|
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
|
|
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
|
|
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
|
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
|
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
|
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
|
|
-- PARTICULAR PURPOSE. --
|
|
-- --
|
|
-- Xilinx products are not intended for use in life support appliances, --
|
|
-- devices, or systems. Use in such applications are expressly --
|
|
-- prohibited. --
|
|
-- --
|
|
-- (c) Copyright 1995-2013 Xilinx, Inc. --
|
|
-- All rights reserved. --
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- ____ ____
|
|
-- / /\/ /
|
|
-- /___/ \ / Vendor: Xilinx
|
|
-- \ \ \/ Version: O.61xd
|
|
-- \ \ Application: netgen
|
|
-- / / Filename: ctrl_fifo1024x64_st_v1.vhd
|
|
-- /___/ /\ Timestamp: Wed Oct 19 15:05:44 2011
|
|
-- \ \ / \
|
|
-- \___\/\___\
|
|
--
|
|
-- Command : -w -sim -ofmt vhdl D:/TMP/08/SVN/00/block_test_generate/tmp/_cg/ctrl_fifo1024x64_st_v1.ngc D:/TMP/08/SVN/00/block_test_generate/tmp/_cg/ctrl_fifo1024x64_st_v1.vhd
|
|
-- Device : 6slx45tfgg484-3
|
|
-- Input file : D:/TMP/08/SVN/00/block_test_generate/tmp/_cg/ctrl_fifo1024x64_st_v1.ngc
|
|
-- Output file : D:/TMP/08/SVN/00/block_test_generate/tmp/_cg/ctrl_fifo1024x64_st_v1.vhd
|
|
-- # of Entities : 1
|
|
-- Design Name : ctrl_fifo1024x64_st_v1
|
|
-- Xilinx : C:\Xilinx\13.2\ISE_DS\ISE\
|
|
--
|
|
-- Purpose:
|
|
-- This VHDL netlist is a verification model and uses simulation
|
|
-- primitives which may not represent the true implementation of the
|
|
-- device, however the netlist is functionally correct and should not
|
|
-- be modified. This file cannot be synthesized and should only be used
|
|
-- with supported simulation tools.
|
|
--
|
|
-- Reference:
|
|
-- Command Line Tools User Guide, Chapter 23
|
|
-- Synthesis and Simulation Design Guide, Chapter 6
|
|
--
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
-- You must compile the wrapper file ctrl_fifo1024x64_st_v1.vhd when simulating
|
|
-- the core, ctrl_fifo1024x64_st_v1. When compiling the wrapper file, be sure to
|
|
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
|
-- instructions, please refer to the "CORE Generator Help".
|
|
|
|
-- The synthesis directives "translate_off/translate_on" specified
|
|
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
|
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
|
|
|
LIBRARY ieee;
|
|
USE ieee.std_logic_1164.ALL;
|
-- synthesis translate_off
|
-- synthesis translate_off
|
library IEEE;
|
LIBRARY XilinxCoreLib;
|
use IEEE.STD_LOGIC_1164.ALL;
|
-- synthesis translate_on
|
library UNISIM;
|
ENTITY ctrl_fifo1024x64_st_v1 IS
|
use UNISIM.VCOMPONENTS.ALL;
|
PORT (
|
use UNISIM.VPKG.ALL;
|
clk : IN STD_LOGIC;
|
|
rst : IN STD_LOGIC;
|
entity ctrl_fifo1024x64_st_v1 is
|
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
port (
|
wr_en : IN STD_LOGIC;
|
clk : in STD_LOGIC := 'X';
|
rd_en : IN STD_LOGIC;
|
rst : in STD_LOGIC := 'X';
|
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
wr_en : in STD_LOGIC := 'X';
|
full : OUT STD_LOGIC;
|
rd_en : in STD_LOGIC := 'X';
|
empty : OUT STD_LOGIC;
|
full : out STD_LOGIC;
|
prog_full : OUT STD_LOGIC
|
empty : out STD_LOGIC;
|
|
prog_full : out STD_LOGIC;
|
|
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
|
|
dout : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
|
);
|
|
end ctrl_fifo1024x64_st_v1;
|
|
|
|
architecture STRUCTURE of ctrl_fifo1024x64_st_v1 is
|
|
signal N0 : STD_LOGIC;
|
|
signal N1 : STD_LOGIC;
|
|
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_4 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_6 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i_7 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_tmp_ram_rd_en : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_184 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_PWR_39_o_MUX_14_o : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb_GND_294_o_MUX_16_o : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_192 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_193 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_194 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT41 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT81_232 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT103 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_1_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_2_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_3_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_4_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_5_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_6_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_7_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_8_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_9_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_10_Q_243 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_9_Q_244 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_9_Q_245 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_8_Q_246 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_8_Q_247 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_7_Q_248 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_7_Q_249 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_6_Q_250 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_6_Q_251 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_5_Q_252 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_5_Q_253 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_4_Q_254 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_4_Q_255 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_3_Q_256 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_3_Q_257 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_2_Q_258 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_2_Q_259 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_1_Q_260 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_1_Q_261 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_0_Q_262 : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_0_mand1_263 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_1_Q : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_2_Q : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_3_Q : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_4_Q : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_5_Q : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_6_Q : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_7_Q : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_8_Q : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_9_Q : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_10_Q : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_rd_en_i_284 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_wr_en_i_285 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT41 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_1_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_2_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_3_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_4_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_5_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_6_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_7_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_8_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_9_Q : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv : STD_LOGIC;
|
|
signal N01 : STD_LOGIC;
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i_rstpot_298 : STD_LOGIC;
|
|
signal N2 : STD_LOGIC;
|
|
signal N4 : STD_LOGIC;
|
|
signal N6 : STD_LOGIC;
|
|
signal N8 : STD_LOGIC;
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_31_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_30_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_29_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_28_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_27_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_26_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_25_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_24_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_23_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_22_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_21_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_20_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_19_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_18_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_17_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_16_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_15_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_14_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_13_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_12_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_11_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_10_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_9_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_8_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_7_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_6_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_5_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_4_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_3_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_2_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_1_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_0_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_3_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_2_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_1_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_0_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_3_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_2_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_31_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_30_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_29_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_28_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_27_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_26_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_25_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_24_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_23_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_22_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_21_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_20_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_19_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_18_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_17_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_16_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_31_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_30_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_29_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_28_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_27_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_26_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_25_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_24_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_23_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_22_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_21_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_20_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_19_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_18_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_17_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_16_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_15_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_14_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_13_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_12_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_11_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_10_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_9_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_8_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_7_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_6_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_5_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_4_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_3_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_2_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_1_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_0_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_3_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_2_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_1_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_0_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_3_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_2_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_31_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_30_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_29_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_28_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_27_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_26_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_25_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_24_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_23_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_22_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_21_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_20_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_19_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_18_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_17_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_16_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_31_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_30_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_29_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_28_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_27_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_26_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_25_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_24_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_23_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_22_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_21_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_20_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_19_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_18_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_17_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_16_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_15_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_14_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_13_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_12_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_11_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_10_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_9_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_8_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_7_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_6_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_5_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_4_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_3_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_2_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_1_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_0_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_3_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_2_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_1_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_0_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_3_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_2_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_31_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_30_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_29_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_28_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_27_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_26_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_25_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_24_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_23_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_22_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_21_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_20_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_19_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_18_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_17_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_16_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_31_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_30_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_29_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_28_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_27_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_26_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_25_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_24_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_23_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_22_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_21_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_20_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_19_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_18_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_17_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_16_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_15_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_14_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_13_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_12_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_11_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_10_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_9_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_8_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_7_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_6_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_5_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_4_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_3_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_2_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_1_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_0_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_3_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_2_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_1_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_0_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_3_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_2_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_1_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_0_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_31_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_30_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_29_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_28_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_27_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_26_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_25_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_24_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_23_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_22_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_21_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_20_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_19_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_18_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_17_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_16_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_15_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_14_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_13_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_7_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_6_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_5_UNCONNECTED : STD_LOGIC;
|
|
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 0 );
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1 : STD_LOGIC_VECTOR ( 9 downto 1 );
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1 : STD_LOGIC_VECTOR ( 9 downto 0 );
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count : STD_LOGIC_VECTOR ( 9 downto 0 );
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1 : STD_LOGIC_VECTOR ( 0 downto 0 );
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count : STD_LOGIC_VECTOR ( 9 downto 1 );
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
|
|
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad : STD_LOGIC_VECTOR ( 10 downto 1 );
|
|
begin
|
|
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_4;
|
|
empty <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i_7;
|
|
prog_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i;
|
|
XST_VCC : VCC
|
|
port map (
|
|
P => N0
|
|
);
|
|
XST_GND : GND
|
|
port map (
|
|
G => N1
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
|
|
generic map(
|
|
INIT => '1'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_PWR_39_o_MUX_14_o,
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i_7
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
|
|
generic map(
|
|
INIT => '1'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_PWR_39_o_MUX_14_o,
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_6
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDC
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb_GND_294_o_MUX_16_o,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_4
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDC
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb_GND_294_o_MUX_16_o,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_184
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_194,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_193
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_192,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_194
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_194,
|
|
D => N1,
|
|
PRE => rst,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_192
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2 : FDP
|
|
generic map(
|
|
INIT => '1'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
D => N1,
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0 : FDP
|
|
generic map(
|
|
INIT => '1'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
D => N1,
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg_1 : FDP
|
|
generic map(
|
|
INIT => '1'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
D => N1,
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg_0 : FDP
|
|
generic map(
|
|
INIT => '1'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
D => N1,
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_4_gms_ms : MUXCY
|
|
port map (
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet(3),
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(4),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_3_gms_ms : MUXCY
|
|
port map (
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet(2),
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(3),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet(3)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_2_gms_ms : MUXCY
|
|
port map (
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet(1),
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(2),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet(2)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_1_gms_ms : MUXCY
|
|
port map (
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet(0),
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(1),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet(1)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_gm_0_gm1_m1 : MUXCY
|
|
port map (
|
|
CI => N0,
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(0),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_gmux_carrynet(0)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_4_gms_ms : MUXCY
|
|
port map (
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet(3),
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(4),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_3_gms_ms : MUXCY
|
|
port map (
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet(2),
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(3),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet(3)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_2_gms_ms : MUXCY
|
|
port map (
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet(1),
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(2),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet(2)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_1_gms_ms : MUXCY
|
|
port map (
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet(0),
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(1),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet(1)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_gm_0_gm1_m1 : MUXCY
|
|
port map (
|
|
CI => N0,
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(0),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_gmux_carrynet(0)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_4_gms_ms : MUXCY
|
|
port map (
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet(3),
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(4),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_3_gms_ms : MUXCY
|
|
port map (
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet(2),
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(3),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet(3)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_2_gms_ms : MUXCY
|
|
port map (
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet(1),
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(2),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet(2)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_1_gms_ms : MUXCY
|
|
port map (
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet(0),
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(1),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet(1)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_gm_0_gm1_m1 : MUXCY
|
|
port map (
|
|
CI => N0,
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(0),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_gmux_carrynet(0)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_4_gms_ms : MUXCY
|
|
port map (
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet(3),
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(4),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_3_gms_ms : MUXCY
|
|
port map (
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet(2),
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(3),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet(3)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_2_gms_ms : MUXCY
|
|
port map (
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet(1),
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(2),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet(2)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_1_gms_ms : MUXCY
|
|
port map (
|
|
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet(0),
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(1),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet(1)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_gm_0_gm1_m1 : MUXCY
|
|
port map (
|
|
CI => N0,
|
|
DI => N1,
|
|
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(0),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_gmux_carrynet(0)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_9 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(9),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_8 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_7 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_6 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_5 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_4 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_3 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_2 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_1 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_9_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(9)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_8 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_8_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_7 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_7_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_6 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_6_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_5 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_5_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_4 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_4_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_3_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_2 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_2_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_1 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_1_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_0 : FDPE
|
|
generic map(
|
|
INIT => '1'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv,
|
|
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_10_Q :
|
|
XORCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_9_Q_244,
|
|
LI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_10_Q_243
|
|
,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_10_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_9_Q :
|
|
XORCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_8_Q_246,
|
|
LI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_9_Q_245
|
|
,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_9_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_9_Q :
|
|
MUXCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_8_Q_246,
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(8),
|
|
S =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_9_Q_245
|
|
,
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_9_Q_244
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_8_Q :
|
|
XORCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_7_Q_248,
|
|
LI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_8_Q_247
|
|
,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_8_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_8_Q :
|
|
MUXCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_7_Q_248,
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(7),
|
|
S =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_8_Q_247
|
|
,
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_8_Q_246
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_7_Q :
|
|
XORCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_6_Q_250,
|
|
LI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_7_Q_249
|
|
,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_7_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_7_Q :
|
|
MUXCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_6_Q_250,
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6),
|
|
S =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_7_Q_249
|
|
,
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_7_Q_248
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_6_Q :
|
|
XORCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_5_Q_252,
|
|
LI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_6_Q_251
|
|
,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_6_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_6_Q :
|
|
MUXCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_5_Q_252,
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
|
|
S =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_6_Q_251
|
|
,
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_6_Q_250
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_5_Q :
|
|
XORCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_4_Q_254,
|
|
LI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_5_Q_253
|
|
,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_5_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_5_Q :
|
|
MUXCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_4_Q_254,
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
|
|
S =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_5_Q_253
|
|
,
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_5_Q_252
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_4_Q :
|
|
XORCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_3_Q_256,
|
|
LI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_4_Q_255
|
|
,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_4_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_4_Q :
|
|
MUXCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_3_Q_256,
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
|
|
S =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_4_Q_255
|
|
,
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_4_Q_254
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_3_Q :
|
|
XORCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_2_Q_258,
|
|
LI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_3_Q_257
|
|
,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_3_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_3_Q :
|
|
MUXCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_2_Q_258,
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
|
|
S =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_3_Q_257
|
|
,
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_3_Q_256
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_2_Q :
|
|
XORCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_1_Q_260,
|
|
LI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_2_Q_259
|
|
,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_2_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_2_Q :
|
|
MUXCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_1_Q_260,
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
|
|
S =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_2_Q_259
|
|
,
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_2_Q_258
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_xor_1_Q :
|
|
XORCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_0_Q_262,
|
|
LI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_1_Q_261
|
|
,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_1_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_1_Q :
|
|
MUXCY
|
|
port map (
|
|
CI =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_0_Q_262,
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1(0),
|
|
S =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_1_Q_261
|
|
,
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_1_Q_260
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_0_Q :
|
|
MUXCY
|
|
port map (
|
|
CI => N1,
|
|
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_0_mand1_263,
|
|
S => N1,
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_cy_0_Q_262
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_10 : FDC
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_10_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(10)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_9 : FDC
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_9_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(9)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_8 : FDC
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_8_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(8)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_7 : FDC
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_7_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(7)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_6 : FDC
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_6_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(6)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_5 : FDC
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_5_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(5)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_4 : FDC
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_4_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(4)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_3 : FDC
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_3_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(3)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_2 : FDC
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_2_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(2)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_1 : FDC
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_1_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(1)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_rd_en_i : FDC
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_rd_en_i_284
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_wr_en_i : FDC
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_wr_en_i_285
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_9 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(9),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(9)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_8 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(8),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(8)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_7 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(7),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(7)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_6 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(6)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_5 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(5)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_4 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(4)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_3 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_2 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_1 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_0 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1(0),
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_9_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(9)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_8 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_8_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(8)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_7 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_7_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(7)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_6 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_6_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_5 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_5_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_4 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_4_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_3_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_2 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_2_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_1 : FDCE
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_1_Q,
|
|
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_ram_rd_en_i1 : LUT2
|
|
generic map(
|
|
INIT => X"2"
|
|
)
|
|
port map (
|
|
I0 => rd_en,
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_6,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
|
|
generic map(
|
|
INIT => X"2"
|
|
)
|
|
port map (
|
|
I0 => wr_en,
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_184,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_tmp_ram_rd_en1 : LUT3
|
|
generic map(
|
|
INIT => X"F4"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_6,
|
|
I1 => rd_en,
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_tmp_ram_rd_en
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_Mmux_ram_full_comb_GND_294_o_MUX_16_o11 : LUT6
|
|
generic map(
|
|
INIT => X"FA32FAF2F030F0F0"
|
|
)
|
|
port map (
|
|
I0 => wr_en,
|
|
I1 => rd_en,
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_184,
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_6,
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp0,
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb_GND_294_o_MUX_16_o
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_Mmux_going_empty_PWR_39_o_MUX_14_o11 : LUT6
|
|
generic map(
|
|
INIT => X"F3A2FFA2F300FF00"
|
|
)
|
|
port map (
|
|
I0 => rd_en,
|
|
I1 => wr_en,
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_184,
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_6,
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp0,
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_comp1,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_PWR_39_o_MUX_14_o
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
|
|
generic map(
|
|
INIT => X"2"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_192,
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_193,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_4_1 : LUT4
|
|
generic map(
|
|
INIT => X"8421"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(8),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(9),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(4)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_3_1 : LUT4
|
|
generic map(
|
|
INIT => X"8421"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(6),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(7),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(3)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_2_1 : LUT4
|
|
generic map(
|
|
INIT => X"8421"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(4),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(5),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(2)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_1_1 : LUT4
|
|
generic map(
|
|
INIT => X"8421"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(1)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_4_1 : LUT4
|
|
generic map(
|
|
INIT => X"8241"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(9),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(8),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(4)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_3_1 : LUT4
|
|
generic map(
|
|
INIT => X"8241"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(7),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(3)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_2_1 : LUT4
|
|
generic map(
|
|
INIT => X"9009"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(2)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_1_1 : LUT4
|
|
generic map(
|
|
INIT => X"9009"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(1)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_4_1 : LUT4
|
|
generic map(
|
|
INIT => X"8421"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(8),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(9),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(4)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_3_1 : LUT4
|
|
generic map(
|
|
INIT => X"8421"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(6),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(7),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(3)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_2_1 : LUT4
|
|
generic map(
|
|
INIT => X"8421"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(4),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(5),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(2)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_1_1 : LUT4
|
|
generic map(
|
|
INIT => X"8421"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(1)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_4_1 : LUT4
|
|
generic map(
|
|
INIT => X"8241"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(9),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(8),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(9),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(4)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_3_1 : LUT4
|
|
generic map(
|
|
INIT => X"9009"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(7),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(6),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(3)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_2_1 : LUT4
|
|
generic map(
|
|
INIT => X"8241"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(4),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(5),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(2)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_1_1 : LUT4
|
|
generic map(
|
|
INIT => X"9009"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(1)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1_0_1 : LUT4
|
|
generic map(
|
|
INIT => X"9009"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c2_v1(0)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT811 : LUT5
|
|
generic map(
|
|
INIT => X"FFFF7FFF"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT41,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT81_232
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT1031 : LUT5
|
|
generic map(
|
|
INIT => X"00008000"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT41,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT103
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT71 : LUT5
|
|
generic map(
|
|
INIT => X"AAAA6AAA"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT41,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_6_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT21 : LUT2
|
|
generic map(
|
|
INIT => X"6"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_1_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT31 : LUT3
|
|
generic map(
|
|
INIT => X"6A"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_2_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT411 : LUT3
|
|
generic map(
|
|
INIT => X"7F"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT41
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT101 : LUT5
|
|
generic map(
|
|
INIT => X"EAAA6A2A"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(9),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT103,
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT81_232,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_9_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT71 : LUT5
|
|
generic map(
|
|
INIT => X"AAAA6AAA"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT41,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_6_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_9_PWR_45_o_equal_8_o_9_SW0 : LUT5
|
|
generic map(
|
|
INIT => X"FFFFFFFE"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(3),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(8),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(4),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(9),
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(5),
|
|
O => N01
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i : FDC
|
|
generic map(
|
|
INIT => '0'
|
|
)
|
|
port map (
|
|
C => clk,
|
|
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(0),
|
|
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i_rstpot_298,
|
|
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1_0_1 : LUT4
|
|
generic map(
|
|
INIT => X"0990"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c0_v1(0)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1_0_1 : LUT4
|
|
generic map(
|
|
INIT => X"9009"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_v1(0)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1_0_1 : LUT4
|
|
generic map(
|
|
INIT => X"0990"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_c1_v1(0)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT81 : LUT6
|
|
generic map(
|
|
INIT => X"AAAAAAAA6AAAAAAA"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(7),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT41,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_7_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT411 : LUT3
|
|
generic map(
|
|
INIT => X"F7"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT41
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT91_SW0 : LUT2
|
|
generic map(
|
|
INIT => X"7"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(7),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6),
|
|
O => N2
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT91 : LUT6
|
|
generic map(
|
|
INIT => X"AAAAAAAAAAAA6AAA"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(8),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT41,
|
|
I5 => N2,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_8_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT101_SW0 : LUT3
|
|
generic map(
|
|
INIT => X"7F"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(7),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(8),
|
|
O => N4
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT101 : LUT6
|
|
generic map(
|
|
INIT => X"AAAAAAAAAAAA6AAA"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(9),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT41,
|
|
I5 => N4,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_9_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT81 : LUT6
|
|
generic map(
|
|
INIT => X"AAAAAAAA6AAAAAAA"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT41,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_7_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_9_PWR_45_o_equal_8_o_9_SW1 : LUT5
|
|
generic map(
|
|
INIT => X"AAAA8EAA"
|
|
)
|
|
port map (
|
|
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i,
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_wr_en_i_285,
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_rd_en_i_284,
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(10),
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(1),
|
|
O => N6
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i_rstpot : LUT6
|
|
generic map(
|
|
INIT => X"AAAAAAABAAAAAAA8"
|
|
)
|
|
port map (
|
|
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i,
|
|
I1 => N01,
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(7),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(6),
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(2),
|
|
I5 => N6,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i_rstpot_298
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_2_Q :
|
|
LUT2
|
|
generic map(
|
|
INIT => X"9"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_2_Q_259
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_3_Q :
|
|
LUT2
|
|
generic map(
|
|
INIT => X"9"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_3_Q_257
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_4_Q :
|
|
LUT2
|
|
generic map(
|
|
INIT => X"9"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_4_Q_255
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_5_Q :
|
|
LUT2
|
|
generic map(
|
|
INIT => X"9"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_5_Q_253
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_6_Q :
|
|
LUT2
|
|
generic map(
|
|
INIT => X"9"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_6_Q_251
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_7_Q :
|
|
LUT2
|
|
generic map(
|
|
INIT => X"9"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(6),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_7_Q_249
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_8_Q :
|
|
LUT2
|
|
generic map(
|
|
INIT => X"9"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(7),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_8_Q_247
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_9_Q :
|
|
LUT2
|
|
generic map(
|
|
INIT => X"9"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(8),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_9_Q_245
|
|
);
|
);
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_10_Q :
|
END ctrl_fifo1024x64_st_v1;
|
LUT2
|
|
generic map(
|
|
INIT => X"9"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(9),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_10_Q_243
|
|
|
|
|
-- synthesis translate_off
|
|
ARCHITECTURE ctrl_fifo1024x64_st_v1_a OF ctrl_fifo1024x64_st_v1 IS
|
|
COMPONENT wrapped_ctrl_fifo1024x64_st_v1
|
|
PORT (
|
|
clk : IN STD_LOGIC;
|
|
rst : IN STD_LOGIC;
|
|
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
|
wr_en : IN STD_LOGIC;
|
|
rd_en : IN STD_LOGIC;
|
|
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
|
full : OUT STD_LOGIC;
|
|
empty : OUT STD_LOGIC;
|
|
prog_full : OUT STD_LOGIC
|
|
);
|
|
END COMPONENT;
|
|
|
|
-- Configuration specification
|
|
FOR ALL : wrapped_ctrl_fifo1024x64_st_v1 USE ENTITY XilinxCoreLib.fifo_generator_v8_2(behavioral)
|
|
GENERIC MAP (
|
|
c_add_ngc_constraint => 0,
|
|
c_application_type_axis => 0,
|
|
c_application_type_rach => 0,
|
|
c_application_type_rdch => 0,
|
|
c_application_type_wach => 0,
|
|
c_application_type_wdch => 0,
|
|
c_application_type_wrch => 0,
|
|
c_axi_addr_width => 32,
|
|
c_axi_aruser_width => 1,
|
|
c_axi_awuser_width => 1,
|
|
c_axi_buser_width => 1,
|
|
c_axi_data_width => 64,
|
|
c_axi_id_width => 4,
|
|
c_axi_ruser_width => 1,
|
|
c_axi_type => 0,
|
|
c_axi_wuser_width => 1,
|
|
c_axis_tdata_width => 64,
|
|
c_axis_tdest_width => 4,
|
|
c_axis_tid_width => 8,
|
|
c_axis_tkeep_width => 4,
|
|
c_axis_tstrb_width => 4,
|
|
c_axis_tuser_width => 4,
|
|
c_axis_type => 0,
|
|
c_common_clock => 1,
|
|
c_count_type => 0,
|
|
c_data_count_width => 10,
|
|
c_default_value => "BlankString",
|
|
c_din_width => 64,
|
|
c_din_width_axis => 1,
|
|
c_din_width_rach => 32,
|
|
c_din_width_rdch => 64,
|
|
c_din_width_wach => 32,
|
|
c_din_width_wdch => 64,
|
|
c_din_width_wrch => 2,
|
|
c_dout_rst_val => "0",
|
|
c_dout_width => 64,
|
|
c_enable_rlocs => 0,
|
|
c_enable_rst_sync => 1,
|
|
c_error_injection_type => 0,
|
|
c_error_injection_type_axis => 0,
|
|
c_error_injection_type_rach => 0,
|
|
c_error_injection_type_rdch => 0,
|
|
c_error_injection_type_wach => 0,
|
|
c_error_injection_type_wdch => 0,
|
|
c_error_injection_type_wrch => 0,
|
|
c_family => "virtex5",
|
|
c_full_flags_rst_val => 0,
|
|
c_has_almost_empty => 0,
|
|
c_has_almost_full => 0,
|
|
c_has_axi_aruser => 0,
|
|
c_has_axi_awuser => 0,
|
|
c_has_axi_buser => 0,
|
|
c_has_axi_rd_channel => 0,
|
|
c_has_axi_ruser => 0,
|
|
c_has_axi_wr_channel => 0,
|
|
c_has_axi_wuser => 0,
|
|
c_has_axis_tdata => 0,
|
|
c_has_axis_tdest => 0,
|
|
c_has_axis_tid => 0,
|
|
c_has_axis_tkeep => 0,
|
|
c_has_axis_tlast => 0,
|
|
c_has_axis_tready => 1,
|
|
c_has_axis_tstrb => 0,
|
|
c_has_axis_tuser => 0,
|
|
c_has_backup => 0,
|
|
c_has_data_count => 0,
|
|
c_has_data_counts_axis => 0,
|
|
c_has_data_counts_rach => 0,
|
|
c_has_data_counts_rdch => 0,
|
|
c_has_data_counts_wach => 0,
|
|
c_has_data_counts_wdch => 0,
|
|
c_has_data_counts_wrch => 0,
|
|
c_has_int_clk => 0,
|
|
c_has_master_ce => 0,
|
|
c_has_meminit_file => 0,
|
|
c_has_overflow => 0,
|
|
c_has_prog_flags_axis => 0,
|
|
c_has_prog_flags_rach => 0,
|
|
c_has_prog_flags_rdch => 0,
|
|
c_has_prog_flags_wach => 0,
|
|
c_has_prog_flags_wdch => 0,
|
|
c_has_prog_flags_wrch => 0,
|
|
c_has_rd_data_count => 0,
|
|
c_has_rd_rst => 0,
|
|
c_has_rst => 1,
|
|
c_has_slave_ce => 0,
|
|
c_has_srst => 0,
|
|
c_has_underflow => 0,
|
|
c_has_valid => 0,
|
|
c_has_wr_ack => 0,
|
|
c_has_wr_data_count => 0,
|
|
c_has_wr_rst => 0,
|
|
c_implementation_type => 0,
|
|
c_implementation_type_axis => 1,
|
|
c_implementation_type_rach => 1,
|
|
c_implementation_type_rdch => 1,
|
|
c_implementation_type_wach => 1,
|
|
c_implementation_type_wdch => 1,
|
|
c_implementation_type_wrch => 1,
|
|
c_init_wr_pntr_val => 0,
|
|
c_interface_type => 0,
|
|
c_memory_type => 1,
|
|
c_mif_file_name => "BlankString",
|
|
c_msgon_val => 0,
|
|
c_optimization_mode => 0,
|
|
c_overflow_low => 0,
|
|
c_preload_latency => 1,
|
|
c_preload_regs => 0,
|
|
c_prim_fifo_type => "1kx36",
|
|
c_prog_empty_thresh_assert_val => 2,
|
|
c_prog_empty_thresh_assert_val_axis => 1022,
|
|
c_prog_empty_thresh_assert_val_rach => 1022,
|
|
c_prog_empty_thresh_assert_val_rdch => 1022,
|
|
c_prog_empty_thresh_assert_val_wach => 1022,
|
|
c_prog_empty_thresh_assert_val_wdch => 1022,
|
|
c_prog_empty_thresh_assert_val_wrch => 1022,
|
|
c_prog_empty_thresh_negate_val => 3,
|
|
c_prog_empty_type => 0,
|
|
c_prog_empty_type_axis => 0,
|
|
c_prog_empty_type_rach => 0,
|
|
c_prog_empty_type_rdch => 0,
|
|
c_prog_empty_type_wach => 0,
|
|
c_prog_empty_type_wdch => 0,
|
|
c_prog_empty_type_wrch => 0,
|
|
c_prog_full_thresh_assert_val => 512,
|
|
c_prog_full_thresh_assert_val_axis => 1023,
|
|
c_prog_full_thresh_assert_val_rach => 1023,
|
|
c_prog_full_thresh_assert_val_rdch => 1023,
|
|
c_prog_full_thresh_assert_val_wach => 1023,
|
|
c_prog_full_thresh_assert_val_wdch => 1023,
|
|
c_prog_full_thresh_assert_val_wrch => 1023,
|
|
c_prog_full_thresh_negate_val => 511,
|
|
c_prog_full_type => 1,
|
|
c_prog_full_type_axis => 0,
|
|
c_prog_full_type_rach => 0,
|
|
c_prog_full_type_rdch => 0,
|
|
c_prog_full_type_wach => 0,
|
|
c_prog_full_type_wdch => 0,
|
|
c_prog_full_type_wrch => 0,
|
|
c_rach_type => 0,
|
|
c_rd_data_count_width => 10,
|
|
c_rd_depth => 1024,
|
|
c_rd_freq => 1,
|
|
c_rd_pntr_width => 10,
|
|
c_rdch_type => 0,
|
|
c_reg_slice_mode_axis => 0,
|
|
c_reg_slice_mode_rach => 0,
|
|
c_reg_slice_mode_rdch => 0,
|
|
c_reg_slice_mode_wach => 0,
|
|
c_reg_slice_mode_wdch => 0,
|
|
c_reg_slice_mode_wrch => 0,
|
|
--c_synchronizer_stage => 2,
|
|
c_underflow_low => 0,
|
|
c_use_common_overflow => 0,
|
|
c_use_common_underflow => 0,
|
|
c_use_default_settings => 0,
|
|
c_use_dout_rst => 1,
|
|
c_use_ecc => 0,
|
|
c_use_ecc_axis => 0,
|
|
c_use_ecc_rach => 0,
|
|
c_use_ecc_rdch => 0,
|
|
c_use_ecc_wach => 0,
|
|
c_use_ecc_wdch => 0,
|
|
c_use_ecc_wrch => 0,
|
|
c_use_embedded_reg => 0,
|
|
c_use_fifo16_flags => 0,
|
|
c_use_fwft_data_count => 0,
|
|
c_valid_low => 0,
|
|
c_wach_type => 0,
|
|
c_wdch_type => 0,
|
|
c_wr_ack_low => 0,
|
|
c_wr_data_count_width => 10,
|
|
c_wr_depth => 1024,
|
|
c_wr_depth_axis => 1024,
|
|
c_wr_depth_rach => 16,
|
|
c_wr_depth_rdch => 1024,
|
|
c_wr_depth_wach => 16,
|
|
c_wr_depth_wdch => 1024,
|
|
c_wr_depth_wrch => 16,
|
|
c_wr_freq => 1,
|
|
c_wr_pntr_width => 10,
|
|
c_wr_pntr_width_axis => 10,
|
|
c_wr_pntr_width_rach => 4,
|
|
c_wr_pntr_width_rdch => 10,
|
|
c_wr_pntr_width_wach => 4,
|
|
c_wr_pntr_width_wdch => 10,
|
|
c_wr_pntr_width_wrch => 4,
|
|
c_wr_response_latency => 1,
|
|
c_wrch_type => 0
|
|
);
|
|
BEGIN
|
|
U0 : wrapped_ctrl_fifo1024x64_st_v1
|
|
PORT MAP (
|
|
clk => clk,
|
|
rst => rst,
|
|
din => din,
|
|
wr_en => wr_en,
|
|
rd_en => rd_en,
|
|
dout => dout,
|
|
full => full,
|
|
empty => empty,
|
|
prog_full => prog_full
|
);
|
);
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_0_mand1 : LUT4
|
|
generic map(
|
|
INIT => X"4044"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_184,
|
|
I1 => wr_en,
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_6,
|
|
I3 => rd_en,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_0_mand1_263
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_1_Q :
|
|
LUT2
|
|
generic map(
|
|
INIT => X"9"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
|
|
O =>
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_10_rd_pntr_wr_inv_pad_10_add_2_OUT_lut_1_Q_261
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT61 : LUT6
|
|
generic map(
|
|
INIT => X"6AAAAAAAAAAAAAAA"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_5_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT42 : LUT4
|
|
generic map(
|
|
INIT => X"6AAA"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_3_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT51 : LUT5
|
|
generic map(
|
|
INIT => X"6AAAAAAA"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_4_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT61 : LUT6
|
|
generic map(
|
|
INIT => X"AAAAAAAA6AAAAAAA"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(5),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_5_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT42 : LUT4
|
|
generic map(
|
|
INIT => X"AA6A"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_3_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT51 : LUT5
|
|
generic map(
|
|
INIT => X"AAAA6AAA"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(4),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_4_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT21 : LUT2
|
|
generic map(
|
|
INIT => X"9"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_1_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mmux_gcc0_gc0_count_9_GND_292_o_mux_2_OUT31 : LUT3
|
|
generic map(
|
|
INIT => X"A6"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_9_GND_292_o_mux_2_OUT_2_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT91_F : LUT6
|
|
generic map(
|
|
INIT => X"6AAAAAAAAAAAAAAA"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8),
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(6),
|
|
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
|
|
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(4),
|
|
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(5),
|
|
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(7),
|
|
O => N8
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT11_INV_0 : INV
|
|
port map (
|
|
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(0),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_wr_pntr_0_inv1_INV_0 : INV
|
|
port map (
|
|
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1(0)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT911 : LUT3
|
|
generic map(
|
|
INIT => X"D8"
|
|
)
|
|
port map (
|
|
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mmux_gc0_count_9_GND_281_o_mux_2_OUT41,
|
|
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(8),
|
|
I2 => N8,
|
|
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_9_GND_281_o_mux_2_OUT_8_Q
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram :
|
|
RAMB16BWER
|
|
generic map(
|
|
DATA_WIDTH_A => 18,
|
|
DATA_WIDTH_B => 18,
|
|
DOA_REG => 0,
|
|
DOB_REG => 0,
|
|
EN_RSTRAM_A => FALSE,
|
|
EN_RSTRAM_B => TRUE,
|
|
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_A => X"000000000",
|
|
INIT_B => X"000000000",
|
|
INIT_FILE => "NONE",
|
|
RSTTYPE => "SYNC",
|
|
RST_PRIORITY_A => "CE",
|
|
RST_PRIORITY_B => "CE",
|
|
SIM_COLLISION_CHECK => "ALL",
|
|
SIM_DEVICE => "SPARTAN6",
|
|
SRVAL_A => X"000000000",
|
|
SRVAL_B => X"000000000",
|
|
WRITE_MODE_A => "READ_FIRST",
|
|
WRITE_MODE_B => "READ_FIRST"
|
|
)
|
|
port map (
|
|
REGCEA => N1,
|
|
CLKA => clk,
|
|
ENB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_tmp_ram_rd_en,
|
|
RSTB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q,
|
|
CLKB => clk,
|
|
REGCEB => N1,
|
|
RSTA => N1,
|
|
ENA => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
DIPA(3) => N1,
|
|
DIPA(2) => N1,
|
|
DIPA(1) => din(17),
|
|
DIPA(0) => din(8),
|
|
WEA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
WEA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
WEA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
WEA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
DOA(31) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_31_UNCONNECTED
|
|
,
|
|
DOA(30) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_30_UNCONNECTED
|
|
,
|
|
DOA(29) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_29_UNCONNECTED
|
|
,
|
|
DOA(28) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_28_UNCONNECTED
|
|
,
|
|
DOA(27) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_27_UNCONNECTED
|
|
,
|
|
DOA(26) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_26_UNCONNECTED
|
|
,
|
|
DOA(25) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_25_UNCONNECTED
|
|
,
|
|
DOA(24) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_24_UNCONNECTED
|
|
,
|
|
DOA(23) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_23_UNCONNECTED
|
|
,
|
|
DOA(22) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_22_UNCONNECTED
|
|
,
|
|
DOA(21) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_21_UNCONNECTED
|
|
,
|
|
DOA(20) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_20_UNCONNECTED
|
|
,
|
|
DOA(19) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_19_UNCONNECTED
|
|
,
|
|
DOA(18) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_18_UNCONNECTED
|
|
,
|
|
DOA(17) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_17_UNCONNECTED
|
|
,
|
|
DOA(16) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_16_UNCONNECTED
|
|
,
|
|
DOA(15) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_15_UNCONNECTED
|
|
,
|
|
DOA(14) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_14_UNCONNECTED
|
|
,
|
|
DOA(13) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_13_UNCONNECTED
|
|
,
|
|
DOA(12) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_12_UNCONNECTED
|
|
,
|
|
DOA(11) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_11_UNCONNECTED
|
|
,
|
|
DOA(10) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_10_UNCONNECTED
|
|
,
|
|
DOA(9) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_9_UNCONNECTED
|
|
,
|
|
DOA(8) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_8_UNCONNECTED
|
|
,
|
|
DOA(7) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_7_UNCONNECTED
|
|
,
|
|
DOA(6) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_6_UNCONNECTED
|
|
,
|
|
DOA(5) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_5_UNCONNECTED
|
|
,
|
|
DOA(4) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_4_UNCONNECTED
|
|
,
|
|
DOA(3) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_3_UNCONNECTED
|
|
,
|
|
DOA(2) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_2_UNCONNECTED
|
|
,
|
|
DOA(1) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_1_UNCONNECTED
|
|
,
|
|
DOA(0) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_0_UNCONNECTED
|
|
,
|
|
ADDRA(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(9),
|
|
ADDRA(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(8),
|
|
ADDRA(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(7),
|
|
ADDRA(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(6),
|
|
ADDRA(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(5),
|
|
ADDRA(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(4),
|
|
ADDRA(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
|
|
ADDRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
|
|
ADDRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
|
|
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
|
|
ADDRA(3) => N1,
|
|
ADDRA(2) => N1,
|
|
ADDRA(1) => N1,
|
|
ADDRA(0) => N1,
|
|
ADDRB(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
|
|
ADDRB(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
|
|
ADDRB(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
|
|
ADDRB(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
|
ADDRB(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
|
ADDRB(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
|
ADDRB(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
|
ADDRB(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
|
ADDRB(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
|
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv,
|
|
ADDRB(3) => N1,
|
|
ADDRB(2) => N1,
|
|
ADDRB(1) => N1,
|
|
ADDRB(0) => N1,
|
|
DIB(31) => N1,
|
|
DIB(30) => N1,
|
|
DIB(29) => N1,
|
|
DIB(28) => N1,
|
|
DIB(27) => N1,
|
|
DIB(26) => N1,
|
|
DIB(25) => N1,
|
|
DIB(24) => N1,
|
|
DIB(23) => N1,
|
|
DIB(22) => N1,
|
|
DIB(21) => N1,
|
|
DIB(20) => N1,
|
|
DIB(19) => N1,
|
|
DIB(18) => N1,
|
|
DIB(17) => N1,
|
|
DIB(16) => N1,
|
|
DIB(15) => N1,
|
|
DIB(14) => N1,
|
|
DIB(13) => N1,
|
|
DIB(12) => N1,
|
|
DIB(11) => N1,
|
|
DIB(10) => N1,
|
|
DIB(9) => N1,
|
|
DIB(8) => N1,
|
|
DIB(7) => N1,
|
|
DIB(6) => N1,
|
|
DIB(5) => N1,
|
|
DIB(4) => N1,
|
|
DIB(3) => N1,
|
|
DIB(2) => N1,
|
|
DIB(1) => N1,
|
|
DIB(0) => N1,
|
|
DOPA(3) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_3_UNCONNECTED
|
|
,
|
|
DOPA(2) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_2_UNCONNECTED
|
|
,
|
|
DOPA(1) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_1_UNCONNECTED
|
|
,
|
|
DOPA(0) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_0_UNCONNECTED
|
|
,
|
|
DIPB(3) => N1,
|
|
DIPB(2) => N1,
|
|
DIPB(1) => N1,
|
|
DIPB(0) => N1,
|
|
DOPB(3) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_3_UNCONNECTED
|
|
,
|
|
DOPB(2) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_2_UNCONNECTED
|
|
,
|
|
DOPB(1) => dout(17),
|
|
DOPB(0) => dout(8),
|
|
DOB(31) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_31_UNCONNECTED
|
|
,
|
|
DOB(30) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_30_UNCONNECTED
|
|
,
|
|
DOB(29) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_29_UNCONNECTED
|
|
,
|
|
DOB(28) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_28_UNCONNECTED
|
|
,
|
|
DOB(27) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_27_UNCONNECTED
|
|
,
|
|
DOB(26) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_26_UNCONNECTED
|
|
,
|
|
DOB(25) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_25_UNCONNECTED
|
|
,
|
|
DOB(24) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_24_UNCONNECTED
|
|
,
|
|
DOB(23) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_23_UNCONNECTED
|
|
,
|
|
DOB(22) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_22_UNCONNECTED
|
|
,
|
|
DOB(21) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_21_UNCONNECTED
|
|
,
|
|
DOB(20) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_20_UNCONNECTED
|
|
,
|
|
DOB(19) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_19_UNCONNECTED
|
|
,
|
|
DOB(18) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_18_UNCONNECTED
|
|
,
|
|
DOB(17) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_17_UNCONNECTED
|
|
,
|
|
DOB(16) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_16_UNCONNECTED
|
|
,
|
|
DOB(15) => dout(16),
|
|
DOB(14) => dout(15),
|
|
DOB(13) => dout(14),
|
|
DOB(12) => dout(13),
|
|
DOB(11) => dout(12),
|
|
DOB(10) => dout(11),
|
|
DOB(9) => dout(10),
|
|
DOB(8) => dout(9),
|
|
DOB(7) => dout(7),
|
|
DOB(6) => dout(6),
|
|
DOB(5) => dout(5),
|
|
DOB(4) => dout(4),
|
|
DOB(3) => dout(3),
|
|
DOB(2) => dout(2),
|
|
DOB(1) => dout(1),
|
|
DOB(0) => dout(0),
|
|
WEB(3) => N1,
|
|
WEB(2) => N1,
|
|
WEB(1) => N1,
|
|
WEB(0) => N1,
|
|
DIA(31) => N1,
|
|
DIA(30) => N1,
|
|
DIA(29) => N1,
|
|
DIA(28) => N1,
|
|
DIA(27) => N1,
|
|
DIA(26) => N1,
|
|
DIA(25) => N1,
|
|
DIA(24) => N1,
|
|
DIA(23) => N1,
|
|
DIA(22) => N1,
|
|
DIA(21) => N1,
|
|
DIA(20) => N1,
|
|
DIA(19) => N1,
|
|
DIA(18) => N1,
|
|
DIA(17) => N1,
|
|
DIA(16) => N1,
|
|
DIA(15) => din(16),
|
|
DIA(14) => din(15),
|
|
DIA(13) => din(14),
|
|
DIA(12) => din(13),
|
|
DIA(11) => din(12),
|
|
DIA(10) => din(11),
|
|
DIA(9) => din(10),
|
|
DIA(8) => din(9),
|
|
DIA(7) => din(7),
|
|
DIA(6) => din(6),
|
|
DIA(5) => din(5),
|
|
DIA(4) => din(4),
|
|
DIA(3) => din(3),
|
|
DIA(2) => din(2),
|
|
DIA(1) => din(1),
|
|
DIA(0) => din(0)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram :
|
|
RAMB16BWER
|
|
generic map(
|
|
DATA_WIDTH_A => 18,
|
|
DATA_WIDTH_B => 18,
|
|
DOA_REG => 0,
|
|
DOB_REG => 0,
|
|
EN_RSTRAM_A => FALSE,
|
|
EN_RSTRAM_B => TRUE,
|
|
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_A => X"000000000",
|
|
INIT_B => X"000000000",
|
|
INIT_FILE => "NONE",
|
|
RSTTYPE => "SYNC",
|
|
RST_PRIORITY_A => "CE",
|
|
RST_PRIORITY_B => "CE",
|
|
SIM_COLLISION_CHECK => "ALL",
|
|
SIM_DEVICE => "SPARTAN6",
|
|
SRVAL_A => X"000000000",
|
|
SRVAL_B => X"000000000",
|
|
WRITE_MODE_A => "READ_FIRST",
|
|
WRITE_MODE_B => "READ_FIRST"
|
|
)
|
|
port map (
|
|
REGCEA => N1,
|
|
CLKA => clk,
|
|
ENB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_tmp_ram_rd_en,
|
|
RSTB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q,
|
|
CLKB => clk,
|
|
REGCEB => N1,
|
|
RSTA => N1,
|
|
ENA => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
DIPA(3) => N1,
|
|
DIPA(2) => N1,
|
|
DIPA(1) => din(35),
|
|
DIPA(0) => din(26),
|
|
WEA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
WEA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
WEA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
WEA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
DOA(31) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_31_UNCONNECTED
|
|
,
|
|
DOA(30) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_30_UNCONNECTED
|
|
,
|
|
DOA(29) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_29_UNCONNECTED
|
|
,
|
|
DOA(28) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_28_UNCONNECTED
|
|
,
|
|
DOA(27) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_27_UNCONNECTED
|
|
,
|
|
DOA(26) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_26_UNCONNECTED
|
|
,
|
|
DOA(25) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_25_UNCONNECTED
|
|
,
|
|
DOA(24) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_24_UNCONNECTED
|
|
,
|
|
DOA(23) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_23_UNCONNECTED
|
|
,
|
|
DOA(22) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_22_UNCONNECTED
|
|
,
|
|
DOA(21) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_21_UNCONNECTED
|
|
,
|
|
DOA(20) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_20_UNCONNECTED
|
|
,
|
|
DOA(19) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_19_UNCONNECTED
|
|
,
|
|
DOA(18) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_18_UNCONNECTED
|
|
,
|
|
DOA(17) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_17_UNCONNECTED
|
|
,
|
|
DOA(16) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_16_UNCONNECTED
|
|
,
|
|
DOA(15) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_15_UNCONNECTED
|
|
,
|
|
DOA(14) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_14_UNCONNECTED
|
|
,
|
|
DOA(13) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_13_UNCONNECTED
|
|
,
|
|
DOA(12) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_12_UNCONNECTED
|
|
,
|
|
DOA(11) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_11_UNCONNECTED
|
|
,
|
|
DOA(10) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_10_UNCONNECTED
|
|
,
|
|
DOA(9) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_9_UNCONNECTED
|
|
,
|
|
DOA(8) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_8_UNCONNECTED
|
|
,
|
|
DOA(7) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_7_UNCONNECTED
|
|
,
|
|
DOA(6) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_6_UNCONNECTED
|
|
,
|
|
DOA(5) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_5_UNCONNECTED
|
|
,
|
|
DOA(4) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_4_UNCONNECTED
|
|
,
|
|
DOA(3) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_3_UNCONNECTED
|
|
,
|
|
DOA(2) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_2_UNCONNECTED
|
|
,
|
|
DOA(1) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_1_UNCONNECTED
|
|
,
|
|
DOA(0) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_0_UNCONNECTED
|
|
,
|
|
ADDRA(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(9),
|
|
ADDRA(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(8),
|
|
ADDRA(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(7),
|
|
ADDRA(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(6),
|
|
ADDRA(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(5),
|
|
ADDRA(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(4),
|
|
ADDRA(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
|
|
ADDRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
|
|
ADDRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
|
|
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
|
|
ADDRA(3) => N1,
|
|
ADDRA(2) => N1,
|
|
ADDRA(1) => N1,
|
|
ADDRA(0) => N1,
|
|
ADDRB(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
|
|
ADDRB(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
|
|
ADDRB(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
|
|
ADDRB(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
|
ADDRB(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
|
ADDRB(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
|
ADDRB(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
|
ADDRB(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
|
ADDRB(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
|
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv,
|
|
ADDRB(3) => N1,
|
|
ADDRB(2) => N1,
|
|
ADDRB(1) => N1,
|
|
ADDRB(0) => N1,
|
|
DIB(31) => N1,
|
|
DIB(30) => N1,
|
|
DIB(29) => N1,
|
|
DIB(28) => N1,
|
|
DIB(27) => N1,
|
|
DIB(26) => N1,
|
|
DIB(25) => N1,
|
|
DIB(24) => N1,
|
|
DIB(23) => N1,
|
|
DIB(22) => N1,
|
|
DIB(21) => N1,
|
|
DIB(20) => N1,
|
|
DIB(19) => N1,
|
|
DIB(18) => N1,
|
|
DIB(17) => N1,
|
|
DIB(16) => N1,
|
|
DIB(15) => N1,
|
|
DIB(14) => N1,
|
|
DIB(13) => N1,
|
|
DIB(12) => N1,
|
|
DIB(11) => N1,
|
|
DIB(10) => N1,
|
|
DIB(9) => N1,
|
|
DIB(8) => N1,
|
|
DIB(7) => N1,
|
|
DIB(6) => N1,
|
|
DIB(5) => N1,
|
|
DIB(4) => N1,
|
|
DIB(3) => N1,
|
|
DIB(2) => N1,
|
|
DIB(1) => N1,
|
|
DIB(0) => N1,
|
|
DOPA(3) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_3_UNCONNECTED
|
|
,
|
|
DOPA(2) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_2_UNCONNECTED
|
|
,
|
|
DOPA(1) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_1_UNCONNECTED
|
|
,
|
|
DOPA(0) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_0_UNCONNECTED
|
|
,
|
|
DIPB(3) => N1,
|
|
DIPB(2) => N1,
|
|
DIPB(1) => N1,
|
|
DIPB(0) => N1,
|
|
DOPB(3) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_3_UNCONNECTED
|
|
,
|
|
DOPB(2) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_2_UNCONNECTED
|
|
,
|
|
DOPB(1) => dout(35),
|
|
DOPB(0) => dout(26),
|
|
DOB(31) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_31_UNCONNECTED
|
|
,
|
|
DOB(30) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_30_UNCONNECTED
|
|
,
|
|
DOB(29) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_29_UNCONNECTED
|
|
,
|
|
DOB(28) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_28_UNCONNECTED
|
|
,
|
|
DOB(27) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_27_UNCONNECTED
|
|
,
|
|
DOB(26) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_26_UNCONNECTED
|
|
,
|
|
DOB(25) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_25_UNCONNECTED
|
|
,
|
|
DOB(24) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_24_UNCONNECTED
|
|
,
|
|
DOB(23) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_23_UNCONNECTED
|
|
,
|
|
DOB(22) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_22_UNCONNECTED
|
|
,
|
|
DOB(21) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_21_UNCONNECTED
|
|
,
|
|
DOB(20) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_20_UNCONNECTED
|
|
,
|
|
DOB(19) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_19_UNCONNECTED
|
|
,
|
|
DOB(18) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_18_UNCONNECTED
|
|
,
|
|
DOB(17) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_17_UNCONNECTED
|
|
,
|
|
DOB(16) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_16_UNCONNECTED
|
|
,
|
|
DOB(15) => dout(34),
|
|
DOB(14) => dout(33),
|
|
DOB(13) => dout(32),
|
|
DOB(12) => dout(31),
|
|
DOB(11) => dout(30),
|
|
DOB(10) => dout(29),
|
|
DOB(9) => dout(28),
|
|
DOB(8) => dout(27),
|
|
DOB(7) => dout(25),
|
|
DOB(6) => dout(24),
|
|
DOB(5) => dout(23),
|
|
DOB(4) => dout(22),
|
|
DOB(3) => dout(21),
|
|
DOB(2) => dout(20),
|
|
DOB(1) => dout(19),
|
|
DOB(0) => dout(18),
|
|
WEB(3) => N1,
|
|
WEB(2) => N1,
|
|
WEB(1) => N1,
|
|
WEB(0) => N1,
|
|
DIA(31) => N1,
|
|
DIA(30) => N1,
|
|
DIA(29) => N1,
|
|
DIA(28) => N1,
|
|
DIA(27) => N1,
|
|
DIA(26) => N1,
|
|
DIA(25) => N1,
|
|
DIA(24) => N1,
|
|
DIA(23) => N1,
|
|
DIA(22) => N1,
|
|
DIA(21) => N1,
|
|
DIA(20) => N1,
|
|
DIA(19) => N1,
|
|
DIA(18) => N1,
|
|
DIA(17) => N1,
|
|
DIA(16) => N1,
|
|
DIA(15) => din(34),
|
|
DIA(14) => din(33),
|
|
DIA(13) => din(32),
|
|
DIA(12) => din(31),
|
|
DIA(11) => din(30),
|
|
DIA(10) => din(29),
|
|
DIA(9) => din(28),
|
|
DIA(8) => din(27),
|
|
DIA(7) => din(25),
|
|
DIA(6) => din(24),
|
|
DIA(5) => din(23),
|
|
DIA(4) => din(22),
|
|
DIA(3) => din(21),
|
|
DIA(2) => din(20),
|
|
DIA(1) => din(19),
|
|
DIA(0) => din(18)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram :
|
|
RAMB16BWER
|
|
generic map(
|
|
DATA_WIDTH_A => 18,
|
|
DATA_WIDTH_B => 18,
|
|
DOA_REG => 0,
|
|
DOB_REG => 0,
|
|
EN_RSTRAM_A => FALSE,
|
|
EN_RSTRAM_B => TRUE,
|
|
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_A => X"000000000",
|
|
INIT_B => X"000000000",
|
|
INIT_FILE => "NONE",
|
|
RSTTYPE => "SYNC",
|
|
RST_PRIORITY_A => "CE",
|
|
RST_PRIORITY_B => "CE",
|
|
SIM_COLLISION_CHECK => "ALL",
|
|
SIM_DEVICE => "SPARTAN6",
|
|
SRVAL_A => X"000000000",
|
|
SRVAL_B => X"000000000",
|
|
WRITE_MODE_A => "READ_FIRST",
|
|
WRITE_MODE_B => "READ_FIRST"
|
|
)
|
|
port map (
|
|
REGCEA => N1,
|
|
CLKA => clk,
|
|
ENB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_tmp_ram_rd_en,
|
|
RSTB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q,
|
|
CLKB => clk,
|
|
REGCEB => N1,
|
|
RSTA => N1,
|
|
ENA => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
DIPA(3) => N1,
|
|
DIPA(2) => N1,
|
|
DIPA(1) => din(53),
|
|
DIPA(0) => din(44),
|
|
WEA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
WEA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
WEA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
WEA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
DOA(31) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_31_UNCONNECTED
|
|
,
|
|
DOA(30) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_30_UNCONNECTED
|
|
,
|
|
DOA(29) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_29_UNCONNECTED
|
|
,
|
|
DOA(28) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_28_UNCONNECTED
|
|
,
|
|
DOA(27) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_27_UNCONNECTED
|
|
,
|
|
DOA(26) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_26_UNCONNECTED
|
|
,
|
|
DOA(25) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_25_UNCONNECTED
|
|
,
|
|
DOA(24) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_24_UNCONNECTED
|
|
,
|
|
DOA(23) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_23_UNCONNECTED
|
|
,
|
|
DOA(22) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_22_UNCONNECTED
|
|
,
|
|
DOA(21) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_21_UNCONNECTED
|
|
,
|
|
DOA(20) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_20_UNCONNECTED
|
|
,
|
|
DOA(19) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_19_UNCONNECTED
|
|
,
|
|
DOA(18) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_18_UNCONNECTED
|
|
,
|
|
DOA(17) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_17_UNCONNECTED
|
|
,
|
|
DOA(16) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_16_UNCONNECTED
|
|
,
|
|
DOA(15) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_15_UNCONNECTED
|
|
,
|
|
DOA(14) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_14_UNCONNECTED
|
|
,
|
|
DOA(13) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_13_UNCONNECTED
|
|
,
|
|
DOA(12) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_12_UNCONNECTED
|
|
,
|
|
DOA(11) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_11_UNCONNECTED
|
|
,
|
|
DOA(10) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_10_UNCONNECTED
|
|
,
|
|
DOA(9) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_9_UNCONNECTED
|
|
,
|
|
DOA(8) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_8_UNCONNECTED
|
|
,
|
|
DOA(7) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_7_UNCONNECTED
|
|
,
|
|
DOA(6) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_6_UNCONNECTED
|
|
,
|
|
DOA(5) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_5_UNCONNECTED
|
|
,
|
|
DOA(4) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_4_UNCONNECTED
|
|
,
|
|
DOA(3) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_3_UNCONNECTED
|
|
,
|
|
DOA(2) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_2_UNCONNECTED
|
|
,
|
|
DOA(1) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_1_UNCONNECTED
|
|
,
|
|
DOA(0) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_0_UNCONNECTED
|
|
,
|
|
ADDRA(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(9),
|
|
ADDRA(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(8),
|
|
ADDRA(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(7),
|
|
ADDRA(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(6),
|
|
ADDRA(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(5),
|
|
ADDRA(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(4),
|
|
ADDRA(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
|
|
ADDRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
|
|
ADDRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
|
|
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
|
|
ADDRA(3) => N1,
|
|
ADDRA(2) => N1,
|
|
ADDRA(1) => N1,
|
|
ADDRA(0) => N1,
|
|
ADDRB(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
|
|
ADDRB(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
|
|
ADDRB(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
|
|
ADDRB(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
|
ADDRB(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
|
ADDRB(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
|
ADDRB(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
|
ADDRB(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
|
ADDRB(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
|
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv,
|
|
ADDRB(3) => N1,
|
|
ADDRB(2) => N1,
|
|
ADDRB(1) => N1,
|
|
ADDRB(0) => N1,
|
|
DIB(31) => N1,
|
|
DIB(30) => N1,
|
|
DIB(29) => N1,
|
|
DIB(28) => N1,
|
|
DIB(27) => N1,
|
|
DIB(26) => N1,
|
|
DIB(25) => N1,
|
|
DIB(24) => N1,
|
|
DIB(23) => N1,
|
|
DIB(22) => N1,
|
|
DIB(21) => N1,
|
|
DIB(20) => N1,
|
|
DIB(19) => N1,
|
|
DIB(18) => N1,
|
|
DIB(17) => N1,
|
|
DIB(16) => N1,
|
|
DIB(15) => N1,
|
|
DIB(14) => N1,
|
|
DIB(13) => N1,
|
|
DIB(12) => N1,
|
|
DIB(11) => N1,
|
|
DIB(10) => N1,
|
|
DIB(9) => N1,
|
|
DIB(8) => N1,
|
|
DIB(7) => N1,
|
|
DIB(6) => N1,
|
|
DIB(5) => N1,
|
|
DIB(4) => N1,
|
|
DIB(3) => N1,
|
|
DIB(2) => N1,
|
|
DIB(1) => N1,
|
|
DIB(0) => N1,
|
|
DOPA(3) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_3_UNCONNECTED
|
|
,
|
|
DOPA(2) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_2_UNCONNECTED
|
|
,
|
|
DOPA(1) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_1_UNCONNECTED
|
|
,
|
|
DOPA(0) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_0_UNCONNECTED
|
|
,
|
|
DIPB(3) => N1,
|
|
DIPB(2) => N1,
|
|
DIPB(1) => N1,
|
|
DIPB(0) => N1,
|
|
DOPB(3) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_3_UNCONNECTED
|
|
,
|
|
DOPB(2) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_2_UNCONNECTED
|
|
,
|
|
DOPB(1) => dout(53),
|
|
DOPB(0) => dout(44),
|
|
DOB(31) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_31_UNCONNECTED
|
|
,
|
|
DOB(30) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_30_UNCONNECTED
|
|
,
|
|
DOB(29) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_29_UNCONNECTED
|
|
,
|
|
DOB(28) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_28_UNCONNECTED
|
|
,
|
|
DOB(27) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_27_UNCONNECTED
|
|
,
|
|
DOB(26) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_26_UNCONNECTED
|
|
,
|
|
DOB(25) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_25_UNCONNECTED
|
|
,
|
|
DOB(24) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_24_UNCONNECTED
|
|
,
|
|
DOB(23) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_23_UNCONNECTED
|
|
,
|
|
DOB(22) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_22_UNCONNECTED
|
|
,
|
|
DOB(21) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_21_UNCONNECTED
|
|
,
|
|
DOB(20) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_20_UNCONNECTED
|
|
,
|
|
DOB(19) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_19_UNCONNECTED
|
|
,
|
|
DOB(18) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_18_UNCONNECTED
|
|
,
|
|
DOB(17) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_17_UNCONNECTED
|
|
,
|
|
DOB(16) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_16_UNCONNECTED
|
|
,
|
|
DOB(15) => dout(52),
|
|
DOB(14) => dout(51),
|
|
DOB(13) => dout(50),
|
|
DOB(12) => dout(49),
|
|
DOB(11) => dout(48),
|
|
DOB(10) => dout(47),
|
|
DOB(9) => dout(46),
|
|
DOB(8) => dout(45),
|
|
DOB(7) => dout(43),
|
|
DOB(6) => dout(42),
|
|
DOB(5) => dout(41),
|
|
DOB(4) => dout(40),
|
|
DOB(3) => dout(39),
|
|
DOB(2) => dout(38),
|
|
DOB(1) => dout(37),
|
|
DOB(0) => dout(36),
|
|
WEB(3) => N1,
|
|
WEB(2) => N1,
|
|
WEB(1) => N1,
|
|
WEB(0) => N1,
|
|
DIA(31) => N1,
|
|
DIA(30) => N1,
|
|
DIA(29) => N1,
|
|
DIA(28) => N1,
|
|
DIA(27) => N1,
|
|
DIA(26) => N1,
|
|
DIA(25) => N1,
|
|
DIA(24) => N1,
|
|
DIA(23) => N1,
|
|
DIA(22) => N1,
|
|
DIA(21) => N1,
|
|
DIA(20) => N1,
|
|
DIA(19) => N1,
|
|
DIA(18) => N1,
|
|
DIA(17) => N1,
|
|
DIA(16) => N1,
|
|
DIA(15) => din(52),
|
|
DIA(14) => din(51),
|
|
DIA(13) => din(50),
|
|
DIA(12) => din(49),
|
|
DIA(11) => din(48),
|
|
DIA(10) => din(47),
|
|
DIA(9) => din(46),
|
|
DIA(8) => din(45),
|
|
DIA(7) => din(43),
|
|
DIA(6) => din(42),
|
|
DIA(5) => din(41),
|
|
DIA(4) => din(40),
|
|
DIA(3) => din(39),
|
|
DIA(2) => din(38),
|
|
DIA(1) => din(37),
|
|
DIA(0) => din(36)
|
|
);
|
|
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram :
|
|
RAMB16BWER
|
|
generic map(
|
|
DATA_WIDTH_A => 18,
|
|
DATA_WIDTH_B => 18,
|
|
DOA_REG => 0,
|
|
DOB_REG => 0,
|
|
EN_RSTRAM_A => FALSE,
|
|
EN_RSTRAM_B => TRUE,
|
|
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
|
INIT_A => X"000000000",
|
|
INIT_B => X"000000000",
|
|
INIT_FILE => "NONE",
|
|
RSTTYPE => "SYNC",
|
|
RST_PRIORITY_A => "CE",
|
|
RST_PRIORITY_B => "CE",
|
|
SIM_COLLISION_CHECK => "ALL",
|
|
SIM_DEVICE => "SPARTAN6",
|
|
SRVAL_A => X"000000000",
|
|
SRVAL_B => X"000000000",
|
|
WRITE_MODE_A => "READ_FIRST",
|
|
WRITE_MODE_B => "READ_FIRST"
|
|
)
|
|
port map (
|
|
REGCEA => N1,
|
|
CLKA => clk,
|
|
ENB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_tmp_ram_rd_en,
|
|
RSTB => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q,
|
|
CLKB => clk,
|
|
REGCEB => N1,
|
|
RSTA => N1,
|
|
ENA => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
DIPA(3) => N1,
|
|
DIPA(2) => N1,
|
|
DIPA(1) => N1,
|
|
DIPA(0) => N1,
|
|
WEA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
WEA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
WEA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
WEA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
|
|
DOA(31) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_31_UNCONNECTED
|
|
,
|
|
DOA(30) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_30_UNCONNECTED
|
|
,
|
|
DOA(29) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_29_UNCONNECTED
|
|
,
|
|
DOA(28) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_28_UNCONNECTED
|
|
,
|
|
DOA(27) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_27_UNCONNECTED
|
|
,
|
|
DOA(26) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_26_UNCONNECTED
|
|
,
|
|
DOA(25) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_25_UNCONNECTED
|
|
,
|
|
DOA(24) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_24_UNCONNECTED
|
|
,
|
|
DOA(23) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_23_UNCONNECTED
|
|
,
|
|
DOA(22) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_22_UNCONNECTED
|
|
,
|
|
DOA(21) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_21_UNCONNECTED
|
|
,
|
|
DOA(20) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_20_UNCONNECTED
|
|
,
|
|
DOA(19) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_19_UNCONNECTED
|
|
,
|
|
DOA(18) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_18_UNCONNECTED
|
|
,
|
|
DOA(17) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_17_UNCONNECTED
|
|
,
|
|
DOA(16) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_16_UNCONNECTED
|
|
,
|
|
DOA(15) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_15_UNCONNECTED
|
|
,
|
|
DOA(14) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_14_UNCONNECTED
|
|
,
|
|
DOA(13) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_13_UNCONNECTED
|
|
,
|
|
DOA(12) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_12_UNCONNECTED
|
|
,
|
|
DOA(11) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_11_UNCONNECTED
|
|
,
|
|
DOA(10) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_10_UNCONNECTED
|
|
,
|
|
DOA(9) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_9_UNCONNECTED
|
|
,
|
|
DOA(8) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_8_UNCONNECTED
|
|
,
|
|
DOA(7) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_7_UNCONNECTED
|
|
,
|
|
DOA(6) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_6_UNCONNECTED
|
|
,
|
|
DOA(5) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_5_UNCONNECTED
|
|
,
|
|
DOA(4) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_4_UNCONNECTED
|
|
,
|
|
DOA(3) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_3_UNCONNECTED
|
|
,
|
|
DOA(2) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_2_UNCONNECTED
|
|
,
|
|
DOA(1) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_1_UNCONNECTED
|
|
,
|
|
DOA(0) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOA_0_UNCONNECTED
|
|
,
|
|
ADDRA(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(9),
|
|
ADDRA(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(8),
|
|
ADDRA(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(7),
|
|
ADDRA(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(6),
|
|
ADDRA(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(5),
|
|
ADDRA(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(4),
|
|
ADDRA(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
|
|
ADDRA(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
|
|
ADDRA(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
|
|
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
|
|
ADDRA(3) => N1,
|
|
ADDRA(2) => N1,
|
|
ADDRA(1) => N1,
|
|
ADDRA(0) => N1,
|
|
ADDRB(13) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(9),
|
|
ADDRB(12) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(8),
|
|
ADDRB(11) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(7),
|
|
ADDRB(10) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(6),
|
|
ADDRB(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(5),
|
|
ADDRB(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(4),
|
|
ADDRB(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
|
|
ADDRB(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
|
|
ADDRB(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
|
|
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1_0_inv,
|
|
ADDRB(3) => N1,
|
|
ADDRB(2) => N1,
|
|
ADDRB(1) => N1,
|
|
ADDRB(0) => N1,
|
|
DIB(31) => N1,
|
|
DIB(30) => N1,
|
|
DIB(29) => N1,
|
|
DIB(28) => N1,
|
|
DIB(27) => N1,
|
|
DIB(26) => N1,
|
|
DIB(25) => N1,
|
|
DIB(24) => N1,
|
|
DIB(23) => N1,
|
|
DIB(22) => N1,
|
|
DIB(21) => N1,
|
|
DIB(20) => N1,
|
|
DIB(19) => N1,
|
|
DIB(18) => N1,
|
|
DIB(17) => N1,
|
|
DIB(16) => N1,
|
|
DIB(15) => N1,
|
|
DIB(14) => N1,
|
|
DIB(13) => N1,
|
|
DIB(12) => N1,
|
|
DIB(11) => N1,
|
|
DIB(10) => N1,
|
|
DIB(9) => N1,
|
|
DIB(8) => N1,
|
|
DIB(7) => N1,
|
|
DIB(6) => N1,
|
|
DIB(5) => N1,
|
|
DIB(4) => N1,
|
|
DIB(3) => N1,
|
|
DIB(2) => N1,
|
|
DIB(1) => N1,
|
|
DIB(0) => N1,
|
|
DOPA(3) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_3_UNCONNECTED
|
|
,
|
|
DOPA(2) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_2_UNCONNECTED
|
|
,
|
|
DOPA(1) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_1_UNCONNECTED
|
|
,
|
|
DOPA(0) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPA_0_UNCONNECTED
|
|
,
|
|
DIPB(3) => N1,
|
|
DIPB(2) => N1,
|
|
DIPB(1) => N1,
|
|
DIPB(0) => N1,
|
|
DOPB(3) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_3_UNCONNECTED
|
|
,
|
|
DOPB(2) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_2_UNCONNECTED
|
|
,
|
|
DOPB(1) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_1_UNCONNECTED
|
|
,
|
|
DOPB(0) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOPB_0_UNCONNECTED
|
|
,
|
|
DOB(31) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_31_UNCONNECTED
|
|
,
|
|
DOB(30) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_30_UNCONNECTED
|
|
,
|
|
DOB(29) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_29_UNCONNECTED
|
|
,
|
|
DOB(28) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_28_UNCONNECTED
|
|
,
|
|
DOB(27) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_27_UNCONNECTED
|
|
,
|
|
DOB(26) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_26_UNCONNECTED
|
|
,
|
|
DOB(25) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_25_UNCONNECTED
|
|
,
|
|
DOB(24) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_24_UNCONNECTED
|
|
,
|
|
DOB(23) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_23_UNCONNECTED
|
|
,
|
|
DOB(22) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_22_UNCONNECTED
|
|
,
|
|
DOB(21) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_21_UNCONNECTED
|
|
,
|
|
DOB(20) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_20_UNCONNECTED
|
|
,
|
|
DOB(19) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_19_UNCONNECTED
|
|
,
|
|
DOB(18) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_18_UNCONNECTED
|
|
,
|
|
DOB(17) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_17_UNCONNECTED
|
|
,
|
|
DOB(16) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_16_UNCONNECTED
|
|
,
|
|
DOB(15) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_15_UNCONNECTED
|
|
,
|
|
DOB(14) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_14_UNCONNECTED
|
|
,
|
|
DOB(13) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_13_UNCONNECTED
|
|
,
|
|
DOB(12) => dout(63),
|
|
DOB(11) => dout(62),
|
|
DOB(10) => dout(61),
|
|
DOB(9) => dout(60),
|
|
DOB(8) => dout(59),
|
|
DOB(7) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_7_UNCONNECTED
|
|
,
|
|
DOB(6) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_6_UNCONNECTED
|
|
,
|
|
DOB(5) =>
|
|
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_s6_noinit_ram_SDP_SIMPLE_PRIM18_ram_DOB_5_UNCONNECTED
|
|
,
|
|
DOB(4) => dout(58),
|
|
DOB(3) => dout(57),
|
|
DOB(2) => dout(56),
|
|
DOB(1) => dout(55),
|
|
DOB(0) => dout(54),
|
|
WEB(3) => N1,
|
|
WEB(2) => N1,
|
|
WEB(1) => N1,
|
|
WEB(0) => N1,
|
|
DIA(31) => N1,
|
|
DIA(30) => N1,
|
|
DIA(29) => N1,
|
|
DIA(28) => N1,
|
|
DIA(27) => N1,
|
|
DIA(26) => N1,
|
|
DIA(25) => N1,
|
|
DIA(24) => N1,
|
|
DIA(23) => N1,
|
|
DIA(22) => N1,
|
|
DIA(21) => N1,
|
|
DIA(20) => N1,
|
|
DIA(19) => N1,
|
|
DIA(18) => N1,
|
|
DIA(17) => N1,
|
|
DIA(16) => N1,
|
|
DIA(15) => N1,
|
|
DIA(14) => N1,
|
|
DIA(13) => N1,
|
|
DIA(12) => din(63),
|
|
DIA(11) => din(62),
|
|
DIA(10) => din(61),
|
|
DIA(9) => din(60),
|
|
DIA(8) => din(59),
|
|
DIA(7) => N1,
|
|
DIA(6) => N1,
|
|
DIA(5) => N1,
|
|
DIA(4) => din(58),
|
|
DIA(3) => din(57),
|
|
DIA(2) => din(56),
|
|
DIA(1) => din(55),
|
|
DIA(0) => din(54)
|
|
);
|
|
|
|
end STRUCTURE;
|
|
|
|
|
END ctrl_fifo1024x64_st_v1_a;
|
-- synthesis translate_on
|
-- synthesis translate_on
|
|
|
