-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Title : stend_sp605_wishbone
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-- Title : stend_sp605_wishbone
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-- Author : Dmitry Smekhov
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-- Author : Dmitry Smekhov
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-- Company : Instrumental Systems
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-- Company : Instrumental Systems
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-- E-mail : dsmv@insys.ru
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-- E-mail : dsmv@insys.ru
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--
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--
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-- Version : 1.2
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-- Version : 1.2
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Description : Stend for test stend_sp605_wishbone
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-- Description : Stend for test stend_sp605_wishbone
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Version 1.2 01.02.2013 Dmitry Smekhov
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-- Version 1.2 01.02.2013 Dmitry Smekhov
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-- Add parameters: test_id, test_log
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-- Add parameters: test_id, test_log
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Version 1.1 (25.10.2011) Kuzmi4
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-- Version 1.1 (25.10.2011) Kuzmi4
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-- Description: add "assert" for stop simulation after TEST finished.
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-- Description: add "assert" for stop simulation after TEST finished.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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library work;
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library work;
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use work.cmd_sim_pkg.all;
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use work.cmd_sim_pkg.all;
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use work.block_pkg.all;
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use work.block_pkg.all;
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use work.sp605_lx45t_wishbone_pkg.all;
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use work.sp605_lx45t_wishbone_pkg.all;
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use work.xilinx_pcie_rport_m2_pkg.all;
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use work.xilinx_pcie_rport_m2_pkg.all;
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use work.test_pkg.all;
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use work.test_pkg.all;
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use std.textio.all;
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use std.textio.all;
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use std.textio;
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use std.textio;
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entity stend_sp605_wishbone is
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entity stend_sp605_wishbone is
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generic(
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generic(
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test_id : in integer:=0; -- идентификатор теста
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test_id : in integer:=3; -- идентификатор теста
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test_log : in string:="src\testbench\log\file_id_" -- имя файла отчёта
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test_log : in string:="src\testbench\log\file_id_" -- имя файла отчёта
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);
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);
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end stend_sp605_wishbone;
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end stend_sp605_wishbone;
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architecture stend_sp605_wishbone of stend_sp605_wishbone is
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architecture stend_sp605_wishbone of stend_sp605_wishbone is
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--
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--
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--function set_file_name( test_log : in string; test_id: in integer ) return string is
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--function set_file_name( test_log : in string; test_id: in integer ) return string is
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--variable str : line;
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--variable str : line;
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--variable ret : string( 255 downto 1 );
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--variable ret : string( 255 downto 1 );
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--begin
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--begin
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--
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--
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-- write( str, test_log );
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-- write( str, test_log );
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-- write( str, string'("_id_") );
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-- write( str, string'("_id_") );
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-- write( str, test_id );
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-- write( str, test_id );
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--
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--
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-- ret:=conv_string( str );
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-- ret:=conv_string( str );
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-- return ret;
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-- return ret;
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--
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--
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--
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--
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--end set_file_name;
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--end set_file_name;
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constant fname_test_log : string:= test_log & integer'image(test_id) & ".log";
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constant fname_test_log : string:= test_log & integer'image(test_id) & ".log";
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signal clk125 : std_logic:='0';
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signal clk125 : std_logic:='0';
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signal clk125p : std_logic;
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signal clk125p : std_logic;
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signal clk125n : std_logic;
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signal clk125n : std_logic;
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signal clk100 : std_logic:='0';
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signal clk100 : std_logic:='0';
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signal clk100p : std_logic;
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signal clk100p : std_logic;
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signal clk100n : std_logic;
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signal clk100n : std_logic;
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signal reset : std_logic;
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signal reset : std_logic;
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signal txp : std_logic_vector( 0 downto 0 ):=(others=>'0');
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signal txp : std_logic_vector( 0 downto 0 ):=(others=>'0');
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signal txn : std_logic_vector( 0 downto 0 ):=(others=>'1');
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signal txn : std_logic_vector( 0 downto 0 ):=(others=>'1');
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signal rxp : std_logic_vector( 0 downto 0 ):=(others=>'0');
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signal rxp : std_logic_vector( 0 downto 0 ):=(others=>'0');
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signal rxn : std_logic_vector( 0 downto 0 ):=(others=>'1');
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signal rxn : std_logic_vector( 0 downto 0 ):=(others=>'1');
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signal rp_txp : std_logic_vector( 0 downto 0 ):=(others=>'0');
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signal rp_txp : std_logic_vector( 0 downto 0 ):=(others=>'0');
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signal rp_txn : std_logic_vector( 0 downto 0 ):=(others=>'1');
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signal rp_txn : std_logic_vector( 0 downto 0 ):=(others=>'1');
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signal rp_rxp : std_logic_vector( 0 downto 0 ):=(others=>'0');
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signal rp_rxp : std_logic_vector( 0 downto 0 ):=(others=>'0');
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signal rp_rxn : std_logic_vector( 0 downto 0 ):=(others=>'1');
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signal rp_rxn : std_logic_vector( 0 downto 0 ):=(others=>'1');
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signal tp : std_logic_vector( 3 downto 1 );
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signal tp : std_logic_vector( 3 downto 1 );
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signal led1 : std_logic;
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signal led1 : std_logic;
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signal led2 : std_logic;
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signal led2 : std_logic;
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signal led3 : std_logic;
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signal led3 : std_logic;
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signal led4 : std_logic;
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signal led4 : std_logic;
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signal cmd : bh_cmd; -- команда
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signal cmd : bh_cmd; -- команда
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signal ret : bh_ret; -- ответ
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signal ret : bh_ret; -- ответ
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--
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--
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-- Additional TEST signals:
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-- Additional TEST signals:
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--
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--
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signal s_spy_fifo_clk : std_logic:='0';
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signal s_spy_fifo_clk : std_logic:='0';
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signal s_spy_fifo_wr_ena : std_logic:='0';
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signal s_spy_fifo_wr_ena : std_logic:='0';
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signal s_spy_fifo_final : std_logic:='0';
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signal s_spy_fifo_final : std_logic:='0';
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signal si_wb_outgoing_fifo_counter : integer:=0;
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signal si_wb_outgoing_fifo_counter : integer:=0;
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begin
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begin
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dut: sp605_lx45t_wishbone
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dut: sp605_lx45t_wishbone
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generic map(
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generic map(
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is_simulation => 2 -- 0 - синтез, 1 - моделирование ADM, 2 - моделирование pcie_core
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is_simulation => 2 -- 0 - синтез, 1 - моделирование ADM, 2 - моделирование pcie_core
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)
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)
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port map(
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port map(
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---- PCI-Express ----
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---- PCI-Express ----
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pci_exp_txp => txp,
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pci_exp_txp => txp,
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pci_exp_txn => txn,
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pci_exp_txn => txn,
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pci_exp_rxp => rxp,
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pci_exp_rxp => rxp,
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pci_exp_rxn => rxn,
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pci_exp_rxn => rxn,
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sys_clk_p => clk125p, -- тактовая частота 125 MHz от PCI_Express
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sys_clk_p => clk125p, -- тактовая частота 125 MHz от PCI_Express
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sys_clk_n => clk125n,
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sys_clk_n => clk125n,
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sys_reset_n => reset, -- 0 - сброс
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sys_reset_n => reset, -- 0 - сброс
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---- Светодиоды ----
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---- Светодиоды ----
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gpio_led1 => led1,
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gpio_led1 => led1,
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gpio_led2 => led2,
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gpio_led2 => led2,
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gpio_led3 => led3,
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gpio_led3 => led3,
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gpio_led0 => led4
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gpio_led0 => led4
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);
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);
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rp : xilinx_pcie_rport_m2
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rp : xilinx_pcie_rport_m2
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generic map (
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generic map (
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REF_CLK_FREQ => 0,
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REF_CLK_FREQ => 0,
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ALLOW_X8_GEN2 => FALSE,
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ALLOW_X8_GEN2 => FALSE,
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PL_FAST_TRAIN => TRUE,
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PL_FAST_TRAIN => TRUE,
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LINK_CAP_MAX_LINK_SPEED => X"1",
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LINK_CAP_MAX_LINK_SPEED => X"1",
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DEVICE_ID => X"6011",
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DEVICE_ID => X"6011",
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LINK_CAP_MAX_LINK_WIDTH => X"01",
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LINK_CAP_MAX_LINK_WIDTH => X"01",
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LINK_CAP_MAX_LINK_WIDTH_int => 1,
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LINK_CAP_MAX_LINK_WIDTH_int => 1,
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LINK_CTRL2_TARGET_LINK_SPEED => X"1",
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LINK_CTRL2_TARGET_LINK_SPEED => X"1",
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LTSSM_MAX_LINK_WIDTH => X"01",
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LTSSM_MAX_LINK_WIDTH => X"01",
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DEV_CAP_MAX_PAYLOAD_SUPPORTED => 2,
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DEV_CAP_MAX_PAYLOAD_SUPPORTED => 2,
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VC0_TX_LASTPACKET => 29,
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VC0_TX_LASTPACKET => 29,
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VC0_RX_RAM_LIMIT => X"7FF",
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VC0_RX_RAM_LIMIT => X"7FF",
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VC0_TOTAL_CREDITS_PD => (308),
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VC0_TOTAL_CREDITS_PD => (308),
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VC0_TOTAL_CREDITS_CD => (308),
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VC0_TOTAL_CREDITS_CD => (308),
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USER_CLK_FREQ => 1
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USER_CLK_FREQ => 1
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)
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)
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port map (
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port map (
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sys_clk => clk100,
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sys_clk => clk100,
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sys_reset_n => reset,
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sys_reset_n => reset,
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pci_exp_txn => rp_txn,
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pci_exp_txn => rp_txn,
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pci_exp_txp => rp_txp,
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pci_exp_txp => rp_txp,
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pci_exp_rxn => rp_rxn,
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pci_exp_rxn => rp_rxn,
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pci_exp_rxp => rp_rxp,
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pci_exp_rxp => rp_rxp,
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cmd => cmd, -- команда
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cmd => cmd, -- команда
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ret => ret -- ответ
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ret => ret -- ответ
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);
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);
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clk125 <= not clk125 after 4 ns;
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clk125 <= not clk125 after 4 ns;
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clk125p <= clk125;
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clk125p <= clk125;
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clk125n <= not clk125;
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clk125n <= not clk125;
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clk100 <= not clk100 after 5 ns;
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clk100 <= not clk100 after 5 ns;
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clk100p <= clk100;
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clk100p <= clk100;
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clk100n <= not clk100;
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clk100n <= not clk100;
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rxp(0) <= rp_txp(0);
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rxp(0) <= rp_txp(0);
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rxn(0) <= rp_txn(0);
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rxn(0) <= rp_txn(0);
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rp_rxp(0) <= txp(0);
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rp_rxp(0) <= txp(0);
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rp_rxn(0) <= txn(0);
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rp_rxn(0) <= txn(0);
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reset <= '0', '1' after 5002 ns;
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reset <= '0', '1' after 5002 ns;
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pr_main: process
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pr_main: process
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variable data : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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variable str : LINE; -- pointer to string
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variable str : LINE; -- pointer to string
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begin
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begin
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-- test_init( "test.log" );
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-- test_init( "test.log" );
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test_init( fname_test_log );
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test_init( fname_test_log );
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wait for 180 us;
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wait for 180 us;
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case( test_id ) is
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case( test_id ) is
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when 0 => test_dsc_incorrect( cmd, ret );
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when 0 => test_dsc_incorrect( cmd, ret );
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when 1 => test_read_4kb( cmd, ret ); -- was original
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when 1 => test_read_4kb( cmd, ret ); -- was original
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when 2 => test_adm_read_8kb( cmd, ret );
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when 2 => test_adm_read_8kb( cmd, ret );
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when 3 => test_read_reg( cmd, ret );
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when 3 => test_read_reg( cmd, ret );
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--when 3 => test_adm_read_16kb( cmd, ret );
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--when 3 => test_adm_read_16kb( cmd, ret );
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--when 4 => test_adm_write_16kb( cmd, ret );
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--when 4 => test_adm_write_16kb( cmd, ret );
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--when 5 => test_block_main( cmd, ret );
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--when 5 => test_block_main( cmd, ret );
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when others => null;
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when others => null;
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end case;
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end case;
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--test_num_1(cmd, ret);
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--test_num_1(cmd, ret);
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--test_num_2(cmd, ret);
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--test_num_2(cmd, ret);
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--test_wb_1(cmd, ret);
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--test_wb_1(cmd, ret);
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--test_wb_2(cmd, ret);
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--test_wb_2(cmd, ret);
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test_close;
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test_close;
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--
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--
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-- Print Final Banner
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-- Print Final Banner
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-- report "Init END OF TEST" severity WARNING;
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-- report "Init END OF TEST" severity WARNING;
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-- assert false
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-- assert false
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-- report "End of TEST; Ending simulation (not a Failure)"
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-- report "End of TEST; Ending simulation (not a Failure)"
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-- severity FAILURE;
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-- severity FAILURE;
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wait;
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wait;
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end process pr_main;
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end process pr_main;
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end stend_sp605_wishbone;
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end stend_sp605_wishbone;
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