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-- Company:
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-- Company:
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-- Engineer: Yann Vernier
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-- Engineer: Yann Vernier
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--
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--
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-- Create Date: 23:05:04 09/08/2009
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-- Create Date: 23:05:04 09/08/2009
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-- Design Name:
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-- Design Name:
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-- Module Name: debounce - Behavioral
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-- Module Name: debounce - Behavioral
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description: Debounces an input signal (for instance, a switch).
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-- Description: Debounces an input signal (for instance, a switch).
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-- Output will only change after input has stayed one value between two enabled clock edges.
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-- Output will only change after input has stayed one value between two enabled clock edges.
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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entity debounce is
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entity debounce is
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Port ( clk : in STD_LOGIC;
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Port ( clk : in STD_LOGIC;
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clken : in STD_LOGIC;
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clken : in STD_LOGIC;
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input : in STD_LOGIC;
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input : in STD_LOGIC;
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output : inout STD_LOGIC);
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output : out STD_LOGIC);
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end debounce;
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end debounce;
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-- Concept: input values are asynchronously connected to SR latches.
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-- Concept: input values are asynchronously connected to SR latches.
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-- Those are synchronously reset, so if both are set, the input is unstable.
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-- Those are synchronously reset, so if both are set, the input is unstable.
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-- On Spartan 3 FPGAs, this architecture probably requires at least three slices,
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-- On Spartan 3 FPGAs, this architecture probably requires at least three slices,
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-- due to separate RS lines for flip-flops. The output register may share, though.
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-- due to separate RS lines for flip-flops. The output register may share, though.
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architecture Behavioral of debounce is
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architecture Behavioral of debounce is
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-- 00->no input value observed (reset), 10 or 01 -> steady value, 11->value changed
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-- 00->no input value observed (reset), 10 or 01 -> steady value, 11->value changed
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signal inputv : std_logic_vector(0 to 1) := "00";
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signal inputv : std_logic_vector(0 to 1) := "00";
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signal next_output : std_logic;
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signal next_output : std_logic;
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signal current_output : std_logic;
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begin
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begin
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output <= current_output;
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-- our two asynch latches must agree for an update to occur
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-- our two asynch latches must agree for an update to occur
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-- the tricky part of the code was convincing the synthesizer we only need one LUT3
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-- the tricky part of the code was convincing the synthesizer we only need one LUT3
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-- to implement this consensus function (inputv must agree to alter output).
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-- to implement this consensus function (inputv must agree to alter output).
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with inputv select
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with inputv select
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next_output <= '0' when "10",
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next_output <= '0' when "10",
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'1' when "01",
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'1' when "01",
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output when others;
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current_output when others;
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process (clk, input)
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process (clk, input)
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begin
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begin
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-- input='0' for asynch set of input(0), synch reset
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-- input='0' for asynch set of input(0), synch reset
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if input='0' then
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if input='0' then
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inputv(0) <= '1';
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inputv(0) <= '1';
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elsif clken='1' and rising_edge(clk) then
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elsif clken='1' and rising_edge(clk) then
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inputv(0) <= '0';
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inputv(0) <= '0';
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end if;
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end if;
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-- same for 1
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-- same for 1
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if input='1' then
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if input='1' then
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inputv(1) <= '1';
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inputv(1) <= '1';
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elsif clken='1' and rising_edge(clk) then
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elsif clken='1' and rising_edge(clk) then
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inputv(1) <= '0';
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inputv(1) <= '0';
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end if;
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end if;
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-- finally, on enabled clocks, update output
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-- finally, on enabled clocks, update output
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if clken='1' and rising_edge(clk) then
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if clken='1' and rising_edge(clk) then
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output <= next_output;
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current_output <= next_output;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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