--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Company:
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-- Company:
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-- Engineer:
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-- Engineer:
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--
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--
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-- Create Date: 00:00:04 08/14/2009
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-- Create Date: 00:00:04 08/14/2009
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-- Design Name:
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-- Design Name:
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-- Module Name: /home/yann/fpga/work/pdp1-3/testtop.vhd
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-- Module Name: /home/yann/fpga/work/pdp1-3/testtop.vhd
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-- Project Name: pdp1-3
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-- Project Name: pdp1-3
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-- Target Device:
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-- Target Device:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- VHDL Test Bench Created by ISE for module: top
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-- VHDL Test Bench Created by ISE for module: top
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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-- Notes:
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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-- simulation model.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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--USE ieee.textio.ALL;
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ENTITY testtop IS
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ENTITY testtop IS
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END testtop;
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END testtop;
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ARCHITECTURE behavior OF testtop IS
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ARCHITECTURE behavior OF testtop IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT top
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COMPONENT top
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PORT(
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PORT(
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CLK_50M : IN std_logic;
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CLK_50M : IN std_logic;
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CLK_AUX : IN std_logic;
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LED : OUT std_logic_vector(7 downto 0);
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LED : OUT std_logic_vector(7 downto 0);
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SW : IN std_logic_vector(3 downto 0);
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SW : IN std_logic_vector(3 downto 0);
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AWAKE : OUT std_logic;
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AWAKE : OUT std_logic;
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SPI_MOSI : OUT std_logic;
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SPI_MOSI : OUT std_logic;
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DAC_CS : OUT std_logic;
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DAC_CS : OUT std_logic;
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SPI_SCK : OUT std_logic;
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SPI_SCK : OUT std_logic;
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DAC_CLR : OUT std_logic;
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DAC_CLR : OUT std_logic;
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DAC_OUT : IN std_logic;
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DAC_OUT : IN std_logic;
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RS232_DCE_RXD : IN std_logic;
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RS232_DCE_RXD : IN std_logic;
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RS232_DCE_TXD : OUT std_logic
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RS232_DCE_TXD : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal CLK_50M : std_logic := '0';
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signal CLK_50M : std_logic := '0';
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signal CLK_AUX : std_logic := '0';
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signal SW : std_logic_vector(3 downto 0) := (others => '0');
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signal SW : std_logic_vector(3 downto 0) := (others => '0');
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signal DAC_OUT : std_logic := '0';
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signal DAC_OUT : std_logic := '0';
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--Outputs
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--Outputs
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signal LED : std_logic_vector(7 downto 0);
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signal LED : std_logic_vector(7 downto 0);
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signal AWAKE : std_logic;
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signal AWAKE : std_logic;
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signal SPI_MOSI : std_logic;
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signal SPI_MOSI : std_logic;
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signal DAC_CS : std_logic;
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signal DAC_CS : std_logic;
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signal SPI_SCK : std_logic;
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signal SPI_SCK : std_logic;
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signal DAC_CLR : std_logic;
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signal DAC_CLR : std_logic;
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signal TXD, RXD : std_logic;
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signal TXD, RXD : std_logic;
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-- UART interface
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COMPONENT Minimal_UART_CORE
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PORT(
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CLOCK : IN std_logic;
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RXD : IN std_logic;
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INP : IN std_logic_vector(7 downto 0);
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WR : IN std_logic;
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OUTP : INOUT std_logic_vector(7 downto 0);
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EOC : OUT std_logic;
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TXD : OUT std_logic;
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EOT : OUT std_logic;
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READY : OUT std_logic
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);
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END COMPONENT;
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signal received_byte, old_received_byte, tx_ready, wrote, byte_request,
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eot : std_logic := '0';
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signal read_byte, write_byte: std_logic_vector(7 downto 0);
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constant CLK_50M_period : time := 20ns;
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constant CLK_50M_period : time := 20ns;
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constant CLK_AUX_period : time := 7.5ns;
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constant bittime : time := 8.680555us; --1s/115200;
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constant bittime : time := 8.680555us; --1s/115200;
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constant waittime : time := 20*bittime;
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procedure send_byte (bytetosend : in std_logic_vector(7 downto 0);
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signal tx_ready : in std_logic;
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signal eot : in std_logic;
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signal write_byte : out std_logic_vector(7 downto 0);
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signal wrote : out std_logic)
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is
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-- subprogram_declarative_items (constant declarations, variable declarations, etc.)
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begin
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-- wait for 100ns;
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wait until rising_edge(CLK_50M) and tx_ready = '1' and eot='0';
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write_byte <= bytetosend;
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wrote <= '1';
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wait until rising_edge(CLK_50M);
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wrote <= '0';
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-- wait until eot='0' and tx_ready='1';
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-- Without UART, it was something like:
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-- RXD <= '0'; wait for bittime;
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-- RXD <= bytetosend(0); wait for bittime;
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-- RXD <= bytetosend(1); wait for bittime;
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-- RXD <= bytetosend(2); wait for bittime;
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-- RXD <= bytetosend(3); wait for bittime;
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-- RXD <= bytetosend(4); wait for bittime;
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-- RXD <= bytetosend(5); wait for bittime;
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-- RXD <= bytetosend(6); wait for bittime;
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-- RXD <= bytetosend(7); wait for bittime;
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-- RXD <= '1'; wait for bittime; -- first sixbit 000101
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-- wait for waittime;
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end send_byte;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: top PORT MAP (
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uut: top PORT MAP (
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CLK_50M => CLK_50M,
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CLK_50M => CLK_50M,
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CLK_AUX => CLK_AUX,
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LED => LED,
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LED => LED,
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SW => SW,
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SW => SW,
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AWAKE => AWAKE,
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AWAKE => AWAKE,
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SPI_MOSI => SPI_MOSI,
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SPI_MOSI => SPI_MOSI,
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DAC_CS => DAC_CS,
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DAC_CS => DAC_CS,
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SPI_SCK => SPI_SCK,
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SPI_SCK => SPI_SCK,
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DAC_CLR => DAC_CLR,
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DAC_CLR => DAC_CLR,
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DAC_OUT => DAC_OUT,
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DAC_OUT => DAC_OUT,
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RS232_DCE_RXD => RXD,
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RS232_DCE_RXD => RXD,
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RS232_DCE_TXD => TXD
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RS232_DCE_TXD => TXD
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);
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);
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-- No clocks detected in port list. Replace CLK_50M below with
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-- No clocks detected in port list. Replace CLK_50M below with
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-- appropriate port name
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-- appropriate port name
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CLK_50M_process :process
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CLK_50M_process :process
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begin
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begin
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CLK_50M <= '0';
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CLK_50M <= '0';
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wait for CLK_50M_period/2;
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wait for CLK_50M_period/2;
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CLK_50M <= '1';
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CLK_50M <= '1';
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wait for CLK_50M_period/2;
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wait for CLK_50M_period/2;
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end process;
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end process;
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CLK_AUX_process :process
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begin
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CLK_AUX <= '0';
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wait for CLK_AUX_period/2;
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CLK_AUX <= '1';
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wait for CLK_AUX_period/2;
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end process;
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-- UART for talking to UUT
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Inst_Minimal_UART_CORE: Minimal_UART_CORE PORT MAP(
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CLOCK => CLK_50M,
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EOC => received_byte, -- end of character; rising edge indicates valid data in OUTP
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OUTP => read_byte,
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RXD => TXD,
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TXD => RXD,
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EOT => eot, -- end of transmit; indicates a character has been sent
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INP => write_byte,
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READY => tx_ready, -- indicates that we may write
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WR => wrote
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);
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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begin
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begin
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RXD <= '1';
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wait for 1ms;
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-- hold reset state for 100ms.
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send_byte("10000101", tx_ready, eot, write_byte, wrote);
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wait for 10ms;
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send_byte("00111111", tx_ready, eot, write_byte, wrote); -- ignored, as bit 7 is not set
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send_byte("10000110", tx_ready, eot, write_byte, wrote);
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wait for 16*bittime;
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send_byte("10111000", tx_ready, eot, write_byte, wrote); -- Together 050670
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-- TODO: show reply data
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-- TODO: show reply data
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RXD <= '0'; wait for bittime;
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RXD <= '1'; wait for bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '1'; wait for bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '1'; wait for bittime;
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RXD <= '1'; wait for bittime; -- first sixbit 000101
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wait for 16*bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '1'; wait for bittime;
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RXD <= '1'; wait for bittime;
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RXD <= '1'; wait for bittime;
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RXD <= '1'; wait for bittime;
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RXD <= '1'; wait for bittime;
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RXD <= '1'; wait for bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '1'; wait for bittime; -- this byte is not marked as binary data and should be skipped
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wait for 16*bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '1'; wait for bittime;
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RXD <= '1'; wait for bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '1'; wait for bittime;
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RXD <= '1'; wait for bittime; -- second sixbit 001100
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wait for 16*bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '1'; wait for bittime;
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RXD <= '1'; wait for bittime;
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RXD <= '1'; wait for bittime;
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RXD <= '0'; wait for bittime;
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RXD <= '1'; wait for bittime;
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RXD <= '1'; wait for bittime; -- third sixbit 111000
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wait for CLK_50M_period*10;
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wait for CLK_50M_period*10;
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-- insert stimulus here
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-- insert stimulus here
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wait;
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wait;
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end process;
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end process;
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END;
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END;
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