----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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-- Company:
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-- Company:
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-- Engineer:
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-- Engineer:
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--
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--
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-- Create Date: 21:25:57 02/09/2009
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-- Create Date: 21:25:57 02/09/2009
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-- Design Name:
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-- Design Name:
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-- Module Name: top - Behavioral
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-- Module Name: top - Behavioral
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity top is
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entity top is
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Port (
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Port (
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CLK_50M : in STD_LOGIC;
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CLK_50M : in STD_LOGIC;
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CLK_AUX : in STD_LOGIC; -- 133.33 MHz
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CLK_AUX : in STD_LOGIC; -- 133.33 MHz
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LED : out std_logic_vector(7 downto 0) := (others=>'0');
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LED : out std_logic_vector(7 downto 0) := (others=>'0');
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SW : in std_logic_vector(3 downto 0);
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SW : in std_logic_vector(3 downto 0);
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AWAKE : out std_logic := '0';
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AWAKE : out std_logic := '0';
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-- SPI is in use for DAC outputs to oscilloscope
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-- SPI is in use for DAC outputs to oscilloscope
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SPI_MOSI : OUT std_logic := 'L';
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SPI_MOSI : OUT std_logic := 'L';
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DAC_CS : OUT std_logic := '1';
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DAC_CS : OUT std_logic := '1';
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SPI_SCK : OUT std_logic := 'L';
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SPI_SCK : OUT std_logic := 'L';
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DAC_CLR : OUT std_logic := 'L';
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DAC_CLR : OUT std_logic := 'L';
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DAC_OUT : IN std_logic := 'L';
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DAC_OUT : IN std_logic := 'L';
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-- VGA is (planned) for emulated vector graphics
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-- VGA is (planned) for emulated vector graphics
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VGA_R : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_R : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_G : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_G : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_B : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_B : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_HSYNC : out STD_LOGIC := '1';
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VGA_HSYNC : out STD_LOGIC := '1';
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VGA_VSYNC : out STD_LOGIC := '0';
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VGA_VSYNC : out STD_LOGIC := '0';
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-- DCE serial port is used for communications with PC
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-- DCE serial port is used for communications with PC
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RS232_DCE_RXD : IN std_logic;
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RS232_DCE_RXD : IN std_logic;
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RS232_DCE_TXD : OUT std_logic := '1';
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RS232_DCE_TXD : OUT std_logic := '1';
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-- pushbutton to be debounced
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-- pushbutton to be debounced
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BTN_EAST : IN std_logic := '0'
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BTN_EAST : IN std_logic := '0'
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);
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);
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end top;
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end top;
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architecture Behavioral of top is
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architecture Behavioral of top is
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subtype word is std_logic_vector(0 to 17);
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subtype word is std_logic_vector(0 to 17);
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component vga is
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component vga is
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Port ( VGA_R : out STD_LOGIC_VECTOR (3 downto 0);
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Port ( VGA_R : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_G : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_G : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_B : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_B : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_HSYNC : out STD_LOGIC := '1';
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VGA_HSYNC : out STD_LOGIC := '1';
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VGA_VSYNC : out STD_LOGIC := '0';
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VGA_VSYNC : out STD_LOGIC := '0';
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CLK_50M : in STD_LOGIC;
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CLK_50M : in STD_LOGIC;
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CLK_133M33 : in STD_LOGIC);
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CLK_133M33 : in STD_LOGIC);
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end component;
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end component;
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component pdp1io is
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component pdp1io is
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Port (
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Port (
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CLK_50M : in STD_LOGIC;
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CLK_50M : in STD_LOGIC;
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CLK_PDP : in STD_LOGIC;
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CLK_PDP : in STD_LOGIC;
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IO_SET : out STD_LOGIC;
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IO_SET : out STD_LOGIC;
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IO_TO_CPU : out STD_LOGIC_VECTOR(0 to 17);
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IO_TO_CPU : out STD_LOGIC_VECTOR(0 to 17);
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AC, IO_FROM_CPU : in STD_LOGIC_VECTOR(0 to 17);
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AC, IO_FROM_CPU : in STD_LOGIC_VECTOR(0 to 17);
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IOT : in STD_LOGIC_VECTOR(0 to 63);
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IOT : in STD_LOGIC_VECTOR(0 to 63);
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IO_RESTART : out STD_LOGIC;
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IO_RESTART : out STD_LOGIC;
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IO_DORESTART : in STD_LOGIC;
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IO_DORESTART : in STD_LOGIC;
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-- SPI is in use for DAC outputs to oscilloscope
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-- SPI is in use for DAC outputs to oscilloscope
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SPI_MOSI : OUT std_logic;
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SPI_MOSI : OUT std_logic;
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DAC_CS : OUT std_logic;
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DAC_CS : OUT std_logic;
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SPI_SCK : OUT std_logic;
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SPI_SCK : OUT std_logic;
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DAC_CLR : OUT std_logic;
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DAC_CLR : OUT std_logic;
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DAC_OUT : IN std_logic;
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DAC_OUT : IN std_logic;
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-- DCE serial port is used for communications with PC
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-- DCE serial port is used for communications with PC
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RS232_DCE_RXD : IN std_logic;
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RS232_DCE_RXD : IN std_logic;
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RS232_DCE_TXD : OUT std_logic
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RS232_DCE_TXD : OUT std_logic
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);
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);
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end component;
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end component;
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COMPONENT flagcross
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COMPONENT flagcross
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generic ( width : integer := 0 );
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generic ( width : integer := 0 );
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PORT(
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PORT(
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ClkA, ClkB, FastClk : IN std_logic;
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ClkA, ClkB, FastClk : IN std_logic;
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A : IN std_logic;
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A : IN std_logic;
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B : OUT std_logic;
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B : OUT std_logic;
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A_reg : in STD_LOGIC_VECTOR(0 to width-1);
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A_reg : in STD_LOGIC_VECTOR(0 to width-1);
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B_reg : out STD_LOGIC_VECTOR(0 to width-1)
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B_reg : out STD_LOGIC_VECTOR(0 to width-1)
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);
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);
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END COMPONENT;
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END COMPONENT;
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component coremem
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component coremem
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Port ( A : in STD_LOGIC_VECTOR (0 to 11);
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Port ( A : in STD_LOGIC_VECTOR (0 to 11);
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CLK : in STD_LOGIC;
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CLK : in STD_LOGIC;
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WE : in STD_LOGIC;
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WE : in STD_LOGIC;
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DI : in word;
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DI : in word;
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DO : inout word);
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DO : inout word);
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end component;
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end component;
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component clockdiv
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component clockdiv
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Port ( CLK_50M : in STD_LOGIC;
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Port ( CLK_50M : in STD_LOGIC;
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CLK : out STD_LOGIC; -- 2MHz
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CLK : out STD_LOGIC; -- 2MHz
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LOCKED : out STD_LOGIC);
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LOCKED : out STD_LOGIC);
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end component;
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end component;
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component pdp1cpu
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component pdp1cpu
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Port ( M_DO : in word;
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Port ( M_DO : in word;
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M_DI : out word;
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M_DI : out word;
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MW : inout STD_LOGIC;
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MW : inout STD_LOGIC;
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MA : out STD_LOGIC_VECTOR (0 to 11);
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MA : out STD_LOGIC_VECTOR (0 to 11);
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AWAKE : out STD_LOGIC;
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AWAKE : out STD_LOGIC;
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CLK : in STD_LOGIC;
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CLK : in STD_LOGIC;
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IOT : out STD_LOGIC_VECTOR(0 to 63);
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IOT : out STD_LOGIC_VECTOR(0 to 63);
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IODOPULSE : out STD_LOGIC;
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IODOPULSE : out STD_LOGIC;
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IODONE : in STD_LOGIC;
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IODONE : in STD_LOGIC;
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IO_set : in STD_LOGIC;
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IO_set : in STD_LOGIC;
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IO_IN : in STD_LOGIC_VECTOR(0 to 17);
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IO_IN : in STD_LOGIC_VECTOR(0 to 17);
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PC : inout unsigned(0 to 11); -- program counter
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PC : inout std_logic_vector(0 to 11); -- program counter
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AC, IO : inout word;
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AC, IO : inout word;
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SW_SENSE : in STD_LOGIC_VECTOR(1 to 6);
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SW_SENSE : in STD_LOGIC_VECTOR(1 to 6);
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RESET : in STD_LOGIC);
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RESET : in STD_LOGIC);
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end component;
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end component;
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COMPONENT debounce
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COMPONENT debounce
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PORT(
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PORT(
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clk : IN std_logic;
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clk : IN std_logic;
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clken : IN std_logic;
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clken : IN std_logic;
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input : IN std_logic;
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input : IN std_logic;
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output : INOUT std_logic
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output : INOUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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signal CLK, CLK_LOCKED, RESET : std_logic := '0';
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signal CLK, CLK_LOCKED, RESET : std_logic := '0';
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signal mem_we : std_logic := '0';
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signal mem_we : std_logic := '0';
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signal mem_di, mem_do, io, ac, io_in : word := (others=>'0');
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signal mem_di, mem_do, io, ac, io_in : word := (others=>'0');
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signal sw_sense : std_logic_vector(1 to 6) := o"00";
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signal sw_sense : std_logic_vector(1 to 6) := o"00";
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signal mem_a : std_logic_vector(0 to 11) := (others=>'0');
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signal mem_a : std_logic_vector(0 to 11) := (others=>'0');
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signal pc : unsigned(0 to 11);
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signal pc : std_logic_vector(0 to 11);
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signal io_dopulse, io_done, io_set : std_logic := '0';
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signal io_dopulse, io_done, io_set : std_logic := '0';
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signal IOT : std_logic_vector(0 to 63) := (others=>'0');
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signal IOT : std_logic_vector(0 to 63) := (others=>'0');
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signal display_trig, display_done: std_logic;
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signal display_trig, display_done: std_logic;
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constant pdp1_enabled : boolean := true;
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constant pdp1_enabled : boolean := true;
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begin
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begin
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RESET <= (not CLK_LOCKED) or BTN_EAST;
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RESET <= (not CLK_LOCKED) or BTN_EAST;
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vga_out : vga port map (
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vga_out : vga port map (
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CLK_50M => CLK_50M,
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CLK_50M => CLK_50M,
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CLK_133M33 => CLK_AUX,
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CLK_133M33 => CLK_AUX,
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VGA_R => VGA_R,
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VGA_R => VGA_R,
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VGA_G => VGA_G,
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VGA_G => VGA_G,
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VGA_B => VGA_B,
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VGA_B => VGA_B,
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VGA_HSYNC => VGA_HSYNC,
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VGA_HSYNC => VGA_HSYNC,
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VGA_VSYNC => VGA_VSYNC
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VGA_VSYNC => VGA_VSYNC
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);
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);
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dummy: if not pdp1_enabled generate
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dummy: if not pdp1_enabled generate
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begin
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begin
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LED <= (others => '0');
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LED <= (others => '0');
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SPI_SCK <= '0';
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SPI_SCK <= '0';
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RS232_DCE_TXD <= '1';
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RS232_DCE_TXD <= '1';
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SPI_MOSI <= '0';
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SPI_MOSI <= '0';
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DAC_CLR <= '0';
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DAC_CLR <= '0';
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AWAKE <= '1';
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AWAKE <= '1';
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DAC_CS <= '1';
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DAC_CS <= '1';
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end generate;
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end generate;
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disabled: if pdp1_enabled generate
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disabled: if pdp1_enabled generate
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begin
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begin
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clock : clockdiv
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clock : clockdiv
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port map (
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port map (
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CLK_50M => CLK_50M,
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CLK_50M => CLK_50M,
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CLK => CLK,
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CLK => CLK,
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LOCKED => CLK_LOCKED
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LOCKED => CLK_LOCKED
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);
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);
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core : coremem
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core : coremem
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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WE => mem_we,
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WE => mem_we,
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DI => mem_di,
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DI => mem_di,
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DO => mem_do,
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DO => mem_do,
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A => mem_a
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A => mem_a
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);
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);
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-- AWAKE <= '1';
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-- AWAKE <= '1';
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cpu : pdp1cpu
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cpu : pdp1cpu
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port map (
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port map (
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CLK => CLK,
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CLK => CLK,
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AWAKE => AWAKE,
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AWAKE => AWAKE,
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M_DO => mem_do,
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M_DO => mem_do,
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M_DI => mem_di,
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M_DI => mem_di,
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MW => mem_we,
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MW => mem_we,
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MA => mem_a,
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MA => mem_a,
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IOT => IOT,
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IOT => IOT,
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IODOPULSE => io_dopulse,
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IODOPULSE => io_dopulse,
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IODONE => io_done,
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IODONE => io_done,
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IO_IN => io_in,
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IO_IN => io_in,
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IO_SET => io_set,
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IO_SET => io_set,
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PC => pc,
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PC => pc,
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IO => IO,
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IO => IO,
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AC => AC,
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AC => AC,
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SW_SENSE => SW_SENSE,
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SW_SENSE => SW_SENSE,
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RESET => RESET
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RESET => RESET
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);
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);
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iodevices : pdp1io port map (
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iodevices : pdp1io port map (
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CLK_50M => CLK_50M,
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CLK_50M => CLK_50M,
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CLK_PDP => CLK,
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CLK_PDP => CLK,
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IO_SET => io_set,
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IO_SET => io_set,
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IO_TO_CPU => io_in,
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IO_TO_CPU => io_in,
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IO_FROM_CPU => IO,
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IO_FROM_CPU => IO,
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AC => AC,
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AC => AC,
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IOT => iot,
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IOT => iot,
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IO_RESTART => io_done,
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IO_RESTART => io_done,
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IO_DORESTART => io_dopulse,
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IO_DORESTART => io_dopulse,
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-- display device uses DAC
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-- display device uses DAC
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SPI_MOSI => SPI_MOSI,
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SPI_MOSI => SPI_MOSI,
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DAC_CS => DAC_CS,
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DAC_CS => DAC_CS,
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SPI_SCK => SPI_SCK,
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SPI_SCK => SPI_SCK,
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DAC_CLR => DAC_CLR,
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DAC_CLR => DAC_CLR,
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DAC_OUT => DAC_OUT,
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DAC_OUT => DAC_OUT,
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-- paper tape reader uses RS232
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-- paper tape reader uses RS232
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RS232_DCE_RXD => RS232_DCE_RXD,
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RS232_DCE_RXD => RS232_DCE_RXD,
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RS232_DCE_TXD => RS232_DCE_TXD);
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RS232_DCE_TXD => RS232_DCE_TXD);
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with SW select
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with SW select
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LED <=
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LED <=
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std_logic_vector(PC(11-7 to 11)) when "0000",
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std_logic_vector(PC(11-7 to 11)) when "0000",
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IO(0 to 7) when others;
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IO(0 to 7) when others;
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SW_SENSE(1 to 4) <= SW(3 downto 0);
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SW_SENSE(1 to 4) <= SW(3 downto 0);
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Inst_debounce: debounce PORT MAP(
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Inst_debounce: debounce PORT MAP(
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clk => CLK,
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clk => CLK,
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clken => '1',
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clken => '1',
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input => BTN_EAST,
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input => BTN_EAST,
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output => SW_SENSE(5)
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output => SW_SENSE(5)
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);
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);
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end generate;
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end generate;
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end Behavioral;
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end Behavioral;
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