//Pepelatz_main.v
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//Pepelatz_main.v
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//This file is the main module of Pepelatz MISC processor. All other modules of Pepelatz must have their own files.
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//This file is the main module of Pepelatz MISC processor. All other modules of Pepelatz must have their own files.
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//Please, comment all in detail.
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//Please, comment all in detail.
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//Module Pepelatz contains the processor root.
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//Module Pepelatz contains the processor root.
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module Pepelatz
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module Pepelatz
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(
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(
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//ROM
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//ROM
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output[15:0]rom_address,//Address for ROM bus.
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output[15:0]rom_address,//Address for ROM bus.
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input [15:0]rom_data, //Data from ROM.
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input [15:0]rom_data, //Data from ROM.
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input rom_ready, //Shows, that rom_data has actual value.
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input rom_ready, //Shows, that rom_data has actual value.
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//RAM
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//RAM
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output ram_write, //Turn on writing mode.
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output ram_write, //Turn on writing mode.
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output[15:0]ram_adress, //Address for RAM bus.
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output[15:0]ram_adress, //Address for RAM bus.
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output[15:0]ram_input, //RAM's write port.
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output[15:0]ram_input, //RAM's write port.
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input [15:0]ram_data, //Data from RAM.
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input [15:0]ram_data, //Data from RAM.
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input ram_ready, //Shows, that ram_data has actual value.
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input ram_ready, //Shows, that ram_data has actual value.
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//Operations
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//Operations
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input clk, //Clock signal.
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input clk, //Clock signal.
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input rst //Reset signal.
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input rst //Reset signal.
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);
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);
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//Output regs used by Verilog. (Just remember: you must create a register for each output)
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//Output regs used by Verilog. (Just remember: you must create a register for each output)
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reg[15:0]rom_address;
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reg[15:0]rom_address;
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reg ram_write;
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reg ram_write;
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reg[15:0]ram_adress;
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reg[15:0]ram_adress;
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reg[15:0]ram_input;
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reg[15:0]ram_input;
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//Processor regs
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//Processor regs
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//Arithmetic stack
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//Arithmetic stack
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reg[5:0] StackPointer;
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reg[5:0] StackPointer;
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reg[15:0]Stack[0:63];
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reg[15:0]Stack[0:63];
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//Call stack
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//Call stack
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reg[3:0]CallPointer;
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reg[3:0]CallPointer;
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reg[15:0]CallStack[0:15];
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reg[15:0]CallStack[0:15];
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//Pointer to current command.
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//Pointer to current command.
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reg[15:0]PC;
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reg[15:0]PC;
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//Dark regs
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//Dark regs
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reg[15:0] command;//command for decoding
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reg[15:0] command;//command for decoding
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wire GetOperand;//if GetOperand==0 then get next command and place it into stack.
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wire GetOperand;//if GetOperand==0 then get next command and place it into stack.
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assign GetOperand=command[0];
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assign GetOperand=command[0];
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//Set of wires to instructions
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//Set of wires to instructions
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wire [4:0]instruction0;
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wire [4:0]instruction0;
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assign instruction0=command[5:1];
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assign instruction0=command[5:1];
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wire [4:0]instruction1;
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wire [4:0]instruction1;
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assign instruction1=command[11:6];
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assign instruction1=command[11:6];
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wire [4:0]instruction2;
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wire [4:0]instruction2;
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assign instruction2=command[15:12];
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assign instruction2=command[15:12];
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reg GetCommand;//if GetCommand=0, current command is not actual!
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reg GetCommand;//if GetCommand=0, current command is not actual.
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always@(posedge clk)//Main block
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always@(posedge clk)//Main block
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if (GetCommand==0) begin//Get command
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if (GetCommand==0) begin//Get command
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end else
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end else
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if (GetOperand==1) begin
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if (GetOperand==1) begin
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end else begin
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end else begin
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end//always
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end//always
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always@(posedge rst)//reset
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always@(posedge rst)//reset
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begin
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begin
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StackPointer=0;
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StackPointer=0;
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PC=0;
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PC=0;
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CallPointer=0;
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CallPointer=0;
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GetCommand=0;
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GetCommand=0;
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end
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end
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endmodule//Pepelatz
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endmodule//Pepelatz
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