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[/] [phr/] [branches/] [placas_1.0/] [placas/] [MOD/] [mod-aislador/] [mod-aislador.lst] - Diff between revs 82 and 85

Rev 82	Rev 85
`eeschema (2010-03-14)-final >> Creation date: mar 09 oct 2012 20:13:15 ART`	`eeschema (2010-03-14)-final >> Creation date: mar 09 oct 2012 20:13:15 ART`

`#Componentes ( orden = Referencia )`	`#Componentes ( orden = Referencia )`
`\| C1 0.1u`	`\| C1 0.1u`
`\| C2 0.1u`	`\| C2 0.1u`
`\| K1 jum_EN2`	`\| K1 jum_EN2`
`\| P1 FPGA`	`\| P1 FPGA`
`\| P2 IO aislados`	`\| P2 IO aislados`
`\| U1 ISO7242A`	`\| U1 ISO7242A`
`#Fin Componentes`	`#Fin Componentes`

`#Componentes ( orden = Valor )`	`#Componentes ( orden = Valor )`
`\| 0.1u C1`	`\| 0.1u C1`
`\| 0.1u C2`	`\| 0.1u C2`
`\| FPGA P1`	`\| FPGA P1`
`\| IO aislados P2`	`\| IO aislados P2`
`\| ISO7242A U1`	`\| ISO7242A U1`
`\| jum_EN2 K1`	`\| jum_EN2 K1`
`#Fin Componentes`	`#Fin Componentes`

`#Fin de Lista`	`#Fin de Lista`

Rev 82	Rev 85
`eeschema (2010-03-14)-final >> Creation date: mar 09 oct 2012 20:13:15 ART`	`eeschema (2010-03-14)-final >> Creation date: mar 09 oct 2012 20:13:15 ART`

`#Componentes ( orden = Referencia )`	`#Componentes ( orden = Referencia )`
`\| C1 0.1u`	`\| C1 0.1u`
`\| C2 0.1u`	`\| C2 0.1u`
`\| K1 jum_EN2`	`\| K1 jum_EN2`
`\| P1 FPGA`	`\| P1 FPGA`
`\| P2 IO aislados`	`\| P2 IO aislados`
`\| U1 ISO7242A`	`\| U1 ISO7242A`
`#Fin Componentes`	`#Fin Componentes`

`#Componentes ( orden = Valor )`	`#Componentes ( orden = Valor )`
`\| 0.1u C1`	`\| 0.1u C1`
`\| 0.1u C2`	`\| 0.1u C2`
`\| FPGA P1`	`\| FPGA P1`
`\| IO aislados P2`	`\| IO aislados P2`
`\| ISO7242A U1`	`\| ISO7242A U1`
`\| jum_EN2 K1`	`\| jum_EN2 K1`
`#Fin Componentes`	`#Fin Componentes`

`#Fin de Lista`	`#Fin de Lista`