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\hyphenation{prin-ci-pian-te e-ner-gí-a re-gu-la-da co-ne-xión}
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\begin{document}
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\begin{document}
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\begin{poster}{
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\begin{poster}{
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{ %Poster title
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{ %Poster title
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\vspace {2.4cm}
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\vspace {2.4cm}
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\huge \sffamily Plataforma de Hardware Reconfigurable
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\huge \sffamily Plataforma de Hardware Reconfigurable
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}
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}
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{ % poster Authors
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{ % poster Authors
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\large{\\[0.5ex]
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\large{\\[0.5ex]
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Luis Alberto Guanuco (lguanuco@electronica.frc.utn.edu.ar)\\
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Luis Alberto Guanuco (lguanuco@electronica.frc.utn.edu.ar)\\
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Sergio Daniel Olmedo (solmedo@scdt.frc.utn.edu.ar)\\
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Maximiliano Quinteros (50214@electronica.frc.utn.edu.ar)} \\
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Alexis Maximiliano Quinteros (50214@electronica.frc.utn.edu.ar)}
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Sergio Daniel Olmedo (solmedo@scdt.frc.utn.edu.ar)
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}
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}
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{ % University logo (top-right logo)
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{ % University logo (top-right logo)
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\vspace {2cm}\\
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\vspace {1.9cm}\\
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\includegraphics[height=0.030\textheight]{UTNlogo.pdf} \\
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%\vspace {0.5cm} \\
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\\
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\includegraphics[height=0.035\textheight]{CUDARlogo.pdf}
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\headerbox{Introducción} {name=contribution,column=0,row=0,span=3}{
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\headerbox{Introducción} {name=contribution,column=0,row=0,span=3}{
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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El proyecto \emph{Plataforma de Hardware Reconfigurable} (PHR) tiene como objetivo principal desarrollar recursos académicos para la difusión y actualización tecnológica relacionados al área digital a través de Dispositivos Lógicos Programables (PLDs).
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El proyecto \emph{Plataforma de Hardware Reconfigurable} (PHR) tiene como objetivo principal desarrollar recursos académicos para la difusión y actualización tecnológica relacionados al área digital a través de Dispositivos Lógicos Programables (PLDs).
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El desarrollo comprende el diseño de hardware y software que se publican bajo licencias libres.
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El desarrollo comprende el diseño de hardware y software que se publican bajo licencias libres.
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}
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}
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\headerbox{Características de la PHR}{name=dos,column=0,below=contribution, span=3}{
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\headerbox{Características de la PHR}{name=dos,column=0,below=contribution, span=3}{
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\begin{description}
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\begin{description}
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\compresslist
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\item [FPGA:] Xilinx Spartan-3A XC3S200A (encapsulado VQG100).
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\item [FPGA:] Xilinx Spartan-3A XC3S200A (encapsulado VQG100).
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\item [Memoria PROM:] Xilinx XCF02S.
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\item [Memoria PROM:] Xilinx XCF02S.
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\item [Voltaje de entrada:] 5V.
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\item [Voltaje de entrada:] 5V.
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\item [Relojes:] Un reloj fijo y tres seleccionables:
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\item [Relojes:] Un reloj fijo y tres seleccionables:
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\begin{description}
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\begin{description}
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\compresslist
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\item [Clock 0:] 50 MHz.
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\item [Clock 0:] 50 MHz.
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\item [Clock 1:] 16 MHz, 1 MHz, 500 kHz y 250 kHz.
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\item [Clock 1:] 16 MHz, 1 MHz, 500 kHz y 250 kHz.
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\item [Clock 2:] 125 kHz, 62.5 kHz, 31.25 kHz, 15.625 kHz.
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\item [Clock 2:] 125 kHz, 62.5 kHz, 31.25 kHz, 15.625 kHz.
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\item [Clock 3:] 3.9062 kHz, 1.9531 kHz, 976,56251 Hz.
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\item [Clock 3:] 3.9062 kHz, 1.9531 kHz, 976,56251 Hz.
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\end{description}
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\end{description}
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\item [Conectores con E/S de propósito general:] 28 pines en total.
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\item [Conectores con E/S de propósito general:] 28 pines en total.
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\item [Periféricos:] 8 LEDs, 8 llaves (DIP switch), 4 pulsadores, Display de 7 segmentos cuádruple, Puerto serie.
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\item [Periféricos:] 8 LEDs, 8 llaves (DIP switch), 4 pulsadores, Display de 7 segmentos cuádruple, Puerto serie.
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\end{description}
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\end{description}
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}
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}
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\headerbox{Diagrama de bloques}{name=tres,column=3,row=0,span=3}{
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\headerbox{Diagrama de bloques}{name=tres,column=3,row=0,span=3}{
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\begin{center}
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\begin{center}
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\includegraphics[width=0.94\textwidth]{block.pdf}
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\includegraphics[width=0.94\textwidth]{block.pdf}
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\end{center}
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}
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}
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\headerbox{Placas del proyecto}{name=diez,column=0,below=dos,span=4}{
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\headerbox{Placas del proyecto}{name=diez,column=0,below=dos,span=4}{
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\begin{center}
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\begin{center}
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\includegraphics[height=0.23\textwidth]{phr.png}\hspace{2em}
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\includegraphics[height=0.23\textwidth]{phr.png}\hspace{2em}
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\includegraphics[height=0.25\textwidth]{phr_top.png}
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\includegraphics[height=0.25\textwidth]{phr_top.png}
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\end{center}
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\end{center}
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La PHR consiste fundamentalmente en tres módulos
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La PHR consiste fundamentalmente en tres módulos
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de soporte físico. El módulo principal es la \emph{placa PHR} donde se encuentran el chip FPGA, relojes,
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de soporte físico. El módulo principal es la \emph{placa PHR} donde se encuentran el chip FPGA, su memoria de configuración, relojes,
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interfaces de entradas y salidas, periféricos (tales como LEDs, botones, llaves DIP, Displays de siete
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interfaces de entradas/salidas y periféricos tales como LEDs, botones, llaves (DIP) y displays de siete
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segmentos), etc. Además tiene conectores especiales para otros dos módulos sin los cuales la placa principal carece de funcionalidad.
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segmentos. Los módulos \emph{S3Power} y \emph{OOCDLink} ofrecen alimentación y conectividad con una computadora respectivammente.
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\begin{multicols}{2}
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\begin{multicols}{2}
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\subsection*{Placa S3Power}
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\subsection*{Placa S3Power}
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Fue desarrollada por el \emph{Instituto Nacional de Tecnología Industrial} (INTI) y está disponible libremente. Permite suministrar energía regulada con tres valores de tensión (1.2V, 2.5V y 3.3V) y distintas características de arranque.
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Fue desarrollada por el \emph{Instituto Nacional de Tecnología Industrial} (INTI) y está disponible libremente[1]. Permite suministrar energía regulada con tres valores de tensión (1.2V, 2.5V y 3.3V).
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La función la realiza principalmente el chip TPS75003 el cuál incluye un regulador lineal y controladores para dos fuentes conmutadas. %Los voltajes utilizados por la FPGA son de 1.2V, 2.5V y 3.3V.
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La función la realiza un dispositivo que integra un regulador lineal y controladores para dos fuentes conmutadas. %Los voltajes utilizados por la FPGA son de 1.2V, 2.5V y 3.3V.inci
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\begin{center}
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\begin{center}
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\includegraphics[height=0.247\textwidth]{s3power.png}
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\includegraphics[height=0.247\textwidth]{s3power.png}
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\end{center}
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\end{center}
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\columnbreak
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\columnbreak
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\subsection*{Placa OOCDLink}
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\subsection*{Placa OOCDLink}
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\vspace{-0.13cm}
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\vspace{-0.13cm}
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Facilita la comunicación entre una computadora y la placa PHR. Su característica modular, o de circuito separado de la placa PHR principal, hace que su utilización no quede restringida a la FPGA y posibilita la interacción con los multiples dispositivos que soportan JTAG.
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Facilita la comunicación entre una computadora y la placa PHR. Su característica modular, o de circuito separado de la placa PHR principal, hace que su utilización no quede restringida a la FPGA y posibilita la interacción con los multiples dispositivos que soportan JTAG.
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Utiliza el chip FT2232D que establece una interfaz JTAG controlable mediante una conexión USB.
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El dispositivo central controla mediante una conexión USB protocolos de comunicación serial como JTAG, SPI e I2C.
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\vspace{-0.55cm}
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\vspace{-0.55cm}
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\begin{center}
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\begin{center}
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\includegraphics[height=0.25\textwidth]{oocdlink.png}
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\includegraphics[height=0.25\textwidth]{oocdlink.png}
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\end{center}
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\end{center}
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\end{multicols}
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\end{multicols}
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}
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}
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\headerbox{Configuración de la FPGA}{name=trece,column=4,below=dos, span=2}{
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\headerbox{Configuración de la FPGA}{name=trece,column=4,below=dos, span=2}{
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\begin{center}
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\begin{center}
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\includegraphics[width=.9\textwidth]{front-end.pdf}
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\includegraphics[width=.86\textwidth]{front-end-raster.png}
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\end{center}
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\end{center}
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Para transferir el diseño del usuario a la FPGA, PHR se sirve de las funciones de \textbf{xc3sprog}, un conjunto de aplicaciones de licencia libre que funciona en linea de comandos y que puede programar varios dispositivos mediante JTAG.
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Para transferir el diseño del usuario a la FPGA, PHR se sirve de las funciones de \textbf{xc3sprog} [2], un conjunto de aplicaciones de licencia libre que funciona en linea de comandos y que puede programar varios dispositivos mediante JTAG.
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No obstante su funcionalidad, xc3sprog puede resultar no intuitivo para el usuario principiante,
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No obstante su funcionalidad, xc3sprog puede resultar no intuitivo para el usuario principiante,
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por lo que se ofrece una interfaz gráfica para invocar a xc3sprog de una manera muy simple.
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por lo que se ofrece una interfaz gráfica que permite invocar a xc3sprog de una manera muy simple.
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}
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}
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\headerbox{Información adicional}{name=xtra,column=4,below=trece, span=2}{
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\headerbox{Información adicional}{name=xtra,column=4,below=trece, span=2}{
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Toda la información del proyecto, incluyendo manuales y PCBs, se encuentra disponible en forma libre y puede accederse a través del sitio web \textbf{http://opencores.org/project,phr}.
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Toda la información del proyecto, incluyendo manuales y PCBs, se encuentra disponible en forma libre y puede accederse a través del sitio web \textbf{http://opencores.org/project,phr}.
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}
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}
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\headerbox{Referencias}{name=ref,column=4,below=xtra, span=2}{
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\headerbox{Referencias}{name=ref,column=4,below=xtra, span=2}{
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[1] \emph{Módulo de alimentación para placas con dispositivos FPGA}, Christian Huy y Diego
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[1] \emph{Módulo de alimentación para placas con dispositivos FPGA}, Christian Huy y Diego
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Brengi, \emph{Instituto Nacional de Tecnología Industrial}.
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Brengi, \emph{Instituto Nacional de Tecnología Industrial}.
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[2] http://xc3sprog.sourceforge.net
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}
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}
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\end{poster}
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\end{poster}
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\end{document}
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\end{document}
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