/* PID controller
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/* PID controller
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Author: Zhu Xu
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Email: m99a1@yahoo.cn
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sigma=Ki*e(n)+sigma
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sigma=Ki*e(n)+sigma
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u(n)=(Kp+Kd)*e(n)+sigma+Kd*(-e(n-1))
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u(n)=(Kp+Kd)*e(n)+sigma+Kd*(-e(n-1))
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Data width of Wishbone slave port can be can be toggled between 64-bit, 32-bit and 16-bit.
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Data width of Wishbone slave port can be can be toggled between 64-bit, 32-bit and 16-bit.
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Address width of Wishbone slave port can be can be modified by changing parameter adr_wb_nb.
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Address width of Wishbone slave port can be can be modified by changing parameter adr_wb_nb.
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Wishbone compliant
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Wishbone compliant
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Work as Wishbone slave, support Classic standard SINGLE/BLOCK READ/WRITE Cycle
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Work as Wishbone slave, support Classic standard SINGLE/BLOCK READ/WRITE Cycle
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registers or wires
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registers or wires
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[15:0]kp,ki,kd,sp,pv; can be both read and written through Wishbone interface, address: 0x0, 0x4, 0x8, 0xc, 0x10
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[15:0]kp,ki,kd,sp,pv; can be both read and written through Wishbone interface, address: 0x0, 0x4, 0x8, 0x12, 0x16
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[15:0]kpd; read only through Wishbone interface, address: 0x14
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[15:0]kpd; read only through Wishbone interface, address: 0x20
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[15:0]err[0:1]; read only through Wishbone interface, address: 0x18, 0x1c
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[15:0]err[0:1]; read only through Wishbone interface, address: 0x24, 0x28
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[15:0]mr,md; not accessable through Wishbone interface
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[15:0]mr,md; not accessable through Wishbone interface
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[31:0]p,b; not accessable through Wishbone interface
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[31:0]p,b; not accessable through Wishbone interface
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[31:0]un,sigma; read only through Wishbone interface, address: 0x20, 0x24
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[31:0]un,sigma; read only through Wishbone interface, address: 0x32, 0x36
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[4:0]OF; overflow register, read only through Wishbone interface, address: 0x28
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[4:0]of; overflow register, read only through Wishbone interface, address: 0x40
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OF[0]==1 : kpd overflow
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of[0]==1 : kpd overflow
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OF[1]==1 : err[0] overflow
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of[1]==1 : err[0] overflow
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OF[2]==1 : err[1] overflow
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of[2]==1 : err[1] overflow
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OF[3]==1 : un overflow
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of[3]==1 : un overflow
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OF[4]==1 : sigma overflow
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of[4]==1 : sigma overflow
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[0:15]rl; read lock, when asserted corelated reagister can not be read through Wishbone interface
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[0:15]rl; read lock, when asserted corelated reagister can not be read through Wishbone interface
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[0:7]wl; write lock, when asserted corelated reagister can not be written through Wishbone interface
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[0:7]wl; write lock, when asserted corelated reagister can not be written through Wishbone interface
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*/
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*/
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`include "PID_defines.v"
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`include "PID_defines.v"
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module PID #(
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module PID #(
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`ifdef wb_16bit
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`ifdef wb_16bit
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parameter wb_nb=16,
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parameter wb_nb=16,
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`endif
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`endif
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`ifdef wb_32bit
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`ifdef wb_32bit
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parameter wb_nb=32,
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parameter wb_nb=32,
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`endif
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`endif
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`ifdef wb_64bit
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`ifdef wb_64bit
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parameter wb_nb=64,
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parameter wb_nb=64,
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`endif
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`endif
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adr_wb_nb=16
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adr_wb_nb=16
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)(
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)(
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//Wishbone Slave Interface
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input i_clk,
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input i_clk,
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input i_rst,
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input i_rst, //reset when low
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//Wishbone Slave port
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input i_wb_cyc,
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input i_wb_cyc,
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input i_wb_stb,
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input i_wb_stb,
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input i_wb_we,
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input i_wb_we,
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input [adr_wb_nb-1:0]i_wb_adr,
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input [adr_wb_nb-1:0]i_wb_adr,
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input [wb_nb-1:0]i_wb_data,
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input [wb_nb-1:0]i_wb_data,
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output o_wb_ack,
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output o_wb_ack,
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output [wb_nb-1:0]o_wb_data,
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output [wb_nb-1:0]o_wb_data,
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//u(n) output
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//u(n) output
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output [31:0]o_un,
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output [31:0]o_un,
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output o_valid
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output o_valid
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);
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);
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parameter kp_adr = 0,
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parameter kp_adr = 0,
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ki_adr = 1,
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ki_adr = 1,
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kd_adr = 2,
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kd_adr = 2,
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sp_adr = 3,
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sp_adr = 3,
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pv_adr = 4,
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pv_adr = 4,
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kpd_adr = 5,
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kpd_adr = 5,
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err_0_adr = 6,
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err_0_adr = 6,
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err_1_adr = 7,
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err_1_adr = 7,
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un_adr = 8,
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un_adr = 8,
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sigma_adr = 9,
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sigma_adr = 9,
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OF_adr = 10;
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of_adr = 10;
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wire rst;
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assign rst=~i_rst;
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reg [15:0]kp,ki,kd,sp,pv;
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reg [15:0]kp,ki,kd,sp,pv;
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reg wlkp,wlki,wlkd,wlsp,wlpv;
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reg wlkp,wlki,wlkd,wlsp,wlpv; // write lock, if one is high the relevant reg is not writeable
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wire [0:7]wl={wlkp,wlki,wlkd,wlsp,wlpv,3'h0};
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wire [0:7]wl={wlkp,wlki,wlkd,wlsp,wlpv,3'h0}; // write lock
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reg wack; //write acknowledged
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reg wack; //write acknowledged
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wire [2:0]adr;
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wire [2:0]adr;
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`ifdef wb_16bit
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`ifdef wb_16bit
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assign adr=i_wb_adr[3:1];
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assign adr=i_wb_adr[3:1];
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`endif
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`endif
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`ifdef wb_32bit
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`ifdef wb_32bit
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assign adr=i_wb_adr[4:2];
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assign adr=i_wb_adr[4:2];
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`endif
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`endif
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`ifdef wb_64bit
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`ifdef wb_64bit
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assign adr=i_wb_adr[5:3];
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assign adr=i_wb_adr[5:3];
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`endif
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`endif
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wire [3:0]adr_1;
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wire [3:0]adr_1;
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`ifdef wb_32bit
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`ifdef wb_32bit
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assign adr_1=i_wb_adr[5:2];
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assign adr_1=i_wb_adr[5:2];
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`endif
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`endif
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`ifdef wb_16bit
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`ifdef wb_16bit
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assign adr_1=i_wb_adr[4:1];
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assign adr_1=i_wb_adr[4:1];
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`endif
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`endif
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`ifdef wb_64bit
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`ifdef wb_64bit
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assign adr_1=i_wb_adr[6:3];
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assign adr_1=i_wb_adr[6:3];
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`endif
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`endif
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wire we; // write enable
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wire we; // write enable
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assign we=i_wb_cyc&i_wb_we&i_wb_stb;
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assign we=i_wb_cyc&i_wb_we&i_wb_stb;
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wire re; //read enable
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wire re; //read enable
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assign re=i_wb_cyc&(~i_wb_we)&i_wb_stb;
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assign re=i_wb_cyc&(~i_wb_we)&i_wb_stb;
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reg state_0; //state machine No.1's state register
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reg state_0; //state machine No.1's state register
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wire adr_check_1;
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wire adr_check_1;
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`ifdef wb_32bit
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`ifdef wb_32bit
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assign adr_check_1=i_wb_adr[adr_wb_nb-1:6]==0;
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assign adr_check_1=i_wb_adr[adr_wb_nb-1:6]==0;
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`endif
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`endif
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`ifdef wb_16bit
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`ifdef wb_16bit
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assign adr_check_1=i_wb_adr[adr_wb_nb-1:5]==0;
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assign adr_check_1=i_wb_adr[adr_wb_nb-1:5]==0;
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`endif
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`endif
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`ifdef wb_64bit
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`ifdef wb_64bit
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assign adr_check_1=i_wb_adr[adr_wb_nb-1:7]==0;
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assign adr_check_1=i_wb_adr[adr_wb_nb-1:7]==0;
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`endif
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`endif
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wire adr_check; //check address's correctness
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wire adr_check; //check address's correctness
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`ifdef wb_16bit
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`ifdef wb_16bit
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assign adr_check=i_wb_adr[4]==0&&adr_check_1;
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assign adr_check=i_wb_adr[4]==0&&adr_check_1;
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`endif
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`endif
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`ifdef wb_32bit
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`ifdef wb_32bit
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assign adr_check=i_wb_adr[5]==0&&adr_check_1;
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assign adr_check=i_wb_adr[5]==0&&adr_check_1;
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`endif
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`endif
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`ifdef wb_64bit
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`ifdef wb_64bit
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assign adr_check=i_wb_adr[6]==0&&adr_check_1;
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assign adr_check=i_wb_adr[6]==0&&adr_check_1;
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`endif
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`endif
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//state machine No.1
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//state machine No.1
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always@(posedge i_clk or negedge rst)
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always@(posedge i_clk or posedge i_rst)
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if(!rst)begin
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if(i_rst)begin
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state_0<=0;
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state_0<=0;
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wack<=0;
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wack<=0;
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kp<=0;
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kp<=0;
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ki<=0;
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ki<=0;
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kd<=0;
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kd<=0;
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sp<=0;
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sp<=0;
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pv<=0;
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pv<=0;
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end
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end
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else begin
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else begin
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if(wack&&(!i_wb_stb)) wack<=0;
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if(wack&&(!i_wb_stb)) wack<=0;
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case(state_0)
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case(state_0)
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0: begin
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0: begin
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if(we&&(!wack)) state_0<=1;
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if(we&&(!wack)) state_0<=1;
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end
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end
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1: begin
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1: begin
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if(adr_check)begin
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if(adr_check)begin
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if(!wl[adr])begin
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if(!wl[adr])begin
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wack<=1;
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wack<=1;
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state_0<=0;
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state_0<=0;
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case(adr)
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case(adr)
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0: begin
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0: begin
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kp<=i_wb_data[15:0];
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kp<=i_wb_data[15:0];
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end
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end
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1: begin
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1: begin
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ki<=i_wb_data[15:0];
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ki<=i_wb_data[15:0];
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end
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end
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2: begin
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2: begin
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kd<=i_wb_data[15:0];
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kd<=i_wb_data[15:0];
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end
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end
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3: begin
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3: begin
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sp<=i_wb_data[15:0];
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sp<=i_wb_data[15:0];
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end
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end
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4: begin
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4: begin
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pv<=i_wb_data[15:0];
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pv<=i_wb_data[15:0];
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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else begin
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else begin
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wack<=1;
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wack<=1;
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state_0<=0;
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state_0<=0;
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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//state machine No.2
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//state machine No.2
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reg [14:0]state_2;
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reg [11:0]state_1;
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reg state_1;
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wire update_kpd;
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wire update_kpd;
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assign update_kpd=wack&&(~adr[2])&&(~adr[0])&&adr_check; //adr==0||adr==2
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assign update_kpd=wack&&(~adr[2])&&(~adr[0])&&adr_check; //adr==0||adr==2
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wire update_esu; //update e(n), sigma and u(n)
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wire update_esu; //update e(n), sigma and u(n)
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assign update_esu=wack&&(adr==4)&&adr_check;
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assign update_esu=wack&&(adr==4)&&adr_check;
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reg rlkpd;
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reg rlkpd; // read lock
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reg rlerr_0;
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reg rlerr_0; // read lock
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reg rlerr_1;
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reg rlerr_1; // read lock
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reg rla;
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reg rla; // read lock
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reg rlsigma;
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reg rlsigma; // read lock
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reg rlOF;
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reg rlof; // read lock
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reg [4:0]OF;
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reg [4:0]of;
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reg [15:0]kpd;
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reg [15:0]kpd;
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reg [15:0]err[0:1];
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reg [15:0]err[0:1];
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wire [15:0]mr,md;
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wire [15:0]mr,md;
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reg [31:0]p;
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reg [31:0]p;
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reg [31:0]a,sigma,un;
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reg [31:0]a,sigma,un;
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reg start; //start signal for multiplier
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reg start; //start signal for multiplier
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reg [1:0]mr_index;
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reg [1:0]mr_index;
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reg md_index;
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reg md_index;
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assign mr= mr_index==1?kpd:
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assign mr= mr_index==1?kpd:
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mr_index==2?kd:ki;
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mr_index==2?kd:ki;
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assign md= md_index?err[1]:err[0];
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assign md= md_index?err[1]:err[0];
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reg cout;
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reg cout;
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wire cin;
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wire cin;
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wire [31:0]sum;
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wire [31:0]sum;
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wire [31:0]product;
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wire [31:0]product;
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wire OF_addition[0:1];
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wire of_addition[0:1];
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assign OF_addition[0]=(p[15]&&a[15]&&(!sum[15]))||((!p[15])&&(!a[15])&&sum[15]);
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assign of_addition[0]=(p[15]&&a[15]&&(!sum[15]))||((!p[15])&&(!a[15])&&sum[15]);
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assign OF_addition[1]=(p[31]&&a[31]&&(!sum[31]))||((!p[31])&&(!a[31])&&sum[31]);
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assign of_addition[1]=(p[31]&&a[31]&&(!sum[31]))||((!p[31])&&(!a[31])&&sum[31]);
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always@(posedge i_clk or posedge i_rst)
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if(i_rst)begin
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reg [31:0]reg_sum;
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state_1<=12'b000000000001;
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reg [31:0]reg_product;
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reg reg_OF_addition[0:1];
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always@(posedge i_clk)begin
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reg_sum<=sum;
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reg_OF_addition[0]<=OF_addition[0];
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reg_OF_addition[1]<=OF_addition[1];
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reg_product<=product;
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end
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always@(posedge i_clk or negedge rst)
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if(!rst)begin
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state_1<=0;
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state_2<=15'b000000000000001;
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wlkp<=0;
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wlkp<=0;
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wlki<=0;
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wlki<=0;
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wlkd<=0;
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wlkd<=0;
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wlsp<=0;
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wlsp<=0;
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wlpv<=0;
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wlpv<=0;
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rlkpd<=0;
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rlkpd<=0;
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rlerr_0<=0;
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rlerr_0<=0;
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rlerr_1<=0;
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rlerr_1<=0;
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rla<=0;
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rla<=0;
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rlsigma<=0;
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rlsigma<=0;
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rlOF<=0;
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rlof<=0;
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OF<=0;
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of<=0;
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kpd<=0;
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kpd<=0;
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err[0]<=0;
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err[0]<=0;
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err[1]<=0;
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err[1]<=0;
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p<=0;
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p<=0;
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a<=0;
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a<=0;
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sigma<=0;
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sigma<=0;
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un<=0;
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un<=0;
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start<=0;
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start<=0;
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mr_index<=0;
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mr_index<=0;
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md_index<=0;
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md_index<=0;
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cout<=0;
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cout<=0;
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end
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end
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else begin
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else begin
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case(state_1)
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case(state_1)
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1: state_1<=0;
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12'b000000000001: begin
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0:begin
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case(state_2)
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15'b0000000000001: begin
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if(update_kpd)begin
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if(update_kpd)begin
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state_2<=15'b000000000000010;
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state_1<=12'b000000000010;
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wlkp<=1;
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wlkp<=1;
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wlkd<=1;
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wlkd<=1;
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wlpv<=1;
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wlpv<=1;
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rlkpd<=1;
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rlkpd<=1;
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rlOF<=1;
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rlof<=1;
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end
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end
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else if(update_esu)begin
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else if(update_esu)begin
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state_2<=15'b00000000001000;
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state_1<=12'b000000001000;
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wlkp<=1;
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wlkp<=1;
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wlki<=1;
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wlki<=1;
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wlkd<=1;
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wlkd<=1;
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wlsp<=1;
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wlsp<=1;
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wlpv<=1;
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wlpv<=1;
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rlkpd<=1;
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rlkpd<=1;
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rlerr_0<=1;
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rlerr_0<=1;
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rlerr_1<=1;
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rlerr_1<=1;
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rla<=1;
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rla<=1;
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rlsigma<=1;
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rlsigma<=1;
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rlOF<=1;
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rlof<=1;
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end
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end
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end
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end
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15'b000000000000010: begin
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12'b000000000010: begin
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p<={{16{kp[15]}},kp};
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p<={{16{kp[15]}},kp};
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a<={{16{kd[15]}},kd};
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a<={{16{kd[15]}},kd};
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state_2<=15'b000000000000100;
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state_1<=12'b000000000100;
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state_1<=1;
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end
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end
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15'b000000000000100: begin
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12'b000000000100: begin
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kpd<=reg_sum[15:0];
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kpd<=sum[15:0];
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wlkp<=0;
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wlkp<=0;
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wlkd<=0;
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wlkd<=0;
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wlpv<=0;
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wlpv<=0;
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rlkpd<=0;
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rlkpd<=0;
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rlOF<=0;
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rlof<=0;
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OF[0]<=reg_OF_addition[0];
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of[0]<=of_addition[0];
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state_2<=15'b000000000000001;
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state_1<=12'b000000000001;
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end
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end
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15'b000000000001000: begin
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12'b000000001000: begin
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p<={{16{~err[0][15]}},~err[0]};
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p<={{16{~err[0][15]}},~err[0]};
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a<={31'b0,1'b1};
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a<={31'b0,1'b1};
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state_2<=15'b000000000010000;
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state_1<=12'b000000010000;
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end
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end
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15'b000000000010000: begin
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12'b000000010000: begin
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state_2<=15'b000000000100000;
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err[1]<=sum[15:0];
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of[2]<=of[1];
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p<={{16{sp[15]}},sp};
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p<={{16{sp[15]}},sp};
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a<={{16{~pv[15]}},~pv};
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a<={{16{~pv[15]}},~pv};
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cout<=1;
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cout<=1;
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state_1<=12'b000000100000;
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end
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end
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15'b000000000100000: begin
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12'b000000100000: begin
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err[1]<=reg_sum[15:0];
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err[0]<=sum[15:0];
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OF[2]<=OF[1];
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of[1]<=of_addition[0];
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state_2<=15'b000000001000000;
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end
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15'b000000001000000: begin
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err[0]<=reg_sum[15:0];
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OF[1]<=reg_OF_addition[0];
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cout<=0;
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cout<=0;
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start<=1;
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start<=1;
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state_2<=15'b000000010000000;
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state_1<=12'b000001000000;
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end
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end
|
15'b000000010000000: begin
|
12'b000001000000: begin
|
mr_index<=1;
|
mr_index<=1;
|
state_2<=15'b000000100000000;
|
state_1<=12'b000010000000;
|
end
|
end
|
15'b000000100000000: begin
|
12'b000010000000: begin
|
mr_index<=2;
|
mr_index<=2;
|
md_index<=1;
|
md_index<=1;
|
state_2<=15'b000001000000000;
|
state_1<=12'b000100000000;
|
end
|
end
|
15'b000001000000000: begin
|
12'b000100000000: begin
|
mr_index<=0;
|
mr_index<=0;
|
md_index<=0;
|
md_index<=0;
|
start<=0;
|
start<=0;
|
state_2<=15'b000010000000000;
|
p<=product;
|
end
|
|
15'b000010000000000: begin
|
|
p<=reg_product;
|
|
a<=sigma;
|
a<=sigma;
|
state_2<=15'b000100000000000;
|
state_1<=12'b001000000000;
|
|
|
end
|
end
|
15'b000100000000000: begin
|
12'b001000000000: begin
|
//need modi
|
a<=sum;
|
|
sigma<=sum;
|
p<=reg_product;
|
of[3]<=of[4]|of_addition[1];
|
|
of[4]<=of[4]|of_addition[1];
|
state_2<=15'b001000000000000;
|
p<=product;
|
end
|
state_1<=12'b010000000000;
|
15'b001000000000000: begin
|
|
|
end
|
a<=reg_product;
|
12'b010000000000: begin
|
sigma<=reg_sum;
|
a<=sum;
|
OF[3]<=OF[4]|reg_OF_addition[1];
|
of[3]<=of[3]|of_addition[1];
|
OF[4]<=OF[4]|reg_OF_addition[1];
|
p<=product;
|
state_1<=1;
|
state_1<=12'b100000000000;
|
|
end
|
state_2<=15'b010000000000000;
|
12'b100000000000: begin
|
|
un<=sum;
|
end
|
of[3]<=of[3]|of_addition[1];
|
15'b010000000000000: begin
|
state_1<=12'b000000000001;
|
a<=reg_sum; //Kpd*err0-Kd*err1
|
|
p<=sigma;
|
|
OF[3]<=OF[3]|reg_OF_addition[1];
|
|
state_1<=1;
|
|
state_2<=15'b100000000000000;
|
|
end
|
|
15'b100000000000000: begin
|
|
un<=reg_sum;
|
|
OF[3]<=OF[3]|reg_OF_addition[1];
|
|
state_2<=15'b000000000000001;
|
|
wlkp<=0;
|
wlkp<=0;
|
wlki<=0;
|
wlki<=0;
|
wlkd<=0;
|
wlkd<=0;
|
wlsp<=0;
|
wlsp<=0;
|
wlpv<=0;
|
wlpv<=0;
|
rlkpd<=0;
|
rlkpd<=0;
|
rlerr_0<=0;
|
rlerr_0<=0;
|
rlerr_1<=0;
|
rlerr_1<=0;
|
rla<=0;
|
rla<=0;
|
rlsigma<=0;
|
rlsigma<=0;
|
rlOF<=0;
|
rlof<=0;
|
end
|
|
endcase
|
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
wire ready;
|
wire ready;
|
multiplier_16x16bit_pipelined multiplier_16x16bit_pipelined(
|
multiplier_16x16bit_pipelined multiplier_16x16bit_pipelined(
|
i_clk,
|
i_clk,
|
rst,
|
~i_rst,
|
start,
|
start,
|
md,
|
md,
|
mr,
|
mr,
|
product,
|
product,
|
ready
|
ready
|
);
|
);
|
|
|
adder_32bit adder_32bit_0(
|
adder_32bit adder_32bit_0(
|
a,
|
a,
|
p,
|
p,
|
cout,
|
cout,
|
sum,
|
sum,
|
cin
|
cin
|
);
|
);
|
|
|
|
|
wire [wb_nb-1:0]rdata[0:15]; //wishbone read data array
|
wire [wb_nb-1:0]rdata[0:15]; //wishbone read data array
|
`ifdef wb_16bit
|
`ifdef wb_16bit
|
assign rdata[0]=kp;
|
assign rdata[0]=kp;
|
assign rdata[1]=ki;
|
assign rdata[1]=ki;
|
assign rdata[2]=kd;
|
assign rdata[2]=kd;
|
assign rdata[3]=sp;
|
assign rdata[3]=sp;
|
assign rdata[4]=pv;
|
assign rdata[4]=pv;
|
assign rdata[5]=kpd;
|
assign rdata[5]=kpd;
|
assign rdata[6]=err[0];
|
assign rdata[6]=err[0];
|
assign rdata[7]=err[1];
|
assign rdata[7]=err[1];
|
assign rdata[8]=un[15:0];
|
assign rdata[8]=un[15:0];
|
assign rdata[9]=sigma[15:0];
|
assign rdata[9]=sigma[15:0];
|
assign rdata[10]={11'b0,OF};
|
assign rdata[10]={11'b0,of};
|
`endif
|
`endif
|
|
|
`ifdef wb_32bit
|
`ifdef wb_32bit
|
assign rdata[0]={{16{kp[15]}},kp};
|
assign rdata[0]={{16{kp[15]}},kp};
|
assign rdata[1]={{16{ki[15]}},ki};
|
assign rdata[1]={{16{ki[15]}},ki};
|
assign rdata[2]={{16{kd[15]}},kd};
|
assign rdata[2]={{16{kd[15]}},kd};
|
assign rdata[3]={{16{sp[15]}},sp};
|
assign rdata[3]={{16{sp[15]}},sp};
|
assign rdata[4]={{16{pv[15]}},pv};
|
assign rdata[4]={{16{pv[15]}},pv};
|
assign rdata[5]={{16{kpd[15]}},kpd};
|
assign rdata[5]={{16{kpd[15]}},kpd};
|
assign rdata[6]={{16{err[0][15]}},err[0]};
|
assign rdata[6]={{16{err[0][15]}},err[0]};
|
assign rdata[7]={{16{err[1][15]}},err[1]};
|
assign rdata[7]={{16{err[1][15]}},err[1]};
|
assign rdata[8]=un;
|
assign rdata[8]=un;
|
assign rdata[9]=sigma;
|
assign rdata[9]=sigma;
|
assign rdata[10]={27'b0,OF};
|
assign rdata[10]={27'b0,of};
|
`endif
|
`endif
|
|
|
`ifdef wb_64bit
|
`ifdef wb_64bit
|
assign rdata[0]={{48{kp[15]}},kp};
|
assign rdata[0]={{48{kp[15]}},kp};
|
assign rdata[1]={{48{ki[15]}},ki};
|
assign rdata[1]={{48{ki[15]}},ki};
|
assign rdata[2]={{48{kd[15]}},kd};
|
assign rdata[2]={{48{kd[15]}},kd};
|
assign rdata[3]={{48{sp[15]}},sp};
|
assign rdata[3]={{48{sp[15]}},sp};
|
assign rdata[4]={{48{pv[15]}},pv};
|
assign rdata[4]={{48{pv[15]}},pv};
|
assign rdata[5]={{48{kpd[15]}},kpd};
|
assign rdata[5]={{48{kpd[15]}},kpd};
|
assign rdata[6]={{48{err[0][15]}},err[0]};
|
assign rdata[6]={{48{err[0][15]}},err[0]};
|
assign rdata[7]={{48{err[1][15]}},err[1]};
|
assign rdata[7]={{48{err[1][15]}},err[1]};
|
assign rdata[8]={{32{un[31]}},un};
|
assign rdata[8]={{32{un[31]}},un};
|
assign rdata[9]={{32{sigma[31]}},sigma};
|
assign rdata[9]={{32{sigma[31]}},sigma};
|
assign rdata[10]={59'b0,OF};
|
assign rdata[10]={59'b0,of};
|
`endif
|
`endif
|
|
|
assign rdata[11]=0;
|
assign rdata[11]=0;
|
assign rdata[12]=0;
|
assign rdata[12]=0;
|
assign rdata[13]=0;
|
assign rdata[13]=0;
|
assign rdata[14]=0;
|
assign rdata[14]=0;
|
assign rdata[15]=0;
|
assign rdata[15]=0;
|
|
|
|
|
wire [0:15]rl;
|
wire [0:15]rl;
|
assign rl={5'b0,rlkpd,rlerr_0,rlerr_1,rla,rlsigma,rlOF,5'b0};
|
assign rl={5'b0,rlkpd,rlerr_0,rlerr_1,rla,rlsigma,rlof,5'b0};
|
|
|
wire rack; // wishbone read acknowledged
|
wire rack; // wishbone read acknowledged
|
assign rack=(re&adr_check_1&(~rl[adr_1]))|(re&(~adr_check_1));
|
assign rack=(re&adr_check_1&(~rl[adr_1]))|(re&(~adr_check_1));
|
|
|
assign o_wb_ack=(wack|rack)&i_wb_stb;
|
assign o_wb_ack=(wack|rack)&i_wb_stb;
|
|
|
assign o_wb_data=adr_check_1?rdata[adr_1]:0;
|
assign o_wb_data=adr_check_1?rdata[adr_1]:0;
|
assign o_un=un;
|
assign o_un=un;
|
assign o_valid=~rla;
|
assign o_valid=~rla;
|
|
|
|
|
|
|
