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Programmable Interval Timer (PIT)Specification
Author: Robert Hayes
rehayes@opencores.org
Rev. 0.1
TIME \@ "MMMM d, yyyy" April 13, 2009
This page has been intentionally left blank.
Revision History
Rev.DateAuthorDescription 0.114/04/09Robert HayesFirst draft release
Contents
TOC \t "Heading 3,2,Index,1,Appendix A,1,Heading 2 name,1,Appendix B,1" Introduction PAGEREF _Toc101247259 \h 1
FEATURES PAGEREF _Toc101247260 \h 1
Architecture PAGEREF _Toc101247261 \h 2
2.1 WISHBONE Interface PAGEREF _Toc101247262 \h 3
2.2 Control Registers PAGEREF _Toc101247263 \h 3
2.3 Prescale Counter PAGEREF _Toc101247264 \h 3
2.4 Main Counter PAGEREF _Toc101247265 \h 3
Operation PAGEREF _Toc101247266 \h 4
Registers PAGEREF _Toc101247267 \h 6
List of Registers PAGEREF _Toc101247268 \h 6
4.1 CNTRL Register PAGEREF _Toc101247269 \h 7
4.1 MOD Register PAGEREF _Toc101247270 \h 10
4.2 CNT Register PAGEREF _Toc101247271 \h 11
Clocks PAGEREF _Toc101247272 \h 13
IO Ports PAGEREF _Toc101247273 \h 14
6.1 WISHBONE Interface PAGEREF _Toc101247274 \h 15
6.2 PIT signals PAGEREF _Toc101247275 \h 16
6.3 PIT Core Parameters PAGEREF _Toc101247276 \h 17
Appendix A PAGEREF _Toc101247277 \h 19
Index PAGEREF _Toc101247278 \h 20
Introduction
The Programmable Interval Timer Module, PIT, is a simple timer to generate a periodic signal for a microcontroller system. This signal may be used for a variety of purposes such as triggering the start of an Analog to Digital or Digital to Analog conversion, as a periodic system interrupt, or to synchronize the start of various other hardware processes.
The PIT RTL code is parameterized so that every module instantiation can be customized to meet system requirements without wasting unneeded resources.
FEATURES
16 bit Main Counter with programmable modulo
15 bit Prescale Counter with programmable modulo selections
Slave mode for synchronizing multiple PIT modules
Interrupt or bit-polling
Static synchronous design
Fully synthesizable
Parameterized so each instance can be optimized for size
Architecture
The PIT core is built around four primary blocks; the WISHBONE Interface, the Control Registers, the Prescale Counter and the Main Counter.
Fig. 2.1 Internal structure PIT Core
2.1 WISHBONE Interface
The WISHBONE Interface isolates the PIT functionality from the WISHBONE bus. This interface takes the bus specific signals and generates a generic set of control signals to drive the PIT control registers. Isolating the WISHBONE bus should help promote PIT module reusability by localizing the scope of changes needed to retarget the PIT module to another bus environment.
2.2 Control Registers
The Command Register, Modulo Register and Count Register are combined into a single module that controls the programmable functions of the PIT. Various bits in the Command Register define the basic operating mode and function enables of the PIT.
2.3 Prescale Counter
The Prescale counter extends the range of the main counter. Using the Prescale counter reduces the timing granularity in terms of master clocks over which the period of the output interrupts can be controlled. As an example if the Prescale Counter modulo is set for a value of 10 then counts of 90 or 100 of the master clock could be decoded but not a master clock count of 95.
2.4 Main Counter
The Main Counter increments at a rate determined by the setting of the Prescale modulo value and the master clock frequency. Each time the Main Counter reaches the modulo value the PIT output signals are activated and the PIT FLAG status bit is set.
Operation
The PIT module is a very simple counter that can be controlled by commands from the WISHBONE bus. The output from the module is a pulse that is one wb_clk_i period wide at a frequency of:
pit_o = wb_clk_i / (MOD_VAL * PRE_SCALR)
Where MOD_VAL is a 16-bit register accessed from the WISHBONE bus and PRE_SCLAR is a four-bit value accessed from the WISHBONE bus that is decoded into 16 possible multiplier values.
Figure 3.1 is an illustration for the case of a PIT module operating with MOD_VAL=5 and PRE_SCLR=0. The start of the counters incrementing is determined by the setting of the CNT_EN bit in the control register. If the PIT module is operating in slave mode then the CNT_EN signal shown in the figure is actually the [ext_sync_i] signal that is controlled by the CNT_EN bit of the master PIT module. Note that the fall time of the signal [cnt_flag_o] is not explicitly defined because it is dependent on receiving a command from the WISHBONE bus to reset the FLAG register.
Fig. 3.1 PIT Signals, MOD_VAL=5
Figure 3.2 is an illustration of the timing relationships of a PIT module operating with MOD_VAL=4 and PRE_SCLR=1(Divide by 2).
Fig. 3.2 PIT Signals, MOD_VAL=4, PRE_SCLR=1
The recommended software procedure for using the PIT Module:
Initialize PIT Slave modules
Set MOD_VAL
Set SLAVE, PRE_SCALR, and ENA_INT
Initialize PIT Master module
Set MOD_VAL
Set SLAVE, PRE_SCALR, and ENA_INT
Set CNT_EN
Registers
The PIT module can be configured through the use of the DWIDTH parameter to have a WISHBONE bus interface with either an 8-bit bus with 8-bit granularity or to use a 16-bit bus with 16-bit granularity. This document shows the resultant address and bit field for both configurations although in an actual instance of the PIT module only one of the pairs of tables will be valid. For an end user or programmer reference it may be best to simplify this document by removing the tables that reference the unused bus configuration.
List of Registers
NameAddressWidthAccessDescriptionCNTRL0x0016RWPIT Control RegisterMOD0x0116RWPIT Modulo RegisterCNT0x0216RPIT Counter ValueTable SEQ Table \* ARABIC 1: List of registers, 16 bit data (default DWIDTH=16)
NameAddressWidthAccessDescriptionCNTRL_00x008RWPIT Control Register LowCNTRL_10x018RWPIT Control Register HighMOD_00x028RWPIT Modulo Register Low ByteMOD_10x038RWPIT Modulo Register High ByteCNT_00x048RPIT Counter Value Low ByteCNT_10x058RPIT Counter Value High ByteTable 1a: List of registers, 8 bit data (DWIDTH=8)
4.1 CNTRL Register
Bit #AccessDescription15RWSLAVE, Slave mode enable bit
When set to 1 the Prescaler Counter and the Main Counter are enabled by an external master mode PIT. This allows the slave mode PIT counters to be synchronized to the CNT_EN bit of the master mode PIT module.
When set to 0 the PIT counters are enabled by the CNT_EN bit.14RDECADE_CNTR, Returns the value of the DECADE_CNTR parameter13RNO_PRESCALE, Returns the value of the NO_PRESCALE parameter.12RReserved11:8RWPRE_SCALR, Prescale Counter modulo value.
Sets the period of the Prescale Counter in bus clocks. See Table 3
If the NO_PRESCALE parameter is set then this field will always return all zeros.7:3RReserved2WFLAG, Main counter rollover status flag.
Read - Returns the current status of the rollover status flag and the interrupt output state.
Write When set to 1 clears the FLAG status bit and the interrupt output. When set to 0 there is no effect.1WENA_INT, Interrupt enable.
When set to 1 the interrupt output is enabled.
When set to 0 the interrupt output is disabled. Clearing this bit only disables the interrupt output, it does not clear the source of the interrupt which is the FLAG status bit.0WCNT_EN, Prescale and Main Counter enable. Clearing this bit resets the Prescale and Main counter to their default state. This bit has no effect when the SLAVE bit is set. Reset Value: CNTRL: 0000hTable SEQ Table \* ARABIC 2: CNTRL Register Bits
Bit #AccessDescription7RWSLAVE, Slave mode enable bit
When set to 1 the Prescaler Counter and the Main Counter are enabled by an external master mode PIT. This allows the slave mode PIT counters to be synchronized to the CNT_EN bit of the master mode PIT module.
When set to 0 the PIT counters are enabled by the CNT_EN bit.6RDECADE_CNTR, Returns the value of the DECADE_CNTR parameter5RNO_PRESCALE, Returns the value of the NO_PRESCALE parameter.4RReserved3:0RWPRE_SCALR, Prescale Counter modulo value.
Sets the period of the Prescale Counter in bus clocks. See Table 3
If the NO_PRESCALE parameter is set then this field will always return all zeros.Reset Value:
CNTRL_1: 40h
Table 2a: CNTRL Register Bits
Bit #AccessDescription7:3RReserved2WFLAG, Main counter rollover status flag.
Read - Returns the current status of the rollover status flag and the interrupt output state.
Write When set to 1 clears the FLAG status bit and the interrupt output. When set to 0 there is no effect.1WENA_INT, Interrupt enable.
When set to 1 the interrupt output is enabled.
When set to 0 the interrupt output is disabled. Clearing this bit only disables the interrupt output, it does not clear the source of the interrupt which is the FLAG status bit.0WCNT_EN, Prescale and Main Counter enable. Clearing this bit resets the Prescale and Main counter to their default state. This bit has no effect when the SLAVE bit is set. Reset Value:
CNTRL_0: 00h
Table 2b: CNTRL Register Bits
PRE_SCALRDECADE_ENA = 0DECADE_ENA = 101112224438841610532100664100071281000082562000095122000010102420000112048200001240962000013819220000141638420000153276820000Table 3: PRE_SCLAR Decode Values
4.1 MOD Register
16 Bit Data Bus
Bit #AccessDescription15:0RWMOD_VAL, Main Counter modulo value
Sets the rollover value of the Main Counter.Reset Value:
MOD_VAL: 0000h
Table 4: MOD Register Bits
8 Bit Data Bus
Bit #AccessDescription7:0RWMOD_VAL_0, MOD_VAL[7:0] Main Counter modulo value
Sets the rollover value of the Main Counter.Reset Value:
MOD_VAL_0: 00h
Table 4a: MOD_VAL_0 Register Bits
Bit #AccessDescription7:0RWMOD_VAL_1, MOD_VAL[15:8] Main Counter modulo value
Sets the rollover value of the Main Counter.Reset Value:
MOD_VAL_1: 00h
Table 4b: MOD_VAL_1 Register Bits
4.2 CNT Register
16 Bit Data Bus
Bit #AccessDescription15:0RWCOUNT_VAL, Current state of the Main Counter.Reset Value:
CNT: 0001h
Table 5: CNT Register Bits
8 Bit Data Bus
Bit #AccessDescription7:0RWCOUNT_VAL_0, COUNT_VAL[7:0] Current state of the Main Counter.
Note: To minimize the gates there is no register to capture the full value of COUNT_VAL when only a byte is read. This means that the value that the processor sees is only the approximate value of COUNT_VAL because one of the bytes will have changed between the read of the first byte of COUNT_VAL and the second byte of COUNT_VAL.Reset Value:
CNT_0: 01h
Table 5a: CNT_0 Register Bits
Bit #AccessDescription7:0RWCOUNT_VAL_1, COUNT_VAL[15:8] Current state of the Main Counter.Reset Value:
CNT_1: 00h
Table 5b: CNT_1 Register Bits
Clocks
NameSourceRates (MHz)RemarksDescriptionMaxMinResolutionwb_clk_iSystem200--Master clock for all PIT registers. Positive edge active.System clock.Table SEQ Table \* ARABIC 3: List of clocks
The wb_clk_i has no timing constraints based on the RTL implementation although there may be constrains applied for synthesis results to be compatible with the target physical implementation. If the PIT is targeted for an ASIC implementation then [wb_clk_i] should be used as the scan clock, any clock multiplexing required to make [wb_clk_i] the scan clock should be done at the system level external to the PIT module.
IO Ports
PortWidthDirectionDescriptionwb_clk_i1InputWISHBONE Bus Clock Input, Master Clockwb_rst_i1InputWISHBONE Synchronous Resetwb_adr_i3InputWISHBONE Lower address bitswb_dat_i8/16InputWISHBONE Bus Datawb_dat_o8/16OutputWISHBONE Bus Datawb_we_i1InputWISHBONE Write enablewb_stb_i1InputWISHBONE Strobe signal/Core selectwb_cyc_i1InputWISHBONE Valid bus cyclewb_ack_o1OutputWISHBONE Bus cycle acknowledge pit_int_o1OutputPIT Interrupt signalpit_o1OutputPIT output pulsecnt_flag_o1OutputCounter rollover flagcnt_sync_o1OutputSync signal to slave mode PIText_sync_i1InputSync signal from master mode PITTable SEQ Table \* ARABIC 4: List of IO ports
6.1 WISHBONE Interface
The core features a WISHBONE RevB.3 compliant WISHBONE Classic interface that operates in SLAVE mode. All output signals are registered. Each access takes 2 clock cycles.
WISHBONE DATASHEETDescriptionSpecificationGeneral description:8-bit SLAVESupported Cycles:SLAVE, READ/WRITEData port, size:
Data port, granularity:
Data port, maximum operand size:
Data transfer ordering:
Data transfer sequencing:Default: 16, option 8 bit
Default: 16, option to match 8 bit port size
Supported signal list and cross reference to equivalent WISHBONE signals:Signal NameWISHBONE Equiv.wb_clk_iCLK_Iwb_rst_iRST_Iwb_adr_iADR_I()wb_dat_iDAT_I()wb_dat_oDAT_O()wb_we_iWE_Iwb_stb_iSTB_Iwb_cyc_iCYC_Iwb_ack_oACK_O
6.1.1 wb_rst_i
The synchronous reset signal has a minimum pulse width requirement of one [wb_clk_i] clock period. It will take two [wb_clk_i] clock cycles for all registers in the PIT module to initialize. Also see information on pin [arst_i].
6.1.2 wb_adr_i
Connections to the WISHBONE address pin will depend on the size of the WISHBONE data bus that is set by the DWIDTH parameter. If DWIDTH=8 the all address pins should be connected, if DWIDTH=16 then [wb_adr_i(2)] should be tied low.
6.2 PIT signals
6.2.1 pit_o
The PIT output signal. This is a one master clock, [wb_clk_i], wide pulse that is output when the Master Counter rolls over after reaching the value stored in the Modulo Register.
6.2.2 cnt_flag_o
This signal is an optional output that tracks the value in the FLAG register. The positive edge becomes active at the same time as the [pit_o] signal and the negative edge is dependent on the PIT interrupt service routine, or polling loop, to clear the FLAG register. This signal may be occasionally useful when an output signal with a longer pulse width is needed to be resynchronized to a slower clock domain than the PIT master clock.
6.2.3 pit_int_o
This signal is the interrupt output from the PIT. The timing and function of this signal is the same as [cnt_flag_o] with an additional output inhibit provided by the ENA_INT control bit.
6.2.4 cnt_sync_o
A PIT that is to be used in master mode will use this signal to synchronize the start of counting in PIT instances that are operating in slave mode. All slave mode PITs that will synchronize to a common master will connect their [ext_sync_i] inputs to this output. The CNT_EN control register drives this signal.
6.2.5 ext_sync_i
A PIT module operating in slave mode will use this signal to synchronize the start of its counters to the setting of the CNT_EN register in the associated master mode PIT. If the PIT module is never to be used in SLAVE mode then this input signal should be tied low.
6.2.6 arst_i
The signal [arst_i] is an asynchronous reset signal that goes to all flops in the PIT. It is provided for FPGA implementations and test methodologies that require this function for initialization. Using [arst_i] instead of [wb_rst_i] can result in lower cell-usage and higher performance for a FPGAs implementation because the standard FPGA cell already provides a dedicated asynchronous reset path. Using [wb_rst_i] for an ASIC implementation might synthesize to a smaller module because smaller non_reset flops can be used. Use either [arst_i] or [wb_rst_i], tie the other to a negated state. The active level of [arst_i] is determined by the parameter ARST_LVL which defaults to active low.
6.3 PIT Core Parameters
ParameterTypeDefaultDescriptionARST_LVLBit1b0Asynchronous reset levelCOUNT_SIZEInt16Number of bits in Main Counter and moduloDECADE_CNTRBit1b1Prescaler decode, 0 = Binary counter, 1 = Decade counterNO_PRESCALEBit1b0Prescale counter disabled, 0 = Prescale counter enabled, 1 = Prescale counter disabledDWIDTHInt16Data Bus size
6.3.1 ARST_LVL
The asynchronous reset level can be set to either active high (1b1) or active low (1b0).
Allowed values: 1b0, 1b1
6.3.2 COUNT_SIZE
The number of bits in the Main Counter.
Allowed values: 16-1
6.3.3 DECADE_CNTR
The Prescale Counter can be set to count as a binary decoded output or a decade decoded output. Setting this value may offer a more intuitive programmer interface. Clearing this bit will allow the maximum prescale value and may also slightly reduce the amount of combinational logic required to decode the Prescale Counter output.
Allowed values: 1b0, 1b1
6.3.4 NO_PRESCALE
Setting this bit should remove the Prescale Counter from the synthesis results to save size and power if this function is not needed to meet system requirements. Synthesis scripts should be coded to allow for the removal of flops with unconnected outputs. Synthesis logfiles should be reviewed to ensure the Prescale counter and its control registers are removed.
Allowed values: 1b0, 1b1
2.1.5 DWIDTH
The width of the microcontroller data buses connected to PIT module. The PIT module can support either an 8-bit data bus with 8-bit resolution or a 16-bit data bus with 16-bit resolution.
Allowed values: 8, 16
Name
[This section may be added to outline different specifications.]
[This section contains an alphabetical list of helpful document entries with their corresponding page numbers.]
OpenCores TITLE \* MERGEFORMAT Programable Interval (PIT) Module DATE \* MERGEFORMAT 4/13/09
HYPERLINK "http://www.opencores.org/"www.opencores.org Rev 0.1 Preliminary PAGE iii
OpenCores TITLE \* MERGEFORMAT Programable Interval (PIT) Module DATE \* MERGEFORMAT 4/13/09
HYPERLINK "http://www.opencores.org/"www.opencores.org Rev 0.1 Preliminary PAGE v
HYPERLINK "http://www.opencores.org/"www.opencores.org Rev 0.1 Preliminary PAGE 20 of SECTIONPAGES20
CNT_EN
MSTR_ROLL
PRE_OUT
MSTR_CNT
PRE_SCALE
0002
0003
0001
0001
0004
0004
0003
cnt_flag_o
pit_o
ext_sync_i
Main
Counter
Count Register
Modulo Register
Command Register
WISHBONE Interface
Prescale
Counter
cnt_sync_o
0002
0001
0002
0002
0001
CNT_FLAG_O
PIT_O
0002
0001
0002
0001
0002
0001
0002
0001
0002
0001
0002
0001
0002
0001
0001
MSTR_CLK
CNT_EN
MSTR_CNT
MSTR_ROLL
CNT_FLAG_O
PIT_O
0003
0002
0001
0005
0004
0003
0002
0001
0005
0004
0003
0002
0001
0005
0004
0001
0003
0002
MSTR_CLK
pit_int_o
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