////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Programable Interrupt Timer - Prescale Counter
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// Programable Interrupt Timer - Prescale Counter
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//
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//
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// Author: Bob Hayes
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// Author: Bob Hayes
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// rehayes@opencores.org
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// rehayes@opencores.org
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//
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//
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// Downloaded from: http://www.opencores.org/projects/pit.....
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// Downloaded from: http://www.opencores.org/projects/pit.....
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2011, Robert Hayes
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// Copyright (c) 2011, Robert Hayes
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//
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//
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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// * Redistributions of source code must retain the above copyright
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the nor the
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// * Neither the name of the nor the
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// names of its contributors may be used to endorse or promote products
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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// derived from this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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module pit_prescale #(parameter COUNT_SIZE = 15,
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module pit_prescale #(parameter COUNT_SIZE = 15,
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parameter DECADE_CNTR = 1,
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parameter DECADE_CNTR = 1,
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parameter NO_PRESCALE = 0)
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parameter NO_PRESCALE = 0)
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(
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(
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output prescale_out, //
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output prescale_out, //
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output counter_sync, //
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output counter_sync, //
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input async_rst_b, //
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input async_rst_b, //
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input sync_reset, // Syncronous reset signal
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input sync_reset, // Syncronous reset signal
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input bus_clk, // Reference Clock
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input bus_clk, // Reference Clock
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input cnt_sync_o, // Syncronous counter enable
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input cnt_sync_o, // Syncronous counter enable
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input ext_sync_i, // Enable from external PIT
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input ext_sync_i, // Enable from external PIT
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input pit_slave, // PIT Slave Mode
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input pit_slave, // PIT Slave Mode
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input [3:0] divisor // Count Divisor
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input [3:0] divisor // Count Divisor
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);
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);
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// Warning: This counter has no safety net if the divisor changes while the
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// Warning: This counter has no safety net if the divisor changes while the
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// counter is active. There may need to be an addtional latch
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// counter is active. There may need to be an addtional latch
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// register for"divisor" that captures on the falling edge of
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// register for"divisor" that captures on the falling edge of
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// "cnt_sync_o" or when "cnt_n" rolls over to eliminate this problem.
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// "cnt_sync_o" or when "cnt_n" rolls over to eliminate this problem.
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logic [COUNT_SIZE-1:0] cnt_n; // Div N counter
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logic [COUNT_SIZE-1:0] cnt_n; // Div N counter
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logic [COUNT_SIZE-1:0] end_count; // Psudo register for decoding
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logic [COUNT_SIZE-1:0] end_count; // Psudo register for decoding
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logic div_1; //
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logic div_1; //
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logic rollover; //
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logic rollover; //
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// This was going to be a "generate" block but iverilog does't support that
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// This was going to be a "generate" block but iverilog does't support that
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// command so we'll just have to trust the compiler to simplify the logic based
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// command so we'll just have to trust the compiler to simplify the logic based
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// on the setting of the constant "DECADE_CNTR"
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// on the setting of the constant "DECADE_CNTR"
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always @*
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always_comb
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if ( DECADE_CNTR )
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if ( DECADE_CNTR )
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case (divisor)
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case (divisor)
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0: end_count = 1;
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0: end_count = 1;
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1: end_count = 2;
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1: end_count = 2;
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2: end_count = 4;
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2: end_count = 4;
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3: end_count = 8;
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3: end_count = 8;
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4: end_count = 10;
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4: end_count = 10;
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5: end_count = 100;
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5: end_count = 100;
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6: end_count = 1_000;
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6: end_count = 1_000;
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7: end_count = 10_000;
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7: end_count = 10_000;
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8: end_count = 20_000;
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8: end_count = 20_000;
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default: end_count = 20_000;
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default: end_count = 20_000;
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endcase
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endcase
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else
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else
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case (divisor)
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unique case (divisor)
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0: end_count = 1;
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0: end_count = 1;
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1: end_count = 2;
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1: end_count = 2;
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2: end_count = 4;
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2: end_count = 4;
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3: end_count = 8;
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3: end_count = 8;
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4: end_count = 16;
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4: end_count = 16;
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5: end_count = 32;
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5: end_count = 32;
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6: end_count = 64;
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6: end_count = 64;
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7: end_count = 128;
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7: end_count = 128;
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8: end_count = 256;
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8: end_count = 256;
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9: end_count = 512;
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9: end_count = 512;
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10: end_count = 1024;
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10: end_count = 1024;
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11: end_count = 2048;
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11: end_count = 2048;
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12: end_count = 4096;
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12: end_count = 4096;
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13: end_count = 8192;
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13: end_count = 8192;
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14: end_count = 16384;
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14: end_count = 16384;
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15: end_count = 32768;
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15: end_count = 32768;
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endcase
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endcase
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assign counter_sync = pit_slave ? ext_sync_i : cnt_sync_o;
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assign counter_sync = pit_slave ? ext_sync_i : cnt_sync_o;
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assign div_1 = (end_count == 1);
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assign div_1 = (end_count == 1);
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assign rollover = NO_PRESCALE || (cnt_n == end_count);
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assign rollover = NO_PRESCALE || (cnt_n == end_count);
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assign prescale_out = (pit_slave && div_1 && ext_sync_i) || rollover;
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assign prescale_out = (pit_slave && div_1 && ext_sync_i) || rollover;
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// Div N Counter
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// Div N Counter
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// If the "NO_PRESCALE" parameter is set the compiler should hopefully strip
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// If the "NO_PRESCALE" parameter is set the compiler should hopefully strip
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// these counter bits when the module is compiled because the only place the
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// these counter bits when the module is compiled because the only place the
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// register outputs go to drive a signal "rollover" that is already a constant.
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// register outputs go to drive a signal "rollover" that is already a constant.
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always @(posedge bus_clk or negedge async_rst_b)
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always_ff @(posedge bus_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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cnt_n <= 1;
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cnt_n <= 1;
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else if ( !counter_sync || rollover)
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else if ( !counter_sync || rollover)
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cnt_n <= 1;
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cnt_n <= 1;
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else
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else
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cnt_n <= cnt_n + 1;
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cnt_n <= cnt_n + 1;
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endmodule // pit_prescale
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endmodule // pit_prescale
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