---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Plamsa Interface (clock divider and interface to FPGA board)
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-- TITLE: Plamsa Interface (clock divider and interface to FPGA board)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 6/6/02
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-- DATE CREATED: 6/6/02
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-- FILENAME: plasma_if.vhd
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-- FILENAME: plasma_if.vhd
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-- PROJECT: Plasma CPU core
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- This entity divides the clock by two and interfaces to the
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-- This entity divides the clock by two and interfaces to the
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-- Altera EP20K200EFC484-2X FPGA board.
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-- Altera EP20K200EFC484-2X FPGA board.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity plasma_if is
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entity plasma_if is
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generic(memory_type : string := "ALTERA";
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generic(memory_type : string := "ALTERA";
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log_file : string := "UNUSED");
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log_file : string := "UNUSED");
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port(clk_in : in std_logic;
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port(clk_in : in std_logic;
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reset_n : in std_logic;
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reset_n : in std_logic;
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uart_read : in std_logic;
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uart_read : in std_logic;
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uart_write : out std_logic;
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uart_write : out std_logic;
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address : out std_logic_vector(31 downto 0);
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address : out std_logic_vector(31 downto 0);
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data : out std_logic_vector(31 downto 0);
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data : out std_logic_vector(31 downto 0);
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we_n : out std_logic;
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we_n : out std_logic;
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oe_n : out std_logic;
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oe_n : out std_logic;
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be_n : out std_logic_vector(3 downto 0);
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be_n : out std_logic_vector(3 downto 0);
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sram0_cs_n : out std_logic;
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sram0_cs_n : out std_logic;
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sram1_cs_n : out std_logic);
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sram1_cs_n : out std_logic);
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end; --entity plasma_if
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end; --entity plasma_if
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architecture logic of plasma_if is
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architecture logic of plasma_if is
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signal clk_reg : std_logic;
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signal clk_reg : std_logic;
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signal reset_in : std_logic;
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signal reset_in : std_logic;
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signal intr_in : std_logic;
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signal intr_in : std_logic;
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signal mem_address : std_logic_vector(31 downto 0);
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signal mem_address : std_logic_vector(31 downto 0);
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signal mem_pause_in : std_logic;
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signal mem_pause_in : std_logic;
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signal write_enable : std_logic;
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signal write_enable : std_logic;
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signal mem_byte_sel : std_logic_vector(3 downto 0);
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signal mem_byte_sel : std_logic_vector(3 downto 0);
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begin --architecture
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begin --architecture
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reset_in <= not reset_n;
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reset_in <= not reset_n;
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intr_in <= '0';
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intr_in <= '0';
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mem_pause_in <= '0';
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mem_pause_in <= '0';
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address <= mem_address;
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address <= mem_address;
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we_n <= not write_enable;
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we_n <= not write_enable;
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oe_n <= write_enable;
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oe_n <= write_enable;
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be_n <= not mem_byte_sel;
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be_n <= not mem_byte_sel;
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sram0_cs_n <= not mem_address(16);
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sram0_cs_n <= not mem_address(16);
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sram1_cs_n <= not mem_address(16);
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sram1_cs_n <= not mem_address(16);
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--convert 33MHz clock to 16.5MHz clock
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--convert 33MHz clock to 16.5MHz clock
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clk_div: process(clk_in, reset_in, clk_reg)
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clk_div: process(clk_in, reset_in, clk_reg)
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begin
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begin
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if reset_in = '1' then
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if reset_in = '1' then
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clk_reg <= '0';
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clk_reg <= '0';
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elsif rising_edge(clk_in) then
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elsif rising_edge(clk_in) then
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clk_reg <= not clk_reg;
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clk_reg <= not clk_reg;
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end if;
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end if;
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end process; --clk_div
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end process; --clk_div
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u1_plama: plasma
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u1_plama: plasma
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generic map (memory_type => memory_type,
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generic map (memory_type => memory_type,
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log_file => log_file)
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log_file => log_file)
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PORT MAP (
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PORT MAP (
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clk_in => clk_reg,
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clk_in => clk_reg,
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reset_in => reset_in,
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reset_in => reset_in,
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intr_in => intr_in,
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intr_in => intr_in,
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uart_read => uart_read,
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uart_read => uart_read,
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uart_write => uart_write,
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uart_write => uart_write,
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mem_address_out => mem_address,
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mem_address_out => mem_address,
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mem_data => data,
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mem_data => data,
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mem_byte_sel_out => mem_byte_sel,
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mem_byte_sel_out => mem_byte_sel,
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mem_write_out => write_enable,
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mem_write_out => write_enable,
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mem_pause_in => mem_pause_in);
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mem_pause_in => mem_pause_in);
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end; --architecture logic
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end; --architecture logic
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