---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Random Access Memory
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-- TITLE: Random Access Memory
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 4/21/01
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-- DATE CREATED: 4/21/01
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-- FILENAME: ram.vhd
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-- FILENAME: ram.vhd
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-- PROJECT: M-lite CPU core
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Implements the RAM, reads the executable from "code.txt",
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-- Implements the RAM, reads the executable from "code.txt",
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-- and saves a character to "output.txt" upon a write to 0xffff.
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-- and saves a character to "output.txt" upon a write to 0xffff.
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-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
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-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity ram is
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entity ram is
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generic(load_file_name : string);
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generic(load_file_name : string);
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port(clk : in std_logic;
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port(clk : in std_logic;
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mem_byte_sel : in std_logic_vector(3 downto 0);
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mem_byte_sel : in std_logic_vector(3 downto 0);
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mem_write : in std_logic;
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mem_write : in std_logic;
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mem_address : in std_logic_vector;
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mem_address : in std_logic_vector;
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mem_data_w : in std_logic_vector(31 downto 0);
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mem_data_w : in std_logic_vector(31 downto 0);
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mem_data_r : out std_logic_vector(31 downto 0));
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mem_data_r : out std_logic_vector(31 downto 0));
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end; --entity ram
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end; --entity ram
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architecture logic of ram is
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architecture logic of ram is
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begin
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begin
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ram_proc: process
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ram_proc: process
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variable data : std_logic_vector(31 downto 0);
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variable data : std_logic_vector(31 downto 0);
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variable d : std_logic_vector(31 downto 0);
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variable d : std_logic_vector(31 downto 0);
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variable datab : std_logic_vector(31 downto 0);
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variable datab : std_logic_vector(31 downto 0);
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variable value : natural;
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variable value : natural;
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subtype word is std_logic_vector(mem_data_w'length-1 downto 0);
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subtype word is std_logic_vector(mem_data_w'length-1 downto 0);
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type storage_array is
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type storage_array is
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array(natural range 0 to 2**mem_address'length-1) of word;
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array(natural range 0 to 2**mem_address'length-1) of word;
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variable storage : storage_array;
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variable storage : storage_array;
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variable index : natural;
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variable index : natural;
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file load_file : text is in load_file_name;
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file load_file : text is in load_file_name;
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file store_file : text is out "output.txt";
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file store_file : text is out "output.txt";
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variable hex_file_line : line;
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variable hex_file_line : line;
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variable c : character;
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variable c : character;
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variable line_length : natural := 0;
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variable line_length : natural := 0;
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begin
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begin
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--load in the ram executable image
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--load in the ram executable image
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index := 0;
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index := 0;
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while not endfile(load_file) loop
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while not endfile(load_file) loop
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readline(load_file, hex_file_line);
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readline(load_file, hex_file_line);
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hread(hex_file_line, data);
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hread(hex_file_line, data);
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storage(index) := data;
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storage(index) := data;
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index := index + 1;
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index := index + 1;
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end loop;
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end loop;
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--assert false report "done reading code" severity note;
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--assert false report "done reading code" severity note;
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wait on clk; --wait for line noise to go away
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wait on clk; --wait for line noise to go away
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wait on mem_address;
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wait on mem_address;
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loop
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loop
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wait on clk, mem_address, mem_write;
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wait on clk, mem_address, mem_write;
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--support putchar() when writing to address 0xffff
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--support putchar() when writing to address 0xffff
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if rising_edge(clk) then
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if rising_edge(clk) then
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if mem_byte_sel(0) = '1' and mem_address = ONES(15 downto 0) then
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if mem_byte_sel(0) = '1' and mem_address = ONES(15 downto 0) then
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index := conv_integer(mem_data_w(6 downto 0));
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index := conv_integer(mem_data_w(6 downto 0));
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if index /= 10 then
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if index /= 10 then
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c := character'val(index);
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c := character'val(index);
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write(hex_file_line, c);
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write(hex_file_line, c);
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line_length := line_length + 1;
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line_length := line_length + 1;
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end if;
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end if;
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--line_length:=100; --DEBUG mode
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--line_length:=100; --DEBUG mode
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if index = 10 or line_length >= 72 then
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if index = 10 or line_length >= 72 then
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writeline(store_file, hex_file_line);
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writeline(store_file, hex_file_line);
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line_length := 0;
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line_length := 0;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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index := conv_integer(mem_address(mem_address'length-1 downto 2));
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index := conv_integer(mem_address(mem_address'length-1 downto 2));
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data := storage(index);
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data := storage(index);
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if mem_write = '0' then
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if mem_write = '0' then
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mem_data_r <= data;
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mem_data_r <= data;
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else
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else
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mem_data_r <= HIGH_Z; --ZERO;
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mem_data_r <= HIGH_Z; --ZERO;
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end if;
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end if;
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if mem_byte_sel(0) = '1' then
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if mem_byte_sel(0) = '1' then
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data(7 downto 0) := mem_data_w(7 downto 0);
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data(7 downto 0) := mem_data_w(7 downto 0);
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end if;
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end if;
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if mem_byte_sel(1) = '1' then
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if mem_byte_sel(1) = '1' then
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data(15 downto 8) := mem_data_w(15 downto 8);
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data(15 downto 8) := mem_data_w(15 downto 8);
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end if;
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end if;
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if mem_byte_sel(2) = '1' then
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if mem_byte_sel(2) = '1' then
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data(23 downto 16) := mem_data_w(23 downto 16);
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data(23 downto 16) := mem_data_w(23 downto 16);
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end if;
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end if;
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if mem_byte_sel(3) = '1' then
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if mem_byte_sel(3) = '1' then
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data(31 downto 24) := mem_data_w(31 downto 24);
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data(31 downto 24) := mem_data_w(31 downto 24);
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end if;
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end if;
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if rising_edge(clk) then
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if rising_edge(clk) then
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if mem_write = '1' then
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if mem_write = '1' then
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storage(index) := data;
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storage(index) := data;
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end if;
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end if;
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end if;
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end if;
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end loop;
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end loop;
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end process;
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end process;
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end; --architecture logic
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end; --architecture logic
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