---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Memory Controller
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-- TITLE: Memory Controller
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 1/31/01
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-- DATE CREATED: 1/31/01
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-- FILENAME: mem_ctrl.vhd
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-- FILENAME: mem_ctrl.vhd
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-- PROJECT: Plasma CPU core
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Memory controller for the Plasma CPU.
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-- Memory controller for the Plasma CPU.
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-- Supports Big or Little Endian mode.
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-- Supports Big or Little Endian mode.
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-- Four cycles for a write unless a(31)='1' then two cycles.
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-- Four cycles for a write unless a(31)='1' then two cycles.
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-- This entity could implement interfaces to:
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-- This entity could implement interfaces to:
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-- Data cache
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-- Data cache
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-- Address cache
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-- Address cache
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-- Memory management unit (MMU)
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-- Memory management unit (MMU)
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-- DRAM controller
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-- DRAM controller
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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|
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entity mem_ctrl is
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entity mem_ctrl is
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generic(ACCURATE_TIMING : boolean := false);
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generic(ACCURATE_TIMING : boolean := false);
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset_in : in std_logic;
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reset_in : in std_logic;
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pause_in : in std_logic;
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pause_in : in std_logic;
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nullify_op : in std_logic;
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nullify_op : in std_logic;
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address_pc : in std_logic_vector(31 downto 0);
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address_pc : in std_logic_vector(31 downto 0);
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opcode_out : out std_logic_vector(31 downto 0);
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opcode_out : out std_logic_vector(31 downto 0);
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|
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address_data : in std_logic_vector(31 downto 0);
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address_data : in std_logic_vector(31 downto 0);
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mem_source : in mem_source_type;
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mem_source : in mem_source_type;
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data_write : in std_logic_vector(31 downto 0);
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data_write : in std_logic_vector(31 downto 0);
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data_read : out std_logic_vector(31 downto 0);
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data_read : out std_logic_vector(31 downto 0);
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pause_out : out std_logic;
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pause_out : out std_logic;
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|
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mem_address : out std_logic_vector(31 downto 0);
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mem_address : out std_logic_vector(31 downto 0);
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mem_data_w : out std_logic_vector(31 downto 0);
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mem_data_w : out std_logic_vector(31 downto 0);
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mem_data_r : in std_logic_vector(31 downto 0);
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mem_data_r : in std_logic_vector(31 downto 0);
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mem_byte_sel : out std_logic_vector(3 downto 0);
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mem_byte_sel : out std_logic_vector(3 downto 0);
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mem_write : out std_logic);
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mem_write : out std_logic);
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end; --entity mem_ctrl
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end; --entity mem_ctrl
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architecture logic of mem_ctrl is
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architecture logic of mem_ctrl is
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--"00" = big_endian; "11" = little_endian
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--"00" = big_endian; "11" = little_endian
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constant little_endian : std_logic_vector(1 downto 0) := "00";
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constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00";
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signal opcode_reg : std_logic_vector(31 downto 0);
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signal opcode_reg : std_logic_vector(31 downto 0);
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signal next_opcode_reg : std_logic_vector(31 downto 0);
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signal next_opcode_reg : std_logic_vector(31 downto 0);
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|
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subtype mem_state_type is std_logic_vector(1 downto 0);
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subtype mem_state_type is std_logic_vector(1 downto 0);
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signal mem_state_reg : mem_state_type;
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signal mem_state_reg : mem_state_type;
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constant STATE_FETCH : mem_state_type := "00";
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constant STATE_FETCH : mem_state_type := "00";
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constant STATE_ADDR : mem_state_type := "01";
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constant STATE_ADDR : mem_state_type := "01";
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constant STATE_WRITE : mem_state_type := "10";
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constant STATE_WRITE : mem_state_type := "10";
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constant STATE_PAUSE : mem_state_type := "11";
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constant STATE_PAUSE : mem_state_type := "11";
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|
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--ACCURATE_TIMING notes:
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--ACCURATE_TIMING notes:
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--The VHDL compiler's timing calculation isn't able to realize that
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--The VHDL compiler's timing calculation isn't able to realize that
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--memory reads take two clock cycles. It notices that reg_bank:reg_dest
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--memory reads take two clock cycles. It notices that reg_bank:reg_dest
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--is dependent on mem_ctrl:mem_data_r which is dependent on
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--is dependent on mem_ctrl:mem_data_r which is dependent on
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--mem_ctrl:mem_address which is dependent on alu:c_alu. However,
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--mem_ctrl:mem_address which is dependent on alu:c_alu. However,
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--this dependency is only true for memory read or write cycles
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--this dependency is only true for memory read or write cycles
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--which are multiple clock cycles. Enabling ACCURATE_TIMING
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--which are multiple clock cycles. Enabling ACCURATE_TIMING
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--creates an additional 32-bit register that does nothing other
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--creates an additional 32-bit register that does nothing other
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--than letting the VHDL compiler accurately predict the maximum
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--than letting the VHDL compiler accurately predict the maximum
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--clock speed.
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--clock speed.
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signal address_reg : std_logic_vector(31 downto 0);
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signal address_reg : std_logic_vector(31 downto 0);
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signal write_reg : std_logic;
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signal write_reg : std_logic;
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signal byte_sel_reg : std_logic_vector(3 downto 0);
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signal byte_sel_reg : std_logic_vector(3 downto 0);
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signal mem_state_next_sig : mem_state_type;
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signal mem_state_next_sig : mem_state_type;
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signal opcode_next_sig : std_logic_vector(31 downto 0);
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signal opcode_next_sig : std_logic_vector(31 downto 0);
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signal write_next_sig : std_logic;
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signal write_next_sig : std_logic;
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signal byte_sel_next_sig : std_logic_vector(3 downto 0);
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signal byte_sel_next_sig : std_logic_vector(3 downto 0);
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|
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begin
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begin
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|
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GEN_REGS: process(clk, reset_in)
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GEN_REGS: process(clk, reset_in)
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begin
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begin
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if reset_in = '1' then
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if reset_in = '1' then
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mem_state_reg <= STATE_FETCH;
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mem_state_reg <= STATE_FETCH;
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opcode_reg <= ZERO;
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opcode_reg <= ZERO;
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next_opcode_reg <= ZERO;
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next_opcode_reg <= ZERO;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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mem_state_reg <= mem_state_next_sig;
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mem_state_reg <= mem_state_next_sig;
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opcode_reg <= opcode_next_sig;
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opcode_reg <= opcode_next_sig;
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if mem_state_reg = STATE_FETCH then
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if mem_state_reg = STATE_FETCH then
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next_opcode_reg <= mem_data_r;
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next_opcode_reg <= mem_data_r;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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GEN_REGS2: process(clk, address_data, write_next_sig, byte_sel_next_sig)
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GEN_REGS2: process(clk, address_data, write_next_sig, byte_sel_next_sig)
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begin
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begin
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if rising_edge(clk) then
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if reset_in = '1' then
|
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if ACCURATE_TIMING then
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address_reg <= ZERO;
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write_reg <= '0';
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byte_sel_reg <= "0000";
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end if;
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elsif rising_edge(clk) then
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if ACCURATE_TIMING then
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if ACCURATE_TIMING then
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address_reg <= address_data;
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address_reg <= address_data;
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write_reg <= write_next_sig;
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write_reg <= write_next_sig;
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byte_sel_reg <= byte_sel_next_sig;
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byte_sel_reg <= byte_sel_next_sig;
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end if;
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end if;
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end if;
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end if;
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if not ACCURATE_TIMING then
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if not ACCURATE_TIMING then
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address_reg <= address_data;
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address_reg <= address_data;
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write_reg <= write_next_sig;
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write_reg <= write_next_sig;
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byte_sel_reg <= byte_sel_next_sig;
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byte_sel_reg <= byte_sel_next_sig;
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end if;
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end if;
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end process;
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end process;
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mem_proc: process(clk, reset_in, pause_in, nullify_op,
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mem_proc: process(clk, reset_in, pause_in, nullify_op,
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address_pc, address_data, mem_source, data_write,
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address_pc, address_data, mem_source, data_write,
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mem_data_r,
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mem_data_r,
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opcode_reg, next_opcode_reg, mem_state_reg,
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opcode_reg, next_opcode_reg, mem_state_reg,
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address_reg, write_reg, byte_sel_reg)
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address_reg, write_reg, byte_sel_reg)
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variable data : std_logic_vector(31 downto 0);
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variable data : std_logic_vector(31 downto 0);
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variable opcode_next : std_logic_vector(31 downto 0);
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variable opcode_next : std_logic_vector(31 downto 0);
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variable byte_sel_next : std_logic_vector(3 downto 0);
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variable byte_sel_next : std_logic_vector(3 downto 0);
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variable byte_sel : std_logic_vector(3 downto 0);
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variable byte_sel : std_logic_vector(3 downto 0);
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variable write_next : std_logic;
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variable write_next : std_logic;
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variable write_line : std_logic;
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variable write_line : std_logic;
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variable mem_state_next : mem_state_type;
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variable mem_state_next : mem_state_type;
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variable pause : std_logic;
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variable pause : std_logic;
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variable address : std_logic_vector(31 downto 0);
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variable address : std_logic_vector(31 downto 0);
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variable bits : std_logic_vector(1 downto 0);
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variable bits : std_logic_vector(1 downto 0);
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variable mem_data_w_v : std_logic_vector(31 downto 0);
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variable mem_data_w_v : std_logic_vector(31 downto 0);
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begin
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begin
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byte_sel_next := "0000";
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byte_sel_next := "0000";
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write_next := '0';
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write_next := '0';
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pause := '0';
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pause := '0';
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mem_state_next := mem_state_reg;
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mem_state_next := mem_state_reg;
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|
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data := ZERO;
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data := ZERO;
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mem_data_w_v := ZERO;
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mem_data_w_v := ZERO;
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|
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case mem_source is
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case mem_source is
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when mem_read32 =>
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when MEM_READ32 =>
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data := mem_data_r;
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data := mem_data_r;
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when mem_read16 | mem_read16s =>
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if address_reg(1) = little_endian(1) then
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when MEM_READ16 | MEM_READ16S =>
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if address_reg(1) = ENDIAN_MODE(1) then
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data(15 downto 0) := mem_data_r(31 downto 16);
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data(15 downto 0) := mem_data_r(31 downto 16);
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else
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else
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data(15 downto 0) := mem_data_r(15 downto 0);
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data(15 downto 0) := mem_data_r(15 downto 0);
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end if;
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end if;
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if mem_source = mem_read16 or data(15) = '0' then
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if mem_source = mem_read16 or data(15) = '0' then
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data(31 downto 16) := ZERO(31 downto 16);
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data(31 downto 16) := ZERO(31 downto 16);
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else
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else
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data(31 downto 16) := ONES(31 downto 16);
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data(31 downto 16) := ONES(31 downto 16);
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end if;
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end if;
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when mem_read8 | mem_read8s =>
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bits := address_reg(1 downto 0) xor little_endian;
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when MEM_READ8 | MEM_READ8s =>
|
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bits := address_reg(1 downto 0) xor ENDIAN_MODE;
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case bits is
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case bits is
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when "00" => data(7 downto 0) := mem_data_r(31 downto 24);
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when "00" => data(7 downto 0) := mem_data_r(31 downto 24);
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when "01" => data(7 downto 0) := mem_data_r(23 downto 16);
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when "01" => data(7 downto 0) := mem_data_r(23 downto 16);
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when "10" => data(7 downto 0) := mem_data_r(15 downto 8);
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when "10" => data(7 downto 0) := mem_data_r(15 downto 8);
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when others => data(7 downto 0) := mem_data_r(7 downto 0);
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when others => data(7 downto 0) := mem_data_r(7 downto 0);
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end case;
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end case;
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if mem_source = mem_read8 or data(7) = '0' then
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if mem_source = MEM_READ8 or data(7) = '0' then
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data(31 downto 8) := ZERO(31 downto 8);
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data(31 downto 8) := ZERO(31 downto 8);
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else
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else
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data(31 downto 8) := ONES(31 downto 8);
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data(31 downto 8) := ONES(31 downto 8);
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end if;
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end if;
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when mem_write32 =>
|
|
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when MEM_WRITE32 =>
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write_next := '1';
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write_next := '1';
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mem_data_w_v := data_write;
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mem_data_w_v := data_write;
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byte_sel_next := "1111";
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byte_sel_next := "1111";
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when mem_write16 =>
|
|
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when MEM_WRITE16 =>
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write_next := '1';
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write_next := '1';
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mem_data_w_v := data_write(15 downto 0) & data_write(15 downto 0);
|
mem_data_w_v := data_write(15 downto 0) & data_write(15 downto 0);
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if address_data(1) = little_endian(1) then
|
if address_data(1) = ENDIAN_MODE(1) then
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byte_sel_next := "1100";
|
byte_sel_next := "1100";
|
else
|
else
|
byte_sel_next := "0011";
|
byte_sel_next := "0011";
|
end if;
|
end if;
|
when mem_write8 =>
|
|
|
when MEM_WRITE8 =>
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write_next := '1';
|
write_next := '1';
|
mem_data_w_v := data_write(7 downto 0) & data_write(7 downto 0) &
|
mem_data_w_v := data_write(7 downto 0) & data_write(7 downto 0) &
|
data_write(7 downto 0) & data_write(7 downto 0);
|
data_write(7 downto 0) & data_write(7 downto 0);
|
bits := address_data(1 downto 0) xor little_endian;
|
bits := address_data(1 downto 0) xor ENDIAN_MODE;
|
case bits is
|
case bits is
|
when "00" =>
|
when "00" =>
|
byte_sel_next := "1000";
|
byte_sel_next := "1000";
|
when "01" =>
|
when "01" =>
|
byte_sel_next := "0100";
|
byte_sel_next := "0100";
|
when "10" =>
|
when "10" =>
|
byte_sel_next := "0010";
|
byte_sel_next := "0010";
|
when others =>
|
when others =>
|
byte_sel_next := "0001";
|
byte_sel_next := "0001";
|
end case;
|
end case;
|
|
|
when others =>
|
when others =>
|
end case;
|
end case;
|
|
|
byte_sel_next_sig <= byte_sel_next;
|
byte_sel_next_sig <= byte_sel_next;
|
write_next_sig <= write_next;
|
write_next_sig <= write_next;
|
|
|
opcode_next := opcode_reg;
|
opcode_next := opcode_reg;
|
case mem_state_reg is --State Machine
|
case mem_state_reg is --State Machine
|
when STATE_FETCH =>
|
when STATE_FETCH =>
|
address := address_pc;
|
address := address_pc;
|
write_line := '0';
|
write_line := '0';
|
byte_sel := "0000";
|
byte_sel := "0000";
|
if mem_source = mem_fetch then --opcode fetch
|
if mem_source = mem_fetch then --opcode fetch
|
mem_state_next := STATE_FETCH;
|
mem_state_next := STATE_FETCH;
|
if pause_in = '0' then
|
if pause_in = '0' then
|
opcode_next := mem_data_r;
|
opcode_next := mem_data_r;
|
end if;
|
end if;
|
else --memory read or write
|
else --memory read or write
|
pause := '1';
|
pause := '1';
|
if pause_in = '0' then
|
if pause_in = '0' then
|
mem_state_next := STATE_ADDR;
|
mem_state_next := STATE_ADDR;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when STATE_ADDR => --address lines pre-hold
|
when STATE_ADDR => --address lines pre-hold
|
address := address_reg;
|
address := address_reg;
|
write_line := write_reg;
|
write_line := write_reg;
|
if write_reg = '1' and address_reg(31) = '1' then
|
if write_reg = '1' and address_reg(31) = '1' then
|
pause := '1';
|
pause := '1';
|
byte_sel := "0000";
|
byte_sel := "0000";
|
if pause_in = '0' then
|
if pause_in = '0' then
|
mem_state_next := STATE_WRITE; --4 cycle access
|
mem_state_next := STATE_WRITE; --4 cycle access
|
end if;
|
end if;
|
else
|
else
|
byte_sel := byte_sel_reg;
|
byte_sel := byte_sel_reg;
|
if pause_in = '0' then
|
if pause_in = '0' then
|
opcode_next := next_opcode_reg;
|
opcode_next := next_opcode_reg;
|
mem_state_next := STATE_FETCH; --2 cycle access
|
mem_state_next := STATE_FETCH; --2 cycle access
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when STATE_WRITE =>
|
when STATE_WRITE =>
|
pause := '1';
|
pause := '1';
|
address := address_reg;
|
address := address_reg;
|
write_line := write_reg;
|
write_line := write_reg;
|
byte_sel := byte_sel_reg;
|
byte_sel := byte_sel_reg;
|
if pause_in = '0' then
|
if pause_in = '0' then
|
mem_state_next := STATE_PAUSE;
|
mem_state_next := STATE_PAUSE;
|
end if;
|
end if;
|
|
|
when OTHERS => --STATE_PAUSE address lines post-hold
|
when OTHERS => --STATE_PAUSE address lines post-hold
|
address := address_reg;
|
address := address_reg;
|
write_line := write_reg;
|
write_line := write_reg;
|
byte_sel := "0000";
|
byte_sel := "0000";
|
if pause_in = '0' then
|
if pause_in = '0' then
|
opcode_next := next_opcode_reg;
|
opcode_next := next_opcode_reg;
|
mem_state_next := STATE_FETCH;
|
mem_state_next := STATE_FETCH;
|
end if;
|
end if;
|
end case;
|
end case;
|
|
|
if nullify_op = '1' and pause_in = '0' then
|
if nullify_op = '1' and pause_in = '0' then
|
opcode_next := ZERO; --NOP after beql
|
opcode_next := ZERO; --NOP after beql
|
end if;
|
end if;
|
|
|
mem_state_next_sig <= mem_state_next;
|
mem_state_next_sig <= mem_state_next;
|
opcode_next_sig <= opcode_next;
|
opcode_next_sig <= opcode_next;
|
|
|
if reset_in = '1' then
|
if reset_in = '1' then
|
write_line := '0';
|
write_line := '0';
|
end if;
|
end if;
|
|
|
opcode_out <= opcode_reg;
|
opcode_out <= opcode_reg;
|
data_read <= data;
|
data_read <= data;
|
pause_out <= pause;
|
pause_out <= pause;
|
mem_byte_sel <= byte_sel;
|
mem_byte_sel <= byte_sel;
|
mem_address <= address;
|
mem_address <= address;
|
mem_write <= write_line;
|
mem_write <= write_line;
|
|
|
if write_line = '1' then
|
if write_line = '1' then
|
mem_data_w <= mem_data_w_v;
|
mem_data_w <= mem_data_w_v;
|
else
|
else
|
mem_data_w <= HIGH_Z; --ZERO;
|
mem_data_w <= HIGH_Z; --ZERO;
|
end if;
|
end if;
|
|
|
end process; --data_proc
|
end process; --data_proc
|
|
|
end; --architecture logic
|
end; --architecture logic
|
|
|
|
|
