---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Multiplication and Division Unit
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-- TITLE: Multiplication and Division Unit
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-- AUTHORS: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHORS: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 1/31/01
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-- DATE CREATED: 1/31/01
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-- FILENAME: mult.vhd
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-- FILENAME: mult.vhd
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-- PROJECT: Plasma CPU core
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Implements the multiplication and division unit in 32 clocks.
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-- Implements the multiplication and division unit in 32 clocks.
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--
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--
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-- To reduce space, compile your code using the flag "-mno-mul" which
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-- To reduce space, compile your code using the flag "-mno-mul" which
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-- will use software base routines in math.c if USE_SW_MULT is defined.
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-- will use software base routines in math.c if USE_SW_MULT is defined.
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-- Then remove references to the entity mult in mlite_cpu.vhd.
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-- Then remove references to the entity mult in mlite_cpu.vhd.
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--
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--
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-- MULTIPLICATION
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-- MULTIPLICATION
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-- long64 answer = 0;
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-- long64 answer = 0;
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-- for(i = 0; i < 32; ++i)
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-- for(i = 0; i < 32; ++i)
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-- {
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-- {
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-- answer = (answer >> 1) + (((b&1)?a:0) << 31);
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-- answer = (answer >> 1) + (((b&1)?a:0) << 31);
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-- b = b >> 1;
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-- b = b >> 1;
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-- }
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-- }
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--
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--
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-- DIVISION
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-- DIVISION
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-- long upper=a, lower=0;
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-- long upper=a, lower=0;
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-- a = b << 31;
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-- a = b << 31;
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-- for(i = 0; i < 32; ++i)
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-- for(i = 0; i < 32; ++i)
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-- {
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-- {
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-- lower = lower << 1;
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-- lower = lower << 1;
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-- if(upper >= a && a && b < 2)
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-- if(upper >= a && a && b < 2)
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-- {
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-- {
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-- upper = upper - a;
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-- upper = upper - a;
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-- lower |= 1;
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-- lower |= 1;
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-- }
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-- }
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-- a = ((b&2) << 30) | (a >> 1);
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-- a = ((b&2) << 30) | (a >> 1);
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-- b = b >> 1;
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-- b = b >> 1;
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-- }
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-- }
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity mult is
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entity mult is
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generic(mult_type : string := "DEFAULT");
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generic(mult_type : string := "DEFAULT");
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset_in : in std_logic;
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reset_in : in std_logic;
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a, b : in std_logic_vector(31 downto 0);
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a, b : in std_logic_vector(31 downto 0);
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mult_func : in mult_function_type;
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mult_func : in mult_function_type;
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c_mult : out std_logic_vector(31 downto 0);
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c_mult : out std_logic_vector(31 downto 0);
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pause_out : out std_logic);
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pause_out : out std_logic);
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end; --entity mult
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end; --entity mult
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architecture logic of mult is
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architecture logic of mult is
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constant MODE_MULT : std_logic := '1';
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constant MODE_MULT : std_logic := '1';
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constant MODE_DIV : std_logic := '0';
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constant MODE_DIV : std_logic := '0';
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signal mode_reg : std_logic;
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signal mode_reg : std_logic;
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signal negate_reg : std_logic;
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signal negate_reg : std_logic;
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signal sign_reg : std_logic;
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signal sign_reg : std_logic;
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signal sign2_reg : std_logic;
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signal sign2_reg : std_logic;
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signal count_reg : std_logic_vector(5 downto 0);
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signal count_reg : std_logic_vector(5 downto 0);
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signal aa_reg : std_logic_vector(31 downto 0);
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signal aa_reg : std_logic_vector(31 downto 0);
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signal bb_reg : std_logic_vector(31 downto 0);
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signal bb_reg : std_logic_vector(31 downto 0);
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signal upper_reg : std_logic_vector(31 downto 0);
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signal upper_reg : std_logic_vector(31 downto 0);
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signal lower_reg : std_logic_vector(31 downto 0);
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signal lower_reg : std_logic_vector(31 downto 0);
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signal a_neg : std_logic_vector(31 downto 0);
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signal a_neg : std_logic_vector(31 downto 0);
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signal b_neg : std_logic_vector(31 downto 0);
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signal b_neg : std_logic_vector(31 downto 0);
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signal sum : std_logic_vector(32 downto 0);
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signal sum : std_logic_vector(32 downto 0);
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begin
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begin
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-- Result
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-- Result
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c_mult <= lower_reg when mult_func = MULT_READ_LO and negate_reg = '0' else
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c_mult <= lower_reg when mult_func = MULT_READ_LO and negate_reg = '0' else
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bv_negate(lower_reg) when mult_func = MULT_READ_LO
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bv_negate(lower_reg) when mult_func = MULT_READ_LO
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and negate_reg = '1' else
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and negate_reg = '1' else
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upper_reg when mult_func = MULT_READ_HI else
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upper_reg when mult_func = MULT_READ_HI else
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ZERO;
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ZERO;
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pause_out <= '1' when (count_reg /= "000000") and
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pause_out <= '1' when (count_reg /= "000000") and
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(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) else '0';
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(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) else '0';
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-- ABS and remainder signals
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-- ABS and remainder signals
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a_neg <= bv_negate(a);
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a_neg <= bv_negate(a);
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b_neg <= bv_negate(b);
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b_neg <= bv_negate(b);
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sum <= bv_adder(upper_reg, aa_reg, mode_reg);
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sum <= bv_adder(upper_reg, aa_reg, mode_reg);
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--multiplication/division unit
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--multiplication/division unit
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mult_proc: process(clk, reset_in, a, b, mult_func,
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mult_proc: process(clk, reset_in, a, b, mult_func,
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a_neg, b_neg, sum, sign_reg, mode_reg, negate_reg,
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a_neg, b_neg, sum, sign_reg, mode_reg, negate_reg,
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count_reg, aa_reg, bb_reg, upper_reg, lower_reg)
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count_reg, aa_reg, bb_reg, upper_reg, lower_reg)
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variable count : std_logic_vector(2 downto 0);
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variable count : std_logic_vector(2 downto 0);
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begin
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begin
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count := "001";
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count := "001";
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if reset_in = '1' then
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if reset_in = '1' then
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mode_reg <= '0';
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mode_reg <= '0';
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negate_reg <= '0';
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negate_reg <= '0';
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sign_reg <= '0';
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sign_reg <= '0';
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sign2_reg <= '0';
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sign2_reg <= '0';
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count_reg <= "000000";
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count_reg <= "000000";
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aa_reg <= ZERO;
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aa_reg <= ZERO;
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bb_reg <= ZERO;
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bb_reg <= ZERO;
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upper_reg <= ZERO;
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upper_reg <= ZERO;
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lower_reg <= ZERO;
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lower_reg <= ZERO;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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case mult_func is
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case mult_func is
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when MULT_WRITE_LO =>
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when MULT_WRITE_LO =>
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lower_reg <= a;
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lower_reg <= a;
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negate_reg <= '0';
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negate_reg <= '0';
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when MULT_WRITE_HI =>
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when MULT_WRITE_HI =>
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upper_reg <= a;
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upper_reg <= a;
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negate_reg <= '0';
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negate_reg <= '0';
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when MULT_MULT =>
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when MULT_MULT =>
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mode_reg <= MODE_MULT;
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mode_reg <= MODE_MULT;
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aa_reg <= a;
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aa_reg <= a;
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bb_reg <= b;
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bb_reg <= b;
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upper_reg <= ZERO;
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upper_reg <= ZERO;
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count_reg <= "100000";
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count_reg <= "100000";
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negate_reg <= '0';
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negate_reg <= '0';
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sign_reg <= '0';
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sign_reg <= '0';
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sign2_reg <= '0';
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sign2_reg <= '0';
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when MULT_SIGNED_MULT =>
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when MULT_SIGNED_MULT =>
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mode_reg <= MODE_MULT;
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mode_reg <= MODE_MULT;
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if b(31) = '0' then
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if b(31) = '0' then
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aa_reg <= a;
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aa_reg <= a;
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bb_reg <= b;
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bb_reg <= b;
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sign_reg <= a(31);
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---- Special case of 0x80000000 * negative number
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--elsif a(31) = '1' and (a(30 downto 0) = ZERO(30 downto 0) or
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-- b(30 downto 0) = ZERO(30 downto 0)) then
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-- aa_reg <= a; --convert to unsigned mult
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-- bb_reg <= b;
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-- sign_reg <= '0';
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else
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else
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aa_reg <= a_neg;
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aa_reg <= a_neg;
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bb_reg <= b_neg;
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bb_reg <= b_neg;
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sign_reg <= a_neg(31);
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end if;
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end if;
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sign_reg <= a(31) xor b(31);
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sign2_reg <= '0';
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sign2_reg <= '0';
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upper_reg <= ZERO;
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upper_reg <= ZERO;
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count_reg <= "100000";
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count_reg <= "100000";
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negate_reg <= '0';
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negate_reg <= '0';
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when MULT_DIVIDE =>
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when MULT_DIVIDE =>
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mode_reg <= MODE_DIV;
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mode_reg <= MODE_DIV;
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aa_reg <= b(0) & ZERO(30 downto 0);
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aa_reg <= b(0) & ZERO(30 downto 0);
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bb_reg <= b;
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bb_reg <= b;
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upper_reg <= a;
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upper_reg <= a;
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count_reg <= "100000";
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count_reg <= "100000";
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negate_reg <= '0';
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negate_reg <= '0';
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when MULT_SIGNED_DIVIDE =>
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when MULT_SIGNED_DIVIDE =>
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mode_reg <= MODE_DIV;
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mode_reg <= MODE_DIV;
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if b(31) = '0' then
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if b(31) = '0' then
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aa_reg(31) <= b(0);
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aa_reg(31) <= b(0);
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bb_reg <= b;
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bb_reg <= b;
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else
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else
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aa_reg(31) <= b_neg(0);
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aa_reg(31) <= b_neg(0);
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bb_reg <= b_neg;
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bb_reg <= b_neg;
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end if;
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end if;
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if a(31) = '0' then
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if a(31) = '0' then
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upper_reg <= a;
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upper_reg <= a;
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else
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else
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upper_reg <= a_neg;
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upper_reg <= a_neg;
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end if;
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end if;
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aa_reg(30 downto 0) <= ZERO(30 downto 0);
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aa_reg(30 downto 0) <= ZERO(30 downto 0);
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count_reg <= "100000";
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count_reg <= "100000";
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negate_reg <= a(31) xor b(31);
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negate_reg <= a(31) xor b(31);
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when others =>
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when others =>
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if count_reg /= "000000" then
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if count_reg /= "000000" then
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if mode_reg = MODE_MULT then
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if mode_reg = MODE_MULT then
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-- Multiplication
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-- Multiplication
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if bb_reg(0) = '1' then
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if bb_reg(0) = '1' then
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upper_reg <= (sign_reg xor sum(32)) & sum(31 downto 1);
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upper_reg <= (sign_reg xor sum(32)) & sum(31 downto 1);
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lower_reg <= sum(0) & lower_reg(31 downto 1);
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lower_reg <= sum(0) & lower_reg(31 downto 1);
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sign2_reg <= sign2_reg or sign_reg;
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sign2_reg <= sign2_reg or sign_reg;
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sign_reg <= '0';
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sign_reg <= '0';
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bb_reg <= '0' & bb_reg(31 downto 1);
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bb_reg <= '0' & bb_reg(31 downto 1);
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-- The following six lines are optional for speedup
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-- The following six lines are optional for speedup
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--elsif bb_reg(3 downto 0) = "0000" and sign2_reg = '0' and
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--elsif bb_reg(3 downto 0) = "0000" and sign2_reg = '0' and
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-- count_reg(5 downto 2) /= "0000" then
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-- count_reg(5 downto 2) /= "0000" then
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-- upper_reg <= "0000" & upper_reg(31 downto 4);
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-- upper_reg <= "0000" & upper_reg(31 downto 4);
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-- lower_reg <= upper_reg(3 downto 0) & lower_reg(31 downto 4);
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-- lower_reg <= upper_reg(3 downto 0) & lower_reg(31 downto 4);
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-- count := "100";
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-- count := "100";
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-- bb_reg <= "0000" & bb_reg(31 downto 4);
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-- bb_reg <= "0000" & bb_reg(31 downto 4);
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else
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else
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upper_reg <= sign2_reg & upper_reg(31 downto 1);
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upper_reg <= sign2_reg & upper_reg(31 downto 1);
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lower_reg <= upper_reg(0) & lower_reg(31 downto 1);
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lower_reg <= upper_reg(0) & lower_reg(31 downto 1);
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bb_reg <= '0' & bb_reg(31 downto 1);
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bb_reg <= '0' & bb_reg(31 downto 1);
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end if;
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end if;
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else
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else
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-- Division
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-- Division
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if sum(32) = '0' and aa_reg /= ZERO and
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if sum(32) = '0' and aa_reg /= ZERO and
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bb_reg(31 downto 1) = ZERO(31 downto 1) then
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bb_reg(31 downto 1) = ZERO(31 downto 1) then
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upper_reg <= sum(31 downto 0);
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upper_reg <= sum(31 downto 0);
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lower_reg(0) <= '1';
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lower_reg(0) <= '1';
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else
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else
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lower_reg(0) <= '0';
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lower_reg(0) <= '0';
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end if;
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end if;
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aa_reg <= bb_reg(1) & aa_reg(31 downto 1);
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aa_reg <= bb_reg(1) & aa_reg(31 downto 1);
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lower_reg(31 downto 1) <= lower_reg(30 downto 0);
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lower_reg(31 downto 1) <= lower_reg(30 downto 0);
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bb_reg <= '0' & bb_reg(31 downto 1);
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bb_reg <= '0' & bb_reg(31 downto 1);
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end if;
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end if;
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count_reg <= count_reg - count;
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count_reg <= count_reg - count;
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end if; --count
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end if; --count
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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end; --architecture logic
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end; --architecture logic
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