----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- PlTbUtils Testbench Template ----
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---- PlTbUtils Testbench Template ----
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---- ----
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---- ----
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---- This file is part of the PlTbUtils project ----
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---- This file is part of the PlTbUtils project ----
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---- http://opencores.org/project,pltbutils ----
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---- http://opencores.org/project,pltbutils ----
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---- ----
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---- ----
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---- Description: ----
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---- Description: ----
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---- PlTbUtils is a collection of functions, procedures and ----
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---- PlTbUtils is a collection of functions, procedures and ----
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---- components for easily creating stimuli and checking response ----
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---- components for easily creating stimuli and checking response ----
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---- in automatic self-checking testbenches. ----
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---- in automatic self-checking testbenches. ----
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---- ----
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---- ----
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---- This file is a template, which can be used as a base when ----
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---- This file is a template, which can be used as a base when ----
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---- testbenches which use PlTbUtils. ----
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---- testbenches which use PlTbUtils. ----
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---- Copy this file to your preferred location and rename the ----
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---- Copy this file to your preferred location and rename the ----
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---- copied file and its contents, by replacing the word ----
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---- copied file and its contents, by replacing the word ----
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---- "template" with a name for your design. ----
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---- "template" with a name for your design. ----
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---- Also remove informative comments enclosed in < ... > . ----
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---- Also remove informative comments enclosed in < ... > . ----
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---- ----
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---- ----
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---- ----
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---- ----
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---- To Do: ----
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---- To Do: ----
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---- - ----
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---- - ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Author(s): ----
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---- - Per Larsson, pela@opencores.org ----
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---- - Per Larsson, pela@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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use std.textio.all;
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use work.txt_util.all;
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use work.txt_util.all;
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use work.pltbutils_func_pkg.all;
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use work.pltbutils_func_pkg.all;
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use work.pltbutils_comp_pkg.all;
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use work.pltbutils_comp_pkg.all;
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-- < Template info: add more libraries here, if needed >
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-- < Template info: add more libraries here, if needed >
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entity tb_template is
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entity tb_template is
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generic (
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generic (
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-- < Template info: add generics here if needed, or remove the generic block >
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-- < Template info: add generics here if needed, or remove the generic block >
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);
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);
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end entity tb_template;
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end entity tb_template;
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architecture bhv of tb_template is
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architecture bhv of tb_template is
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-- Simulation status- and control signals
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-- Simulation status- and control signals
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signal test_num : integer;
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signal test_num : integer;
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-- VHDL-1993:
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-- VHDL-1993:
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--signal test_name : string(pltbutils_test_name'range);
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--signal test_name : string(pltbutils_test_name'range);
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--signal info : string(pltbutils_info'range);
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--signal info : string(pltbutils_info'range);
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-- VHDL-2002:
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-- VHDL-2002:
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signal test_name : string(pltbutils_sc.test_name'range);
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signal test_name : string(pltbutils_sc.test_name'range);
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signal info : string(pltbutils_sc.info'range);
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signal info : string(pltbutils_sc.info'range);
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signal checks : integer;
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signal checks : integer;
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signal errors : integer;
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signal errors : integer;
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signal stop_sim : std_logic;
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signal stop_sim : std_logic;
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-- DUT stimuli and response signals
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-- DUT stimuli and response signals
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signal clk : std_logic;
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signal clk : std_logic;
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signal rst : std_logic;
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signal rst : std_logic;
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-- < Template info: add more DUT stimuli and response signals here. >
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-- < Template info: add more DUT stimuli and response signals here. >
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begin
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begin
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-- Simulation status and control for viewing in waveform window
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-- Simulation status and control for viewing in waveform window
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-- VHDL-1993:
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-- VHDL-1993:
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--test_num <= pltbutils_test_num;
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--test_num <= pltbutils_test_num;
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--test_name <= pltbutils_test_name;
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--test_name <= pltbutils_test_name;
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--checks <= pltbutils_chk_cnt;
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--checks <= pltbutils_chk_cnt;
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--errors <= pltbutils_err_cnt;
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--errors <= pltbutils_err_cnt;
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-- VHDL-2002:
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-- VHDL-2002:
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test_num <= pltbutils_sc.test_num;
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test_num <= pltbutils_sc.test_num;
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test_name <= pltbutils_sc.test_name;
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test_name <= pltbutils_sc.test_name;
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info <= pltbutils_sc.info;
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info <= pltbutils_sc.info;
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checks <= pltbutils_sc.chk_cnt;
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checks <= pltbutils_sc.chk_cnt;
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errors <= pltbutils_sc.err_cnt;
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errors <= pltbutils_sc.err_cnt;
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stop_sim <= pltbutils_sc.stop_sim;
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stop_sim <= pltbutils_sc.stop_sim;
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dut0 : entity work.template
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dut0 : entity work.template
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generic map (
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generic map (
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-- < Template info: add DUT generics here, if any. >
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-- < Template info: add DUT generics here, if any. >
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)
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)
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port map (
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port map (
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clk_i => clk, -- Template example
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clk_i => clk, -- Template example
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rst_i => rst, -- Template example
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rst_i => rst, -- Template example
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-- < Template info: add more DUT ports here. >
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-- < Template info: add more DUT ports here. >
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);
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);
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clkgen0 : pltbutils_clkgen
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clkgen0 : pltbutils_clkgen
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generic map(
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generic map(
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G_PERIOD => G_CLK_PERIOD
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G_PERIOD => G_CLK_PERIOD
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)
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)
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port map(
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port map(
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clk_o => clk,
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clk_o => clk,
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stop_sim_i => stop_sim
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stop_sim_i => stop_sim
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);
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);
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tc0 : entity work.tc_example
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tc0 : entity work.tc_example
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generic map (
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generic map (
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-- < Template info: add generics for testcase component here, if any. >
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-- < Template info: add generics for testcase component here, if any. >
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)
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)
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port map(
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port map(
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clk => clk, -- Template example
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clk => clk, -- Template example
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rst => rst, -- Template example
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rst => rst, -- Template example
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-- < Template info: add more ports for testcase component here. >
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-- < Template info: add more ports for testcase component here. >
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);
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);
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end architecture bhv;
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end architecture bhv;
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