----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- PlTbUtils Testbench ----
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---- PlTbUtils Testbench ----
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---- ----
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---- ----
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---- This file is part of the PlTbUtils project ----
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---- This file is part of the PlTbUtils project ----
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---- http://opencores.org/project,pltbutils ----
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---- http://opencores.org/project,pltbutils ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- PlTbUtils is a collection of functions, procedures and ----
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---- PlTbUtils is a collection of functions, procedures and ----
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---- components for easily creating stimuli and checking response ----
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---- components for easily creating stimuli and checking response ----
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---- in automatic self-checking testbenches. ----
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---- in automatic self-checking testbenches. ----
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---- ----
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---- ----
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---- This is a testbench file, which is used to verify ----
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---- This is a testbench file, which is used to verify ----
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---- - pltbutils_func_pkg ----
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---- - pltbutils_func_pkg ----
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---- - pltbutils_comp ----
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---- - pltbutils_comp ----
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---- This testbench is NOT selfchecking or automatic. ----
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---- This testbench is NOT selfchecking or automatic. ----
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---- Manually check the transcript and waveform, when simulating. ----
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---- Manually check the transcript and waveform, when simulating. ----
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---- It prints some informative text in the transcript, to help ----
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---- It prints some informative text in the transcript, to help ----
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---- with the manual inspection. ----
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---- with the manual inspection. ----
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---- ----
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---- ----
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---- ----
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---- ----
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---- To Do: ----
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---- To Do: ----
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---- - ----
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---- - ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Author(s): ----
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---- - Per Larsson, pela@opencores.org ----
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---- - Per Larsson, pela@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
|
---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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use std.textio.all;
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use work.txt_util.all;
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use work.txt_util.all;
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use work.pltbutils_func_pkg.all;
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use work.pltbutils_func_pkg.all;
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use work.pltbutils_comp_pkg.all;
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use work.pltbutils_comp_pkg.all;
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|
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entity tb_pltbutils is
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entity tb_pltbutils is
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generic (
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generic (
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G_CLK_PERIOD : time := 10 ns
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G_CLK_PERIOD : time := 10 ns
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);
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);
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end entity tb_pltbutils;
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end entity tb_pltbutils;
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|
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architecture bhv of tb_pltbutils is
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architecture bhv of tb_pltbutils is
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|
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-- Simulation status- and control signals
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-- Simulation status- and control signals
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signal test_num : integer;
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signal test_num : integer;
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signal test_name : string(pltbutils_sc.test_name'range);
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signal test_name : string(pltbutils_sc.test_name'range);
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signal info : string(pltbutils_sc.info'range);
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signal info : string(pltbutils_sc.info'range);
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signal checks : integer;
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signal checks : integer;
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signal errors : integer;
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signal errors : integer;
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signal stop_sim : std_logic;
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signal stop_sim : std_logic;
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|
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-- Expected number of checks and number of errors to be reported
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-- Expected number of checks and number of errors to be reported
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-- by pltbutils. The counting is made by variables, but the
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-- by pltbutils. The counting is made by variables, but the
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-- variables are copied to these signals for easier viewing in
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-- variables are copied to these signals for easier viewing in
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-- the simulator's waveform window.
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-- the simulator's waveform window.
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signal expected_checks_cnt : integer := 0;
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signal expected_checks_cnt : integer := 0;
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signal expected_errors_cnt : integer := 0;
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signal expected_errors_cnt : integer := 0;
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|
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-- DUT stimuli and response signals
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-- DUT stimuli and response signals
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signal clk : std_logic;
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signal clk : std_logic;
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signal clk_cnt : integer := 0;
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signal clk_cnt : integer := 0;
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signal clk_cnt_clr : boolean := false;
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signal clk_cnt_clr : boolean := false;
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signal s_i : integer;
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signal s_i : integer;
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signal s_sl : std_logic;
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signal s_sl : std_logic;
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signal s_slv : std_logic_vector(7 downto 0);
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signal s_slv : std_logic_vector(7 downto 0);
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signal s_u : unsigned(7 downto 0);
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signal s_u : unsigned(7 downto 0);
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signal s_s : unsigned(7 downto 0);
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signal s_s : unsigned(7 downto 0);
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|
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begin
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begin
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|
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-- Simulation status and control for viewing in waveform window
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-- Simulation status and control for viewing in waveform window
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test_num <= pltbutils_sc.test_num;
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test_num <= pltbutils_sc.test_num;
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test_name <= pltbutils_sc.test_name;
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test_name <= pltbutils_sc.test_name;
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info <= pltbutils_sc.info;
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info <= pltbutils_sc.info;
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checks <= pltbutils_sc.chk_cnt;
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checks <= pltbutils_sc.chk_cnt;
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errors <= pltbutils_sc.err_cnt;
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errors <= pltbutils_sc.err_cnt;
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stop_sim <= pltbutils_sc.stop_sim;
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stop_sim <= pltbutils_sc.stop_sim;
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|
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-- Clock generator
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-- Clock generator
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clkgen0 : pltbutils_clkgen
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clkgen0 : pltbutils_clkgen
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generic map(
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generic map(
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G_PERIOD => G_CLK_PERIOD
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G_PERIOD => G_CLK_PERIOD
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)
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)
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port map(
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port map(
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clk_o => clk,
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clk_o => clk,
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stop_sim_i => stop_sim
|
stop_sim_i => stop_sim
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);
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);
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|
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-- Clock cycle counter
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-- Clock cycle counter
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p_clk_cnt : process (clk_cnt_clr, clk)
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p_clk_cnt : process (clk_cnt_clr, clk)
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begin
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begin
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if clk_cnt_clr then
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if clk_cnt_clr then
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clk_cnt <= 0;
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clk_cnt <= 0;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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clk_cnt <= clk_cnt + 1;
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clk_cnt <= clk_cnt + 1;
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end if;
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end if;
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end process p_clk_cnt;
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end process p_clk_cnt;
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|
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-- Testcase
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-- Testcase
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p_tc1 : process
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p_tc1 : process
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variable v_expected_tests_cnt : integer := 0;
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variable v_expected_checks_cnt : integer := 0;
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variable v_expected_checks_cnt : integer := 0;
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variable v_expected_errors_cnt : integer := 0;
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variable v_expected_errors_cnt : integer := 0;
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begin
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begin
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|
|
print("<Testing startsim()>");
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print("<Testing startsim()>");
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startsim("tc1", pltbutils_sc);
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startsim("tc1", pltbutils_sc);
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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assert test_num = 0
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assert test_num = 0
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report "test_num after startsim() incorrect"
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report "test_num after startsim() incorrect"
|
severity error;
|
severity error;
|
print("<Done testing startsim()>");
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print("<Done testing startsim()>");
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|
|
print("<Testing testname() with auto-incrementing test_num>");
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print("<Testing starttest() with auto-incrementing test_num>");
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testname("TestName1", pltbutils_sc);
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starttest("TestName1", pltbutils_sc);
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v_expected_tests_cnt := v_expected_tests_cnt + 1;
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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assert test_num = 1
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assert test_num = 1
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report "test_num after startsim() incorrect"
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report "test_num after starttest() incorrect"
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severity error;
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severity error;
|
print("<Done testing testname() with auto-incrementing test_num()>");
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print("<Done testing starttest() with auto-incrementing test_num()>");
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|
|
print("<Testing testname() with explicit test_num>");
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print("<Testing endtest()>");
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testname(3, "TestName2", pltbutils_sc);
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endtest(pltbutils_sc);
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|
print("<Done testing endtest()>");
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|
|
|
print("<Testing starttest() with explicit test_num>");
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|
starttest(3, "TestName2", pltbutils_sc);
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|
v_expected_tests_cnt := v_expected_tests_cnt + 1;
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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assert test_num = 3
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assert test_num = 3
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report "test_num after startsim() incorrect"
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report "test_num after startsim() incorrect"
|
severity error;
|
severity error;
|
print("<Done testing testname() with explicit test_num>");
|
print("<Done testing starttest() with explicit test_num>");
|
|
|
print("<Testing waitclks()>");
|
print("<Testing waitclks()>");
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clk_cnt_clr <= true;
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clk_cnt_clr <= true;
|
wait until rising_edge(clk);
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wait until rising_edge(clk);
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clk_cnt_clr <= false;
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clk_cnt_clr <= false;
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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waitclks(10, clk, pltbutils_sc);
|
waitclks(10, clk, pltbutils_sc);
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assert clk_cnt = 10
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assert clk_cnt = 10
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report "clk_cnt after waitclks() incorrect:" & integer'image(clk_cnt) &
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report "clk_cnt after waitclks() incorrect:" & integer'image(clk_cnt) &
|
" expected:" & integer'image(10)
|
" expected:" & integer'image(10)
|
severity error;
|
severity error;
|
print("<Done testing waitclks()>");
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print("<Done testing waitclks()>");
|
|
|
print("<Testing check() integer>");
|
print("<Testing check() integer>");
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s_i <= 0;
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s_i <= 0;
|
wait until rising_edge(clk);
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wait until rising_edge(clk);
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check("Testing correct integer = 0", s_i, 0, pltbutils_sc);
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check("Testing correct integer = 0", s_i, 0, pltbutils_sc);
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v_expected_checks_cnt := v_expected_checks_cnt + 1;
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v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
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expected_checks_cnt <= v_expected_checks_cnt;
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s_i <= 1;
|
s_i <= 1;
|
wait until rising_edge(clk);
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wait until rising_edge(clk);
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check("Testing correct integer = 1", s_i, 1, pltbutils_sc);
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check("Testing correct integer = 1", s_i, 1, pltbutils_sc);
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v_expected_checks_cnt := v_expected_checks_cnt + 1;
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v_expected_checks_cnt := v_expected_checks_cnt + 1;
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expected_checks_cnt <= v_expected_checks_cnt;
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expected_checks_cnt <= v_expected_checks_cnt;
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s_i <= 17;
|
s_i <= 17;
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing incorrect integer = 17", s_i, 18, pltbutils_sc);
|
check("Testing incorrect integer = 17", s_i, 18, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
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v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
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expected_checks_cnt <= v_expected_checks_cnt;
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v_expected_errors_cnt := v_expected_errors_cnt + 1;
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v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
expected_errors_cnt <= v_expected_errors_cnt;
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s_i <= -1;
|
s_i <= -1;
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing negative integer = -1", s_i, -1, pltbutils_sc);
|
check("Testing negative integer = -1", s_i, -1, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
|
|
print("<Done testing check() integer>");
|
print("<Done testing check() integer>");
|
|
|
print("<Testing check() std_logic>");
|
print("<Testing check() std_logic>");
|
s_sl <= '0';
|
s_sl <= '0';
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing correct std_logic = '0'", s_sl, '0', pltbutils_sc);
|
check("Testing correct std_logic = '0'", s_sl, '0', pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_sl <= '1';
|
s_sl <= '1';
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing correct std_logic = '1'", s_sl, '1', pltbutils_sc);
|
check("Testing correct std_logic = '1'", s_sl, '1', pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_sl <= 'X';
|
s_sl <= 'X';
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing incorrect std_logic = '1'", s_sl, '1', pltbutils_sc);
|
check("Testing incorrect std_logic = '1'", s_sl, '1', pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
print("<Done testing check() std_logic>");
|
print("<Done testing check() std_logic>");
|
|
|
print("<Testing check() std_logic against integer>");
|
print("<Testing check() std_logic against integer>");
|
s_sl <= '0';
|
s_sl <= '0';
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing correct std_logic = '0'", s_sl, 0, pltbutils_sc);
|
check("Testing correct std_logic = '0'", s_sl, 0, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_sl <= '1';
|
s_sl <= '1';
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing correct std_logic = '1'", s_sl, 1, pltbutils_sc);
|
check("Testing correct std_logic = '1'", s_sl, 1, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_sl <= 'X';
|
s_sl <= 'X';
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing incorrect std_logic = '1'", s_sl, 1, pltbutils_sc);
|
check("Testing incorrect std_logic = '1'", s_sl, 1, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
s_sl <= '1';
|
s_sl <= '1';
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing std_logic = '1' with incorrect expected", s_sl, 2, pltbutils_sc);
|
check("Testing std_logic = '1' with incorrect expected", s_sl, 2, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
print("<Done testing check() std_logic against integer>");
|
print("<Done testing check() std_logic against integer>");
|
|
|
print("<Testing check() std_logic_vector>");
|
print("<Testing check() std_logic_vector>");
|
s_slv <= x"00";
|
s_slv <= x"00";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing correct std_logic_vector = x'00'", s_slv, x"00", pltbutils_sc);
|
check("Testing correct std_logic_vector = x'00'", s_slv, x"00", pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_slv <= x"47";
|
s_slv <= x"47";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing correct std_logic_vector = x'47'", s_slv, x"47", pltbutils_sc);
|
check("Testing correct std_logic_vector = x'47'", s_slv, x"47", pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_slv <= x"11";
|
s_slv <= x"11";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing incorrect std_logic_vector = x'11'", s_slv, x"10", pltbutils_sc);
|
check("Testing incorrect std_logic_vector = x'11'", s_slv, x"10", pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
print("<Done testing check() std_logic_vector>");
|
print("<Done testing check() std_logic_vector>");
|
|
|
print("<Testing check() std_logic_vector with mask>");
|
print("<Testing check() std_logic_vector with mask>");
|
s_slv <= x"47";
|
s_slv <= x"47";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing std_logic_vector = x'47' with correct nibble mask", s_slv, x"57", x"0F", pltbutils_sc);
|
check("Testing std_logic_vector = x'47' with correct nibble mask", s_slv, x"57", x"0F", pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_slv <= x"47";
|
s_slv <= x"47";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing std_logic_vector = x'47' with incorrect nibble mask", s_slv, x"57", x"F0", pltbutils_sc);
|
check("Testing std_logic_vector = x'47' with incorrect nibble mask", s_slv, x"57", x"F0", pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
print("<Done testing check() std_logic_vector with mask>");
|
print("<Done testing check() std_logic_vector with mask>");
|
|
|
print("<Testing check() std_logic_vector against integer>");
|
print("<Testing check() std_logic_vector against integer>");
|
s_slv <= x"00";
|
s_slv <= x"00";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing correct std_logic_vector = x'00'", s_slv, 0, pltbutils_sc);
|
check("Testing correct std_logic_vector = x'00'", s_slv, 0, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_slv <= x"47";
|
s_slv <= x"47";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing correct std_logic_vector = x'47'", s_slv, 16#47#, pltbutils_sc);
|
check("Testing correct std_logic_vector = x'47'", s_slv, 16#47#, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_slv <= x"11";
|
s_slv <= x"11";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing incorrect std_logic_vector = x'11'", s_slv, 16#10#, pltbutils_sc);
|
check("Testing incorrect std_logic_vector = x'11'", s_slv, 16#10#, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
s_slv <= x"FF";
|
s_slv <= x"FF";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing negative std_logic_vector = x'FF'", s_slv, -1, pltbutils_sc);
|
check("Testing negative std_logic_vector = x'FF'", s_slv, -1, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
print("<Done testing check() std_logic_vector against integer>");
|
print("<Done testing check() std_logic_vector against integer>");
|
|
|
print("<Testing check() std_logic_vector with mask against integer>");
|
print("<Testing check() std_logic_vector with mask against integer>");
|
s_slv <= x"47";
|
s_slv <= x"47";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing std_logic_vector = x'47' with correct nibble mask", s_slv, 16#57#, x"0F", pltbutils_sc);
|
check("Testing std_logic_vector = x'47' with correct nibble mask", s_slv, 16#57#, x"0F", pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_slv <= x"47";
|
s_slv <= x"47";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing std_logic_vector = x'47' with incorrect nibble mask", s_slv, 16#57#, x"F0", pltbutils_sc);
|
check("Testing std_logic_vector = x'47' with incorrect nibble mask", s_slv, 16#57#, x"F0", pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
print("<Done testing check() std_logic_vector with mask against integer>");
|
print("<Done testing check() std_logic_vector with mask against integer>");
|
|
|
print("<Testing check() unsigned>");
|
print("<Testing check() unsigned>");
|
s_u <= x"00";
|
s_u <= x"00";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing correct unsigned = x'00'", s_u, x"00", pltbutils_sc);
|
check("Testing correct unsigned = x'00'", s_u, x"00", pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_u <= x"47";
|
s_u <= x"47";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing correct unsigned = x'47'", s_u, x"47", pltbutils_sc);
|
check("Testing correct unsigned = x'47'", s_u, x"47", pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_u <= x"11";
|
s_u <= x"11";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing incorrect unsigned = x'11'", s_u, x"10", pltbutils_sc);
|
check("Testing incorrect unsigned = x'11'", s_u, x"10", pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
print("<Done testing check() unsigned>");
|
print("<Done testing check() unsigned>");
|
|
|
print("<Testing check() unsigned against integer>");
|
print("<Testing check() unsigned against integer>");
|
s_u <= x"00";
|
s_u <= x"00";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing correct unsigned = x'00'", s_u, 0, pltbutils_sc);
|
check("Testing correct unsigned = x'00'", s_u, 0, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_u <= x"47";
|
s_u <= x"47";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing correct unsigned = x'47'", s_u, 16#47#, pltbutils_sc);
|
check("Testing correct unsigned = x'47'", s_u, 16#47#, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_u <= x"11";
|
s_u <= x"11";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing incorrect unsigned = x'11'", s_u, 16#10#, pltbutils_sc);
|
check("Testing incorrect unsigned = x'11'", s_u, 16#10#, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
print("<Done testing check() unsigned against integer>");
|
print("<Done testing check() unsigned against integer>");
|
|
|
print("<Testing check() signed>");
|
print("<Testing check() signed>");
|
s_s <= x"00";
|
s_s <= x"00";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing correct signed = x'00'", s_s, x"00", pltbutils_sc);
|
check("Testing correct signed = x'00'", s_s, x"00", pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_s <= x"47";
|
s_s <= x"47";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing correct signed = x'47'", s_s, x"47", pltbutils_sc);
|
check("Testing correct signed = x'47'", s_s, x"47", pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_s <= x"11";
|
s_s <= x"11";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing incorrect signed = x'11'", s_s, x"10", pltbutils_sc);
|
check("Testing incorrect signed = x'11'", s_s, x"10", pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
s_s <= x"FF";
|
s_s <= x"FF";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing negative signed = x'FF'", s_s, x"FF", pltbutils_sc);
|
check("Testing negative signed = x'FF'", s_s, x"FF", pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
print("<Done testing check() signed>");
|
print("<Done testing check() signed>");
|
|
|
print("<Testing check() signed against integer>");
|
print("<Testing check() signed against integer>");
|
s_s <= x"00";
|
s_s <= x"00";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing correct signed = x'00'", s_s, 0, pltbutils_sc);
|
check("Testing correct signed = x'00'", s_s, 0, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_s <= x"47";
|
s_s <= x"47";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing correct signed = x'47'", s_s, 16#47#, pltbutils_sc);
|
check("Testing correct signed = x'47'", s_s, 16#47#, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_s <= x"11";
|
s_s <= x"11";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing incorrect signed = x'11'", s_s, 16#10#, pltbutils_sc);
|
check("Testing incorrect signed = x'11'", s_s, 16#10#, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
s_s <= x"FF";
|
s_s <= x"FF";
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
print("The following check fails in ModelSim for unknown reason." &
|
print("The following check fails in ModelSim for unknown reason." &
|
" It causes mismatch between expected number of errors" &
|
" It causes mismatch between expected number of errors" &
|
" and the number presented by endsim()");
|
" and the number presented by endsim()");
|
check("Testing negative signed = x'FF'", s_s, -1, pltbutils_sc);
|
check("Testing negative signed = x'FF'", s_s, -1, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
print("<Done testing check() signed against integer>");
|
print("<Done testing check() signed against integer>");
|
|
|
print("<Testing check() boolean expression>");
|
print("<Testing check() boolean expression>");
|
s_i <= 0;
|
s_i <= 0;
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing correct boolean expression 0 = 16#00#", s_i = 16#00#, pltbutils_sc);
|
check("Testing correct boolean expression 0 = 16#00#", s_i = 16#00#, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
s_i <= 47;
|
s_i <= 47;
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
check("Testing incorrect boolean expression 47 < 16#10#", s_i < 16#10#, pltbutils_sc);
|
check("Testing incorrect boolean expression 47 < 16#10#", s_i < 16#10#, pltbutils_sc);
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
v_expected_checks_cnt := v_expected_checks_cnt + 1;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
expected_checks_cnt <= v_expected_checks_cnt;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
v_expected_errors_cnt := v_expected_errors_cnt + 1;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
expected_errors_cnt <= v_expected_errors_cnt;
|
print("<Done testing check() boolean expresson>");
|
print("<Done testing check() boolean expresson>");
|
|
|
|
print("<Testing endtest()>");
|
|
endtest(pltbutils_sc);
|
|
print("<Done testing endtest()>");
|
|
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
print("<Testing endsim()>");
|
print("<Testing endsim()>");
|
|
print("Expected number of tests: " & str(v_expected_tests_cnt));
|
print("Expected number of checks: " & str(v_expected_checks_cnt));
|
print("Expected number of checks: " & str(v_expected_checks_cnt));
|
print("Expected number of errors: " & str(v_expected_errors_cnt));
|
print("Expected number of errors: " & str(v_expected_errors_cnt));
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
endsim(pltbutils_sc, true);
|
endsim(pltbutils_sc, true);
|
wait until rising_edge(clk);
|
wait until rising_edge(clk);
|
print("<Done testing endsim()>");
|
print("<Done testing endsim()>");
|
wait;
|
wait;
|
end process p_tc1;
|
end process p_tc1;
|
end architecture bhv;
|
end architecture bhv;
|
|
|