-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <https://github.com/skordal/potato/issues>
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-- Report bugs and issues on <https://github.com/skordal/potato/issues>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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--! @brief Dummy module for an SoC implementation.
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--! @brief Dummy module for an SoC implementation.
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--! Reads returns whatever was last written into the module.
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--! Reads returns whatever was last written into the module.
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entity pp_soc_dummy is
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entity pp_soc_dummy is
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- Wishbone signals:
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-- Wishbone signals:
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wb_dat_in : in std_logic_vector(31 downto 0);
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wb_dat_in : in std_logic_vector(31 downto 0);
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wb_dat_out : out std_logic_vector(31 downto 0);
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wb_dat_out : out std_logic_vector(31 downto 0);
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wb_cyc_in : in std_logic;
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wb_cyc_in : in std_logic;
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wb_stb_in : in std_logic;
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wb_stb_in : in std_logic;
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wb_we_in : in std_logic;
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wb_we_in : in std_logic;
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wb_ack_out : out std_logic
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wb_ack_out : out std_logic
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);
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);
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end entity pp_soc_dummy;
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end entity pp_soc_dummy;
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architecture behaviour of pp_soc_dummy is
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architecture behaviour of pp_soc_dummy is
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signal reg : std_logic_vector(31 downto 0);
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signal reg : std_logic_vector(31 downto 0);
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signal ack : std_logic;
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signal ack : std_logic;
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begin
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begin
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wb_ack_out <= ack and wb_cyc_in and wb_stb_in;
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wb_ack_out <= ack and wb_cyc_in and wb_stb_in;
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wishbone: process(clk)
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wishbone: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if reset = '1' then
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if reset = '1' then
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reg <= (others => '0');
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reg <= (others => '0');
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ack <= '0';
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ack <= '0';
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else
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else
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if wb_cyc_in = '1' and wb_stb_in = '1' and ack = '0' then
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if wb_cyc_in = '1' and wb_stb_in = '1' and ack = '0' then
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if wb_we_in = '1' then
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if wb_we_in = '1' then
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reg <= wb_dat_in;
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reg <= wb_dat_in;
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ack <= '1';
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ack <= '1';
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else
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else
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wb_dat_out <= reg;
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wb_dat_out <= reg;
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ack <= '1';
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ack <= '1';
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end if;
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end if;
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elsif wb_stb_in = '0' then
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elsif wb_stb_in = '0' then
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ack <= '0';
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ack <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process wishbone;
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end process wishbone;
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end architecture behaviour;
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end architecture behaviour;
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