-- Practical Test Application for the Potato Processor
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <https://github.com/skordal/potato-test/issues>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity imem_wrapper is
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entity imem_wrapper is
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- Wishbone interface:
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-- Wishbone interface:
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wb_adr_in : in std_logic_vector(12 downto 0);
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wb_adr_in : in std_logic_vector(12 downto 0);
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wb_dat_out : out std_logic_vector(31 downto 0);
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wb_dat_out : out std_logic_vector(31 downto 0);
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wb_cyc_in : in std_logic;
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wb_cyc_in : in std_logic;
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wb_stb_in : in std_logic;
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wb_stb_in : in std_logic;
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wb_ack_out : out std_logic
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wb_ack_out : out std_logic
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);
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);
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end entity imem_wrapper;
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end entity imem_wrapper;
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architecture behaviour of imem_wrapper is
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architecture behaviour of imem_wrapper is
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type wb_state is (IDLE, READ_ACK);
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type wb_state is (IDLE, READ_ACK);
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signal state : wb_state := IDLE;
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signal state : wb_state := IDLE;
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signal address : std_logic_vector(10 downto 0);
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signal address : std_logic_vector(10 downto 0);
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signal data : std_logic_vector(31 downto 0);
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signal data : std_logic_vector(31 downto 0);
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signal ack : std_logic := '0';
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signal ack : std_logic := '0';
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begin
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begin
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imem: entity work.instruction_rom
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imem: entity work.instruction_rom
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port map(
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port map(
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clka => clk,
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clka => clk,
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addra => address,
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addra => address,
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douta => wb_dat_out
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douta => wb_dat_out
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);
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);
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wb_ack_out <= ack and wb_cyc_in and wb_stb_in;
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wb_ack_out <= ack and wb_cyc_in and wb_stb_in;
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wishbone: process(clk)
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wishbone: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if reset = '1' then
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if reset = '1' then
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ack <= '0';
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ack <= '0';
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state <= IDLE;
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state <= IDLE;
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else
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else
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case state is
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case state is
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when IDLE =>
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when IDLE =>
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if wb_cyc_in = '1' and wb_stb_in = '1' then
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if wb_cyc_in = '1' and wb_stb_in = '1' then
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address <= wb_adr_in(12 downto 2);
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address <= wb_adr_in(12 downto 2);
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state <= READ_ACK;
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state <= READ_ACK;
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end if;
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end if;
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when READ_ACK =>
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when READ_ACK =>
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if ack = '0' then
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if ack = '0' then
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ack <= '1';
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ack <= '1';
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elsif wb_stb_in = '0' then
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elsif wb_stb_in = '0' then
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ack <= '0';
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ack <= '0';
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state <= IDLE;
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state <= IDLE;
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end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process wishbone;
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end process wishbone;
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end architecture behaviour;
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end architecture behaviour;
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