-- Practical Test Application for the Potato Processor
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-- Practical Test Application for the Potato Processor
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-- (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity toplevel is
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entity toplevel is
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port(
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port(
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clk : in std_logic; -- System clock, 100 MHz
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clk : in std_logic; -- System clock, 100 MHz
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reset_n : in std_logic; -- CPU reset signal, active low
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reset_n : in std_logic; -- CPU reset signal, active low
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-- External interrupt input:
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-- External interrupt input:
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external_interrupt : in std_logic;
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external_interrupt : in std_logic;
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-- GPIO pins, must be inout to use with the GPIO module:
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-- GPIO pins, must be inout to use with the GPIO module:
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switches : inout std_logic_vector(15 downto 0);
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switches : inout std_logic_vector(15 downto 0);
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leds : inout std_logic_vector(15 downto 0);
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leds : inout std_logic_vector(15 downto 0);
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-- UART1 (host) pins:
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-- UART1 (host) pins:
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uart_txd : out std_logic;
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uart_txd : out std_logic;
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uart_rxd : in std_logic
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uart_rxd : in std_logic
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);
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);
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end entity toplevel;
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end entity toplevel;
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architecture behaviour of toplevel is
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architecture behaviour of toplevel is
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signal system_clk : std_logic;
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signal system_clk : std_logic;
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signal timer_clk : std_logic;
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signal timer_clk : std_logic;
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-- Active high reset signal:
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-- Active high reset signal:
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signal reset : std_logic;
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signal reset : std_logic;
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-- IRQs:
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-- IRQs:
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signal irq : std_logic_vector(7 downto 0);
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signal irq : std_logic_vector(7 downto 0);
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signal uart_irq_rts, uart_irq_recv : std_logic;
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signal uart_irq_rts, uart_irq_recv : std_logic;
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signal timer_irq : std_logic;
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signal timer_irq : std_logic;
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-- Processor wishbone interface:
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-- Processor wishbone interface:
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signal p_adr_out : std_logic_vector(31 downto 0);
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signal p_adr_out : std_logic_vector(31 downto 0);
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signal p_dat_out : std_logic_vector(31 downto 0);
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signal p_dat_out : std_logic_vector(31 downto 0);
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signal p_dat_in : std_logic_vector(31 downto 0);
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signal p_dat_in : std_logic_vector(31 downto 0);
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signal p_sel_out : std_logic_vector( 3 downto 0);
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signal p_sel_out : std_logic_vector( 3 downto 0);
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signal p_we_out : std_logic;
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signal p_we_out : std_logic;
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signal p_cyc_out, p_stb_out : std_logic;
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signal p_cyc_out, p_stb_out : std_logic;
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signal p_ack_in : std_logic;
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signal p_ack_in : std_logic;
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-- Instruction memory wishbone interface:
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-- Instruction memory wishbone interface:
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signal imem_adr_in : std_logic_vector(12 downto 0);
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signal imem_adr_in : std_logic_vector(12 downto 0);
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signal imem_dat_out : std_logic_vector(31 downto 0);
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signal imem_dat_out : std_logic_vector(31 downto 0);
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signal imem_cyc_in, imem_stb_in : std_logic;
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signal imem_cyc_in, imem_stb_in : std_logic;
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signal imem_ack_out : std_logic;
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signal imem_ack_out : std_logic;
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-- Data memory wishbone interface:
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-- Data memory wishbone interface:
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signal dmem_adr_in : std_logic_vector(12 downto 0);
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signal dmem_adr_in : std_logic_vector(12 downto 0);
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signal dmem_dat_in : std_logic_vector(31 downto 0);
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signal dmem_dat_in : std_logic_vector(31 downto 0);
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signal dmem_dat_out : std_logic_vector(31 downto 0);
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signal dmem_dat_out : std_logic_vector(31 downto 0);
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signal dmem_sel_in : std_logic_vector( 3 downto 0);
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signal dmem_sel_in : std_logic_vector( 3 downto 0);
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signal dmem_we_in : std_logic;
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signal dmem_we_in : std_logic;
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signal dmem_cyc_in, dmem_stb_in : std_logic;
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signal dmem_cyc_in, dmem_stb_in : std_logic;
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signal dmem_ack_out : std_logic;
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signal dmem_ack_out : std_logic;
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-- GPIO module I (switches) wishbone interface:
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-- GPIO module I (switches) wishbone interface:
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signal gpio1_adr_in : std_logic_vector(1 downto 0);
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signal gpio1_adr_in : std_logic_vector(1 downto 0);
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signal gpio1_dat_in : std_logic_vector(31 downto 0);
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signal gpio1_dat_in : std_logic_vector(31 downto 0);
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signal gpio1_dat_out : std_logic_vector(31 downto 0);
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signal gpio1_dat_out : std_logic_vector(31 downto 0);
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signal gpio1_we_in : std_logic;
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signal gpio1_we_in : std_logic;
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signal gpio1_cyc_in, gpio1_stb_in : std_logic;
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signal gpio1_cyc_in, gpio1_stb_in : std_logic;
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signal gpio1_ack_out : std_logic;
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signal gpio1_ack_out : std_logic;
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-- GPIO module II (LEDs) wishbone interface:
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-- GPIO module II (LEDs) wishbone interface:
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signal gpio2_adr_in : std_logic_vector(1 downto 0);
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signal gpio2_adr_in : std_logic_vector(1 downto 0);
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signal gpio2_dat_in : std_logic_vector(31 downto 0);
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signal gpio2_dat_in : std_logic_vector(31 downto 0);
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signal gpio2_dat_out : std_logic_vector(31 downto 0);
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signal gpio2_dat_out : std_logic_vector(31 downto 0);
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signal gpio2_we_in : std_logic;
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signal gpio2_we_in : std_logic;
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signal gpio2_cyc_in, gpio2_stb_in : std_logic;
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signal gpio2_cyc_in, gpio2_stb_in : std_logic;
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signal gpio2_ack_out : std_logic;
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signal gpio2_ack_out : std_logic;
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-- UART module wishbone interface:
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-- UART module wishbone interface:
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signal uart_adr_in : std_logic_vector(1 downto 0);
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signal uart_adr_in : std_logic_vector(1 downto 0);
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signal uart_dat_in : std_logic_vector(7 downto 0);
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signal uart_dat_in : std_logic_vector(7 downto 0);
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signal uart_dat_out : std_logic_vector(7 downto 0);
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signal uart_dat_out : std_logic_vector(7 downto 0);
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signal uart_we_in : std_logic;
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signal uart_we_in : std_logic;
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signal uart_cyc_in, uart_stb_in : std_logic;
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signal uart_cyc_in, uart_stb_in : std_logic;
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signal uart_ack_out : std_logic;
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signal uart_ack_out : std_logic;
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-- Timer module wishbone interface:
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-- Timer module wishbone interface:
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signal timer_adr_in : std_logic_vector(1 downto 0);
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signal timer_adr_in : std_logic_vector(1 downto 0);
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signal timer_dat_in : std_logic_vector(31 downto 0);
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signal timer_dat_in : std_logic_vector(31 downto 0);
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signal timer_dat_out : std_logic_vector(31 downto 0);
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signal timer_dat_out : std_logic_vector(31 downto 0);
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signal timer_we_in : std_logic;
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signal timer_we_in : std_logic;
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signal timer_cyc_in, timer_stb_in : std_logic;
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signal timer_cyc_in, timer_stb_in : std_logic;
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signal timer_ack_out : std_logic;
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signal timer_ack_out : std_logic;
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-- Dummy module interface:
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-- Dummy module interface:
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signal dummy_dat_in : std_logic_vector(31 downto 0);
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signal dummy_dat_in : std_logic_vector(31 downto 0);
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signal dummy_dat_out : std_logic_vector(31 downto 0);
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signal dummy_dat_out : std_logic_vector(31 downto 0);
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signal dummy_we_in : std_logic;
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signal dummy_we_in : std_logic;
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signal dummy_cyc_in, dummy_stb_in : std_logic;
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signal dummy_cyc_in, dummy_stb_in : std_logic;
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signal dummy_ack_out : std_logic;
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signal dummy_ack_out : std_logic;
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-- Address decoder signals:
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-- Address decoder signals:
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type ad_state_type is (IDLE, BUSY);
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type ad_state_type is (IDLE, BUSY);
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signal ad_state : ad_state_type;
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signal ad_state : ad_state_type;
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type module_name is (
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type module_name is (
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MODULE_IMEM, MODULE_DMEM, -- Memory modules
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MODULE_IMEM, MODULE_DMEM, -- Memory modules
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MODULE_GPIO1, MODULE_GPIO2, -- GPIO modules
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MODULE_GPIO1, MODULE_GPIO2, -- GPIO modules
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MODULE_UART, -- UART module
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MODULE_UART, -- UART module
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MODULE_TIMER, -- Timer module
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MODULE_TIMER, -- Timer module
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MODULE_DUMMY, -- Dummy module, used for invalid addresses
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MODULE_DUMMY, -- Dummy module, used for invalid addresses
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MODULE_NONE -- Boring no-module mode
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MODULE_NONE -- Boring no-module mode
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);
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);
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signal active_module : module_name;
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signal active_module : module_name;
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begin
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begin
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reset <= not reset_n;
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reset <= not reset_n;
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irq <= (
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irq <= (
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0 => external_interrupt,
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0 => external_interrupt,
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1 => uart_irq_rts, 2 => uart_irq_recv,
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1 => uart_irq_rts, 2 => uart_irq_recv,
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5 => timer_irq, others => '0'
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5 => timer_irq, others => '0'
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);
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);
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clkgen: entity work.clock_generator
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clkgen: entity work.clock_generator
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port map(
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port map(
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clk => clk,
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clk => clk,
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system_clk => system_clk,
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system_clk => system_clk,
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timer_clk => timer_clk
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timer_clk => timer_clk
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);
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);
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processor: entity work.pp_potato
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processor: entity work.pp_potato
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port map(
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port map(
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clk => system_clk,
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clk => system_clk,
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reset => reset,
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reset => reset,
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irq => irq,
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irq => irq,
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fromhost_data => (others => '0'),
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fromhost_data => (others => '0'),
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fromhost_updated => '0',
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fromhost_updated => '0',
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tohost_data => open,
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tohost_data => open,
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tohost_updated => open,
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tohost_updated => open,
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wb_adr_out => p_adr_out,
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wb_adr_out => p_adr_out,
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wb_dat_out => p_dat_out,
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wb_dat_out => p_dat_out,
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wb_dat_in => p_dat_in,
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wb_dat_in => p_dat_in,
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wb_sel_out => p_sel_out,
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wb_sel_out => p_sel_out,
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wb_we_out => p_we_out,
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wb_we_out => p_we_out,
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wb_cyc_out => p_cyc_out,
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wb_cyc_out => p_cyc_out,
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wb_stb_out => p_stb_out,
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wb_stb_out => p_stb_out,
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wb_ack_in => p_ack_in
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wb_ack_in => p_ack_in
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);
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);
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imem: entity work.imem_wrapper
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imem: entity work.imem_wrapper
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port map(
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port map(
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clk => system_clk,
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clk => system_clk,
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reset => reset,
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reset => reset,
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wb_adr_in => imem_adr_in,
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wb_adr_in => imem_adr_in,
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wb_dat_out => imem_dat_out,
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wb_dat_out => imem_dat_out,
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wb_cyc_in => imem_cyc_in,
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wb_cyc_in => imem_cyc_in,
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wb_stb_in => imem_stb_in,
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wb_stb_in => imem_stb_in,
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wb_ack_out => imem_ack_out
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wb_ack_out => imem_ack_out
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);
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);
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dmem: entity work.pp_soc_memory
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dmem: entity work.pp_soc_memory
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generic map(
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generic map(
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MEMORY_SIZE => 8192
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MEMORY_SIZE => 8192
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) port map(
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) port map(
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clk => system_clk,
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clk => system_clk,
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reset => reset,
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reset => reset,
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wb_adr_in => dmem_adr_in,
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wb_adr_in => dmem_adr_in,
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wb_dat_in => dmem_dat_in,
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wb_dat_in => dmem_dat_in,
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wb_dat_out => dmem_dat_out,
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wb_dat_out => dmem_dat_out,
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wb_sel_in => dmem_sel_in,
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wb_sel_in => dmem_sel_in,
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wb_we_in => dmem_we_in,
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wb_we_in => dmem_we_in,
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wb_cyc_in => dmem_cyc_in,
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wb_cyc_in => dmem_cyc_in,
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wb_stb_in => dmem_stb_in,
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wb_stb_in => dmem_stb_in,
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wb_ack_out => dmem_ack_out
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wb_ack_out => dmem_ack_out
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);
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);
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gpio1: entity work.pp_soc_gpio
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gpio1: entity work.pp_soc_gpio
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generic map(
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generic map(
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NUM_GPIOS => 16
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NUM_GPIOS => 16
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) port map(
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) port map(
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clk => system_clk,
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clk => system_clk,
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reset => reset,
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reset => reset,
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gpio => switches,
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gpio => switches,
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wb_adr_in => gpio1_adr_in,
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wb_adr_in => gpio1_adr_in,
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wb_dat_in => gpio1_dat_in,
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wb_dat_in => gpio1_dat_in,
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wb_dat_out => gpio1_dat_out,
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wb_dat_out => gpio1_dat_out,
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wb_cyc_in => gpio1_cyc_in,
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wb_cyc_in => gpio1_cyc_in,
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wb_stb_in => gpio1_stb_in,
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wb_stb_in => gpio1_stb_in,
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wb_we_in => gpio1_we_in,
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wb_we_in => gpio1_we_in,
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wb_ack_out => gpio1_ack_out
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wb_ack_out => gpio1_ack_out
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);
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);
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gpio2: entity work.pp_soc_gpio
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gpio2: entity work.pp_soc_gpio
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generic map(
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generic map(
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NUM_GPIOS => 16
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NUM_GPIOS => 16
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) port map(
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) port map(
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clk => system_clk,
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clk => system_clk,
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reset => reset,
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reset => reset,
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gpio => leds,
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gpio => leds,
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wb_adr_in => gpio2_adr_in,
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wb_adr_in => gpio2_adr_in,
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wb_dat_in => gpio2_dat_in,
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wb_dat_in => gpio2_dat_in,
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wb_dat_out => gpio2_dat_out,
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wb_dat_out => gpio2_dat_out,
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wb_cyc_in => gpio2_cyc_in,
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wb_cyc_in => gpio2_cyc_in,
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wb_stb_in => gpio2_stb_in,
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wb_stb_in => gpio2_stb_in,
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wb_we_in => gpio2_we_in,
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wb_we_in => gpio2_we_in,
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wb_ack_out => gpio2_ack_out
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wb_ack_out => gpio2_ack_out
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);
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);
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uart1: entity work.pp_soc_uart
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uart1: entity work.pp_soc_uart
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generic map(
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generic map(
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FIFO_DEPTH => 64,
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FIFO_DEPTH => 64,
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--SAMPLE_CLK_DIVISOR => 27 -- For 50 MHz
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SAMPLE_CLK_DIVISOR => 27 -- For 50 MHz
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SAMPLE_CLK_DIVISOR => 33 -- For 60 MHz
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--SAMPLE_CLK_DIVISOR => 33 -- For 60 MHz
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) port map(
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) port map(
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clk => system_clk,
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clk => system_clk,
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reset => reset,
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reset => reset,
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txd => uart_txd,
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txd => uart_txd,
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rxd => uart_rxd,
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rxd => uart_rxd,
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irq_send_buffer_empty => uart_irq_rts,
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irq_send_buffer_empty => uart_irq_rts,
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irq_data_received => uart_irq_recv,
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irq_data_received => uart_irq_recv,
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wb_adr_in => uart_adr_in,
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wb_adr_in => uart_adr_in,
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wb_dat_in => uart_dat_in,
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wb_dat_in => uart_dat_in,
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wb_dat_out => uart_dat_out,
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wb_dat_out => uart_dat_out,
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wb_cyc_in => uart_cyc_in,
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wb_cyc_in => uart_cyc_in,
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wb_stb_in => uart_stb_in,
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wb_stb_in => uart_stb_in,
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wb_we_in => uart_we_in,
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wb_we_in => uart_we_in,
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wb_ack_out => uart_ack_out
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wb_ack_out => uart_ack_out
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);
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);
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|
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timer1: entity work.pp_soc_timer
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timer1: entity work.pp_soc_timer
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port map(
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port map(
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clk => system_clk,
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clk => system_clk,
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reset => reset,
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reset => reset,
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irq => timer_irq,
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irq => timer_irq,
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wb_adr_in => timer_adr_in,
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wb_adr_in => timer_adr_in,
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wb_dat_in => timer_dat_in,
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wb_dat_in => timer_dat_in,
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wb_dat_out => timer_dat_out,
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wb_dat_out => timer_dat_out,
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wb_cyc_in => timer_cyc_in,
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wb_cyc_in => timer_cyc_in,
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wb_stb_in => timer_stb_in,
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wb_stb_in => timer_stb_in,
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wb_we_in => timer_we_in,
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wb_we_in => timer_we_in,
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wb_ack_out => timer_ack_out
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wb_ack_out => timer_ack_out
|
);
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);
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|
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dummy: entity work.pp_soc_dummy
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dummy: entity work.pp_soc_dummy
|
port map(
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port map(
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clk => system_clk,
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clk => system_clk,
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reset => reset,
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reset => reset,
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wb_dat_in => dummy_dat_in,
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wb_dat_in => dummy_dat_in,
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wb_dat_out => dummy_dat_out,
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wb_dat_out => dummy_dat_out,
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wb_cyc_in => dummy_cyc_in,
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wb_cyc_in => dummy_cyc_in,
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wb_stb_in => dummy_stb_in,
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wb_stb_in => dummy_stb_in,
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wb_we_in => dummy_we_in,
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wb_we_in => dummy_we_in,
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wb_ack_out => dummy_ack_out
|
wb_ack_out => dummy_ack_out
|
);
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);
|
|
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imem_cyc_in <= p_cyc_out when active_module = MODULE_IMEM else '0';
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imem_cyc_in <= p_cyc_out when active_module = MODULE_IMEM else '0';
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dmem_cyc_in <= p_cyc_out when active_module = MODULE_DMEM else '0';
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dmem_cyc_in <= p_cyc_out when active_module = MODULE_DMEM else '0';
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gpio1_cyc_in <= p_cyc_out when active_module = MODULE_GPIO1 else '0';
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gpio1_cyc_in <= p_cyc_out when active_module = MODULE_GPIO1 else '0';
|
gpio2_cyc_in <= p_cyc_out when active_module = MODULE_GPIO2 else '0';
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gpio2_cyc_in <= p_cyc_out when active_module = MODULE_GPIO2 else '0';
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uart_cyc_in <= p_cyc_out when active_module = MODULE_UART else '0';
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uart_cyc_in <= p_cyc_out when active_module = MODULE_UART else '0';
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timer_cyc_in <= p_cyc_out when active_module = MODULE_TIMER else '0';
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timer_cyc_in <= p_cyc_out when active_module = MODULE_TIMER else '0';
|
dummy_cyc_in <= p_cyc_out when active_module = MODULE_DUMMY else '0';
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dummy_cyc_in <= p_cyc_out when active_module = MODULE_DUMMY else '0';
|
|
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imem_stb_in <= p_stb_out when active_module = MODULE_IMEM else '0';
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imem_stb_in <= p_stb_out when active_module = MODULE_IMEM else '0';
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dmem_stb_in <= p_stb_out when active_module = MODULE_DMEM else '0';
|
dmem_stb_in <= p_stb_out when active_module = MODULE_DMEM else '0';
|
gpio1_stb_in <= p_stb_out when active_module = MODULE_GPIO1 else '0';
|
gpio1_stb_in <= p_stb_out when active_module = MODULE_GPIO1 else '0';
|
gpio2_stb_in <= p_stb_out when active_module = MODULE_GPIO2 else '0';
|
gpio2_stb_in <= p_stb_out when active_module = MODULE_GPIO2 else '0';
|
uart_stb_in <= p_stb_out when active_module = MODULE_UART else '0';
|
uart_stb_in <= p_stb_out when active_module = MODULE_UART else '0';
|
timer_stb_in <= p_stb_out when active_module = MODULE_TIMER else '0';
|
timer_stb_in <= p_stb_out when active_module = MODULE_TIMER else '0';
|
dummy_stb_in <= p_stb_out when active_module = MODULE_DUMMY else '0';
|
dummy_stb_in <= p_stb_out when active_module = MODULE_DUMMY else '0';
|
|
|
imem_adr_in <= p_adr_out(12 downto 0);
|
imem_adr_in <= p_adr_out(12 downto 0);
|
dmem_adr_in <= p_adr_out(12 downto 0);
|
dmem_adr_in <= p_adr_out(12 downto 0);
|
gpio1_adr_in <= p_adr_out(3 downto 2);
|
gpio1_adr_in <= p_adr_out(3 downto 2);
|
gpio2_adr_in <= p_adr_out(3 downto 2);
|
gpio2_adr_in <= p_adr_out(3 downto 2);
|
uart_adr_in <= p_adr_out(3 downto 2);
|
uart_adr_in <= p_adr_out(3 downto 2);
|
timer_adr_in <= p_adr_out(3 downto 2);
|
timer_adr_in <= p_adr_out(3 downto 2);
|
|
|
dmem_dat_in <= p_dat_out;
|
dmem_dat_in <= p_dat_out;
|
gpio1_dat_in <= p_dat_out;
|
gpio1_dat_in <= p_dat_out;
|
gpio2_dat_in <= p_dat_out;
|
gpio2_dat_in <= p_dat_out;
|
uart_dat_in <= p_dat_out(7 downto 0);
|
uart_dat_in <= p_dat_out(7 downto 0);
|
timer_dat_in <= p_dat_out;
|
timer_dat_in <= p_dat_out;
|
dummy_dat_in <= p_dat_out;
|
dummy_dat_in <= p_dat_out;
|
|
|
dmem_sel_in <= p_sel_out;
|
dmem_sel_in <= p_sel_out;
|
|
|
gpio1_we_in <= p_we_out;
|
gpio1_we_in <= p_we_out;
|
gpio2_we_in <= p_we_out;
|
gpio2_we_in <= p_we_out;
|
dmem_we_in <= p_we_out;
|
dmem_we_in <= p_we_out;
|
uart_we_in <= p_we_out;
|
uart_we_in <= p_we_out;
|
timer_we_in <= p_we_out;
|
timer_we_in <= p_we_out;
|
dummy_we_in <= p_we_out;
|
dummy_we_in <= p_we_out;
|
|
|
address_decoder: process(system_clk)
|
address_decoder: process(system_clk)
|
begin
|
begin
|
if rising_edge(system_clk) then
|
if rising_edge(system_clk) then
|
if reset = '1' then
|
if reset = '1' then
|
ad_state <= IDLE;
|
ad_state <= IDLE;
|
active_module <= MODULE_NONE;
|
active_module <= MODULE_NONE;
|
else
|
else
|
case ad_state is
|
case ad_state is
|
when IDLE =>
|
when IDLE =>
|
if p_cyc_out = '1' and p_stb_out = '1' then
|
if p_cyc_out = '1' then
|
if p_adr_out(31 downto 13) = b"0000000000000000000" then
|
if p_adr_out(31 downto 13) = b"0000000000000000000" then
|
active_module <= MODULE_IMEM;
|
active_module <= MODULE_IMEM;
|
ad_state <= BUSY;
|
ad_state <= BUSY;
|
elsif p_adr_out(31 downto 13) = b"0000000000000000001" then -- 0x2000
|
elsif p_adr_out(31 downto 13) = b"0000000000000000001" then -- 0x2000
|
active_module <= MODULE_DMEM;
|
active_module <= MODULE_DMEM;
|
ad_state <= BUSY;
|
ad_state <= BUSY;
|
elsif p_adr_out(31 downto 11) = b"000000000000000001000" then -- 0x4000
|
elsif p_adr_out(31 downto 11) = b"000000000000000001000" then -- 0x4000
|
active_module <= MODULE_GPIO1;
|
active_module <= MODULE_GPIO1;
|
ad_state <= BUSY;
|
ad_state <= BUSY;
|
elsif p_adr_out(31 downto 11) = b"000000000000000001001" then -- 0x4800
|
elsif p_adr_out(31 downto 11) = b"000000000000000001001" then -- 0x4800
|
active_module <= MODULE_GPIO2;
|
active_module <= MODULE_GPIO2;
|
ad_state <= BUSY;
|
ad_state <= BUSY;
|
elsif p_adr_out(31 downto 11) = b"000000000000000001010" then -- 0x5000
|
elsif p_adr_out(31 downto 11) = b"000000000000000001010" then -- 0x5000
|
active_module <= MODULE_UART;
|
active_module <= MODULE_UART;
|
ad_state <= BUSY;
|
ad_state <= BUSY;
|
elsif p_adr_out(31 downto 11) = b"000000000000000001011" then -- 0x5800
|
elsif p_adr_out(31 downto 11) = b"000000000000000001011" then -- 0x5800
|
active_module <= MODULE_TIMER;
|
active_module <= MODULE_TIMER;
|
ad_state <= BUSY;
|
ad_state <= BUSY;
|
else
|
else
|
active_module <= MODULE_DUMMY;
|
active_module <= MODULE_DUMMY;
|
ad_state <= BUSY;
|
ad_state <= BUSY;
|
end if;
|
end if;
|
|
else
|
|
active_module <= MODULE_NONE;
|
end if;
|
end if;
|
when BUSY =>
|
when BUSY =>
|
if p_cyc_out = '0' then
|
if p_cyc_out = '0' then
|
active_module <= MODULE_NONE;
|
active_module <= MODULE_NONE;
|
ad_state <= IDLE;
|
ad_state <= IDLE;
|
end if;
|
end if;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process address_decoder;
|
end process address_decoder;
|
|
|
module_mux: process(active_module, imem_ack_out, imem_dat_out, dmem_ack_out, dmem_dat_out,
|
module_mux: process(active_module, imem_ack_out, imem_dat_out, dmem_ack_out, dmem_dat_out,
|
gpio1_ack_out, gpio1_dat_out, gpio2_ack_out, gpio2_dat_out, uart_ack_out, uart_dat_out,
|
gpio1_ack_out, gpio1_dat_out, gpio2_ack_out, gpio2_dat_out, uart_ack_out, uart_dat_out,
|
timer_ack_out, timer_dat_out, dummy_ack_out, dummy_dat_out)
|
timer_ack_out, timer_dat_out, dummy_ack_out, dummy_dat_out)
|
begin
|
begin
|
case active_module is
|
case active_module is
|
when MODULE_IMEM =>
|
when MODULE_IMEM =>
|
p_ack_in <= imem_ack_out;
|
p_ack_in <= imem_ack_out;
|
p_dat_in <= imem_dat_out;
|
p_dat_in <= imem_dat_out;
|
when MODULE_DMEM =>
|
when MODULE_DMEM =>
|
p_ack_in <= dmem_ack_out;
|
p_ack_in <= dmem_ack_out;
|
p_dat_in <= dmem_dat_out;
|
p_dat_in <= dmem_dat_out;
|
when MODULE_GPIO1 =>
|
when MODULE_GPIO1 =>
|
p_ack_in <= gpio1_ack_out;
|
p_ack_in <= gpio1_ack_out;
|
p_dat_in <= gpio1_dat_out;
|
p_dat_in <= gpio1_dat_out;
|
when MODULE_GPIO2 =>
|
when MODULE_GPIO2 =>
|
p_ack_in <= gpio2_ack_out;
|
p_ack_in <= gpio2_ack_out;
|
p_dat_in <= gpio2_dat_out;
|
p_dat_in <= gpio2_dat_out;
|
when MODULE_UART =>
|
when MODULE_UART =>
|
p_ack_in <= uart_ack_out;
|
p_ack_in <= uart_ack_out;
|
p_dat_in <= (31 downto 8 => '0') & uart_dat_out;
|
p_dat_in <= (31 downto 8 => '0') & uart_dat_out;
|
when MODULE_TIMER =>
|
when MODULE_TIMER =>
|
p_ack_in <= timer_ack_out;
|
p_ack_in <= timer_ack_out;
|
p_dat_in <= timer_dat_out;
|
p_dat_in <= timer_dat_out;
|
when MODULE_DUMMY =>
|
when MODULE_DUMMY =>
|
p_ack_in <= dummy_ack_out;
|
p_ack_in <= dummy_ack_out;
|
p_dat_in <= dummy_dat_out;
|
p_dat_in <= dummy_dat_out;
|
when MODULE_NONE =>
|
when MODULE_NONE =>
|
p_ack_in <= '0';
|
p_ack_in <= '0';
|
p_dat_in <= (others => '0');
|
p_dat_in <= (others => '0');
|
end case;
|
end case;
|
end process module_mux;
|
end process module_mux;
|
|
|
end architecture behaviour;
|
end architecture behaviour;
|
|
|
