-- The Potato Processor - A simple processor for FPGAs
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-- The Potato Processor - A simple processor for FPGAs
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-- (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>
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-- (c) Kristian Klomsten Skordal 2015 <kristian.skordal@wafflemail.net>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity pp_soc_7seg is
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entity pp_soc_7seg is
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generic(
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generic(
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NUM_DISPLAYS : natural := 8; -- Number of 7-segment displays connected to the module.
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NUM_DISPLAYS : natural := 8; -- Number of 7-segment displays connected to the module.
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SWITCH_COUNT : natural; -- How many ticks of the input clock to count before switching displays.
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SWITCH_COUNT : natural; -- How many ticks of the input clock to count before switching displays.
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CATHODE_ENABLE_VALUE : std_logic := '0'; -- Value of the cathode output when enabled.
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CATHODE_ENABLE_VALUE : std_logic := '0'; -- Value of the cathode output when enabled.
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ANODE_ENABLE_VALUE : std_logic := '0' -- Value of the anode output when enabled.
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ANODE_ENABLE_VALUE : std_logic := '0' -- Value of the anode output when enabled.
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- Connections to the displays:
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-- Connections to the displays:
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seg7_anode : out std_logic_vector(NUM_DISPLAYS - 1 downto 0); -- One for each display
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seg7_anode : out std_logic_vector(NUM_DISPLAYS - 1 downto 0); -- One for each display
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seg7_cathode : out std_logic_vector(6 downto 0);
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seg7_cathode : out std_logic_vector(6 downto 0);
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-- Wishbone interface:
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-- Wishbone interface:
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wb_adr_in : in std_logic_vector( 0 downto 0);
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wb_adr_in : in std_logic_vector( 0 downto 0);
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wb_dat_in : in std_logic_vector(31 downto 0);
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wb_dat_in : in std_logic_vector(31 downto 0);
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wb_dat_out : out std_logic_vector(31 downto 0);
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wb_dat_out : out std_logic_vector(31 downto 0);
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wb_cyc_in : in std_logic;
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wb_cyc_in : in std_logic;
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wb_stb_in : in std_logic;
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wb_stb_in : in std_logic;
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wb_we_in : in std_logic;
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wb_we_in : in std_logic;
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wb_ack_out : out std_logic
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wb_ack_out : out std_logic
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);
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);
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end entity pp_soc_7seg;
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end entity pp_soc_7seg;
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architecture behaviour of pp_soc_7seg is
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architecture behaviour of pp_soc_7seg is
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signal ctrl_value : std_logic_vector(NUM_DISPLAYS * 4 - 1 downto 0);
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signal ctrl_value : std_logic_vector(NUM_DISPLAYS * 4 - 1 downto 0);
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signal ctrl_enable : std_logic_vector(NUM_DISPLAYS - 1 downto 0);
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signal ctrl_enable : std_logic_vector(NUM_DISPLAYS - 1 downto 0);
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type seg7_array is array (0 to NUM_DISPLAYS - 1) of std_logic_vector(6 downto 0);
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type seg7_array is array (0 to NUM_DISPLAYS - 1) of std_logic_vector(6 downto 0);
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signal output_array : seg7_array;
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signal output_array : seg7_array;
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subtype display_counter_type is natural range 0 to NUM_DISPLAYS - 1;
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subtype display_counter_type is natural range 0 to NUM_DISPLAYS - 1;
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signal active_display : display_counter_type := 0;
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signal active_display : display_counter_type := 0;
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constant ANODE_DISABLE_VALUE : std_logic := not ANODE_ENABLE_VALUE;
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constant ANODE_DISABLE_VALUE : std_logic := not ANODE_ENABLE_VALUE;
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subtype switch_counter_type is natural range 0 to SWITCH_COUNT - 1;
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subtype switch_counter_type is natural range 0 to SWITCH_COUNT - 1;
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signal switch_counter : switch_counter_type := 0;
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signal switch_counter : switch_counter_type := 0;
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signal anodes : std_logic_vector(NUM_DISPLAYS - 1 downto 0);
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signal anodes : std_logic_vector(NUM_DISPLAYS - 1 downto 0);
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-- Wishbone controller acknowledge signal:
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-- Wishbone controller acknowledge signal:
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signal ack : std_logic;
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signal ack : std_logic;
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begin
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begin
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assert NUM_DISPLAYS <= 8 and NUM_DISPLAYS > 0
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assert NUM_DISPLAYS <= 8 and NUM_DISPLAYS > 0
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report "Only 1 - 8 displays are supported by the 7-seg module!"
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report "Only 1 - 8 displays are supported by the 7-seg module!"
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severity FAILURE;
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severity FAILURE;
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-- Connect display outputs:
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-- Connect display outputs:
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seg7_cathode <= output_array(active_display) when CATHODE_ENABLE_VALUE = '0' else not output_array(active_display);
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seg7_cathode <= output_array(active_display) when CATHODE_ENABLE_VALUE = '0' else not output_array(active_display);
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seg7_anode <= anodes;
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seg7_anode <= anodes and not ctrl_enable when ANODE_ENABLE_VALUE = '1' else anodes and ctrl_enable;
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-- Create one decoder for each display:
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-- Create one decoder for each display:
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generate_decoders: for i in 0 to NUM_DISPLAYS - 1
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generate_decoders: for i in 0 to NUM_DISPLAYS - 1
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generate
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generate
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decoder: entity work.pp_seg7dec
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decoder: entity work.pp_seg7dec
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port map(
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port map(
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input => ctrl_value(i * 4 + 3 downto i * 4),
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input => ctrl_value(i * 4 + 3 downto i * 4),
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output => output_array(i)
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output => output_array(i)
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);
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);
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end generate;
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end generate;
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-- Switch between the displays:
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-- Switch between the displays:
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switch_displays: process(clk)
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switch_displays: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if reset = '1' then
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if reset = '1' then
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anodes <= (0 => ANODE_ENABLE_VALUE, others => ANODE_DISABLE_VALUE);
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anodes <= (0 => ANODE_ENABLE_VALUE, others => ANODE_DISABLE_VALUE);
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active_display <= 0;
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active_display <= 0;
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else
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else
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if switch_counter = SWITCH_COUNT - 1 then
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if switch_counter = SWITCH_COUNT - 1 then
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anodes <= std_logic_vector(rotate_left(unsigned(anodes), 1));
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anodes <= std_logic_vector(rotate_left(unsigned(anodes), 1));
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switch_counter <= 0;
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switch_counter <= 0;
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if active_display = NUM_DISPLAYS - 1 then
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if active_display = NUM_DISPLAYS - 1 then
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active_display <= 0;
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active_display <= 0;
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else
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else
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active_display <= active_display + 1;
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active_display <= active_display + 1;
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end if;
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end if;
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else
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else
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switch_counter <= switch_counter + 1;
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switch_counter <= switch_counter + 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process switch_displays;
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end process switch_displays;
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----- Wishbone controller: -----
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----- Wishbone controller: -----
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wb_ack_out <= ack and wb_cyc_in and wb_stb_in;
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wb_ack_out <= ack and wb_cyc_in and wb_stb_in;
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wishbone: process(clk)
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wishbone: process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if reset = '1' then
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if reset = '1' then
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ctrl_value <= (others => '0');
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ctrl_value <= (others => '0');
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ctrl_enable <= (others => '1');
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ctrl_enable <= (others => '1');
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wb_dat_out <= (others => '0');
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wb_dat_out <= (others => '0');
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ack <= '0';
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ack <= '0';
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else
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else
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if wb_cyc_in = '1' and wb_stb_in = '1' and ack = '0' then
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if wb_cyc_in = '1' and wb_stb_in = '1' and ack = '0' then
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if wb_we_in = '1' then
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if wb_we_in = '1' then
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case wb_adr_in is
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case wb_adr_in is
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when b"0" =>
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when b"0" =>
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ctrl_enable <= wb_dat_in(NUM_DISPLAYS - 1 downto 0);
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ctrl_enable <= wb_dat_in(NUM_DISPLAYS - 1 downto 0);
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when b"1" =>
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when b"1" =>
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ctrl_value <= wb_dat_in(NUM_DISPLAYS * 4 - 1 downto 0);
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ctrl_value <= wb_dat_in(NUM_DISPLAYS * 4 - 1 downto 0);
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when others =>
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when others =>
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end case;
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end case;
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ack <= '1';
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ack <= '1';
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else
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else
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case wb_adr_in is
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case wb_adr_in is
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when b"0" =>
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when b"0" =>
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wb_dat_out <= std_logic_vector(resize(unsigned(ctrl_enable), wb_dat_out'length));
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wb_dat_out <= std_logic_vector(resize(unsigned(ctrl_enable), wb_dat_out'length));
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when b"1" =>
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when b"1" =>
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wb_dat_out <= std_logic_vector(resize(unsigned(ctrl_value), wb_dat_out'length));
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wb_dat_out <= std_logic_vector(resize(unsigned(ctrl_value), wb_dat_out'length));
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when others =>
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when others =>
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end case;
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end case;
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ack <= '1';
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ack <= '1';
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end if;
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end if;
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elsif wb_stb_in = '0' then
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elsif wb_stb_in = '0' then
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ack <= '0';
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ack <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process wishbone;
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end process wishbone;
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end architecture behaviour;
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end architecture behaviour;
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