-- The Potato Processor - A simple processor for FPGAs
|
-- The Potato Processor - A simple processor for FPGAs
|
-- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
|
-- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net>
|
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
|
-- Report bugs and issues on <http://opencores.org/project,potato,bugtracker>
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
|
|
use work.pp_types.all;
|
use work.pp_types.all;
|
|
|
entity pp_alu is
|
entity pp_alu is
|
port(
|
port(
|
x, y : in std_logic_vector(31 downto 0);
|
x, y : in std_logic_vector(31 downto 0);
|
result : out std_logic_vector(31 downto 0);
|
result : out std_logic_vector(31 downto 0);
|
operation : in alu_operation
|
operation : in alu_operation
|
);
|
);
|
end entity pp_alu;
|
end entity pp_alu;
|
|
|
architecture behaviour of pp_alu is
|
architecture behaviour of pp_alu is
|
begin
|
begin
|
|
|
calculate: process(operation, x, y)
|
calculate: process(operation, x, y)
|
begin
|
begin
|
case operation is
|
case operation is
|
when ALU_AND =>
|
when ALU_AND =>
|
result <= x and y;
|
result <= x and y;
|
when ALU_OR =>
|
when ALU_OR =>
|
result <= x or y;
|
result <= x or y;
|
when ALU_XOR =>
|
when ALU_XOR =>
|
result <= x xor y;
|
result <= x xor y;
|
when ALU_SLT =>
|
when ALU_SLT =>
|
if signed(x) < signed(y) then
|
if signed(x) < signed(y) then
|
result <= (0 => '1', others => '0');
|
result <= (0 => '1', others => '0');
|
else
|
else
|
result <= (others => '0');
|
result <= (others => '0');
|
end if;
|
end if;
|
when ALU_SLTU =>
|
when ALU_SLTU =>
|
if unsigned(x) < unsigned(y) then
|
if unsigned(x) < unsigned(y) then
|
result <= (0 => '1', others => '0');
|
result <= (0 => '1', others => '0');
|
else
|
else
|
result <= (others => '0');
|
result <= (others => '0');
|
end if;
|
end if;
|
when ALU_ADD =>
|
when ALU_ADD =>
|
result <= std_logic_vector(unsigned(x) + unsigned(y));
|
result <= std_logic_vector(unsigned(x) + unsigned(y));
|
when ALU_SUB =>
|
when ALU_SUB =>
|
result <= std_logic_vector(unsigned(x) - unsigned(y));
|
result <= std_logic_vector(unsigned(x) - unsigned(y));
|
when ALU_SRL =>
|
when ALU_SRL =>
|
result <= std_logic_vector(shift_right(unsigned(x), to_integer(unsigned(y(4 downto 0)))));
|
result <= std_logic_vector(shift_right(unsigned(x), to_integer(unsigned(y(4 downto 0)))));
|
when ALU_SLL =>
|
when ALU_SLL =>
|
result <= std_logic_vector(shift_left(unsigned(x), to_integer(unsigned(y(4 downto 0)))));
|
result <= std_logic_vector(shift_left(unsigned(x), to_integer(unsigned(y(4 downto 0)))));
|
when ALU_SRA =>
|
when ALU_SRA =>
|
result <= std_logic_vector(shift_right(signed(x), to_integer(unsigned(y(4 downto 0)))));
|
result <= std_logic_vector(shift_right(signed(x), to_integer(unsigned(y(4 downto 0)))));
|
when others =>
|
when others =>
|
result <= (others => '0');
|
result <= (others => '0');
|
end case;
|
end case;
|
end process calculate;
|
end process calculate;
|
|
|
end architecture behaviour;
|
end architecture behaviour;
|
|
|
